Int
ern
at
i
onal
Journ
al of
P
ower E
le
ctr
on
i
cs a
n
d
Drive
S
ystem
(I
J
PE
D
S
)
Vo
l.
11
,
No.
2
,
June
2020
,
pp.
8
2
3
~
8
2
6
IS
S
N:
20
88
-
8694
,
DOI: 10
.11
591/
ij
peds
.
v
1
1
.i
2
.
pp
8
2
3
-
8
2
6
823
Journ
al h
om
e
page
:
http:
//
ij
pe
ds
.i
aescore.c
om
A
ne
w g
ate dri
ve for a si
ngle
-
ph
ase m
atr
i
x convert
er
Rahimi
Bahar
om
1
, N
or
F
ar
ahaid
a Abd
ul
Rahma
n
2
, Mu
ha
m
ad
N
ab
il
Hidaya
t
3
, Kh
ai
rul Sa
fuan
Muhamm
ad
4
,
Moham
ma
d
Naw
aw
i
Sero
j
i
5
,
N
or
Zaih
ar
Yah
aya
6
1,2
,3,4
,5
Facul
ty
of
Elec
tr
ical Engi
n
ee
ring
,
Univ
ersiti
T
eknol
ogi
MA
RA,
Mala
ysi
a.
6
Depa
rtment of
El
e
ct
ri
ca
l
&
Ele
ct
roni
cs
Engi
n
eering,
Univ
ersit
i
Te
knologi PETR
ON
AS
,
Mala
ysia
Art
ic
le
In
f
o
ABSTR
A
CT
Art
ic
le
history:
Re
cei
ved
Oct
2
7
, 201
9
Re
vised
Dec
1
2
, 2
01
9
Accepte
d
Ja
n
1
3
,
2020
Thi
s
pape
r
pre
se
nts
the
n
ew
generat
ion
of
adva
n
c
ed
gate
driv
er
c
i
rcu
it
b
ase
d
on
IR2110
devi
ce
for
a
Singl
e
-
Phase
Matri
x
Convert
er
(SP
MC)
ci
rcu
i
t
topol
ogy
that
uses
MO
SF
ET
s
or
IGBTs
sw
it
che
s
.
Th
e
new
gen
erati
on
of
gate
drive
ci
rcu
it
use
s
le
ss
numbe
r
of
com
pone
nts,
si
nce
a
singl
e
IR2
110
devic
e
ca
n
dr
ive
two
p
ower
sw
it
che
s
,
t
hus
red
uce
pow
er
losses
and
m
ini
mize
the
com
pl
exi
ty
of
c
onvent
ion
al
ci
r
c
uit
.
An
addition
al
isolation
of
th
e
upp
er
and
lower
sid
es
of
I
R2110
device
fe
at
ure
s
additional
prot
ec
t
ion
to
th
e
proposed
gat
e
dr
ive
sys
tem.
As
a
r
esult
,
t
he
proposed
ga
t
e
drive
ci
r
cui
t
j
ust
uses
four
IR2110
gate
dri
ves
in
orde
r
to
c
ontrol
e
ight
sw
itches
of
SP
MC
c
irc
uit,
thus,
solve
the
conv
en
ti
onal
bulky
g
ate
drive
ci
r
cui
t
pro
ble
m
in
SP
M
Cs
oper
ation.
Thi
s
is
in
li
ne
w
it
h
the
in
te
rn
at
io
nal
power
elec
tr
onic
technology
roa
d
-
ma
ps
to
red
uc
e
losses
,
cost
,
volu
me
,
the
ref
or
e
to
rai
s
e
up
th
e
power
densit
y
of
power
elec
tronics
converte
rs.
Vali
da
ti
on
h
ave
bee
n
done
th
rough
the
expe
ri
me
nt
al
te
s
t
-
rig
.
As
a
resul
t
,
such
n
ew
the
or
et
i
ca
l
enha
n
cem
ent
s
c
an
be
used
as
a
novel
founda
ti
on
of
f
uture
high
power
d
ensit
y
of
S
PM
C
ci
rcu
i
t
topol
ogy
and
in
-
li
ne
w
it
h
the
F
ourth
Industri
al
Revol
uti
on
(IR
4.
0)
which
were
cha
ra
cteri
z
ed
m
ai
nly
by
ad
vanc
es
in te
chno
logy.
Ke
yw
or
d
s
:
Gate d
rive
r
ci
r
cuit
Power de
ns
it
y
Sing
le
-
phase
matri
x
c
onve
rt
er
This
is an
open
acc
ess arti
cl
e
un
der
the
CC
BY
-
SA
l
ic
ense
.
Corres
pond
in
g
Aut
h
or
:
Ra
himi Ba
ha
rom,
Faculty
of Elec
tric
al
Engineer
ing
,
Un
i
ver
sit
i Te
knol
og
i
MARA
,
40450 S
hah A
l
am, S
el
a
ngor,
M
al
aysia.
Emai
l:
r
ahimi
6579
@gmai
l.co
m
1.
INTROD
U
CTION
M
at
rix
Co
nve
rters
(
M
C)
ha
ve
bee
n
cl
ass
ifie
d
as
an
a
dv
a
nce
d
a
nd
emer
ging
c
on
ver
te
r
[1
-
2].
The
SP
M
C
as
sh
ow
n
in
Fig
ure
1
c
on
sist
s
of
f
our
bi
-
direct
ion
al
s
witc
hes
that
inter
face
with
thei
r
in
pu
t
and
ou
t
pu
t
te
r
min
al
s
[3
-
11]
.
I
n
order
t
o
f
ulf
il
the
desig
n
of
high
performa
nce
an
d
hi
gh
-
sp
ee
d
s
witc
hing
app
li
cat
io
ns
,
I
GBTs
or
M
O
SFETs
hav
e
be
en
em
ployed
.
Figure
2
s
ho
ws
the
to
polo
gy
of
S1
a
nd
S2
us
in
g
IG
BTs
c
onnec
te
d
i
n
c
ommo
n
-
e
mit
te
r
(c
om
mon
-
E
)
[
12
-
13].
Since
the
S
PM
C
use
s
ei
ght
s
witc
hes
,
he
nce,
it
requires
ei
ght
gate
dr
i
ver
ci
r
cuits.
The
us
e
of
high
-
powe
r
transist
or
s
c
ou
l
d
le
ad
to
t
he
us
e
of
gate
dr
ive
ci
rcu
it
s
with
a
functi
on
of
po
wer
am
plifie
r
t
hat
can
acce
pt
low
-
pow
er
in
put
for
pr
oducin
g
hi
gh
vo
lt
a
ge
dr
i
ve
ou
t
pu
t.
G
at
e
dr
ivers
ca
n be
pr
ov
i
ded eit
her o
n
-
c
hip o
r
as
a
discrete m
od
ule.
A
c
onve
ntion
a
l
gate
dri
ve
ci
rcu
it
is
on
l
y
c
apab
le
t
o
c
on
t
ro
l
a
si
ng
le
s
witc
h,
res
ulti
ng
in
bulk
y
conve
rsion
sys
te
m
[14
-
17].
It
al
so
requires
sever
al
numb
e
rs
of
el
ect
ronic
com
pone
nts;
thu
s
,
it
cou
l
d
le
ad
to
high
l
os
ses
a
nd
reduces
the
eff
ic
ie
nc
y
of
t
he
S
P
M
C
s
ys
t
em.
More
over,
ad
diti
on
al
pr
otect
ion
de
vic
es
are
require
d
in
orde
r
t
o
protect
the
powe
r
s
witc
hes.
Re
ce
ntly
,
powe
r
el
ect
r
on
ic
c
onve
rter
s
siz
e
and
wei
gh
t
a
re
crit
ic
al
wh
e
n
s
pace
is
c
onstra
ints
[
18
-
19].
T
her
e
fore,
an
al
te
rn
at
ive
te
c
hnology
to
s
ol
ve
the
a
foreme
ntion
e
d
pro
blems
are
desira
ble.
I
n
t
his
pa
per,
a
ne
w
gate
dr
i
ve
base
d
IR
2110
is
propose
d
f
or
t
he
SP
M
C
ci
rcu
it
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2088
-
8
694
In
t J
P
ow
Ele
c
&
Dr
i
S
ys
t
,
V
ol
.
1
1
, N
o.
2
,
J
un
e
2020
:
8
2
3
–
8
2
6
824
topolo
gy
;
to
in
crease
the
SP
M
C
powe
r
de
nsi
ty.
It
i
nh
e
rits
sim
ple
ci
rc
uit
de
sig
n
with
le
ss
numb
e
r
of
de
vice
s
us
e
d.
T
hus,
it
may
s
olv
e
the
siz
e
and
l
os
ses
issues
in
SP
MC
.
The
refor
e
,
t
he
ne
w
gate
dr
ive
ci
rcu
it
is
i
n
li
ne
with
t
he
po
we
r
el
ect
r
onic
s
te
chnolo
gy
r
oadmap
that
te
nds
to
re
duce
siz
e
,
vo
l
um
e
,
l
os
s
es
a
nd
c
os
t
of
fu
t
ur
e
powe
r
c
onver
t
er [2
0].
S
4
b
a
L
o
a
d
S
2
b
S
3
b
S
1
b
S
3
a
S
1
a
S
4
a
S
2
V
s
I
G
B
T
I
G
B
T
D
I
O
D
E
D
I
O
D
E
C
u
r
r
e
n
t
F
l
o
w
C
u
r
r
e
n
t
F
l
o
w
S
1
a
S
1
b
Figure
1.
SP
MC
circuit t
op
olo
gy
Figure
2.
S
witc
hes
a
rr
a
ngeme
nt
2.
THE
PR
OPO
SED GATE
D
RIV
E
C
I
R
CUIT FO
R
SP
M
C
The
de
vice
of
IR2110
at
the
hear
t
of
the
se
cond
ge
ner
at
i
on
of
gate
dri
ve
ci
rcu
it
ca
n
wit
h
sta
nd
up
to
500
V
[
21
-
24
]
.
The
propose
d
gate
dr
ive
ba
sed
on
IR
2110
al
lows
a
l
ow
cu
rr
e
nt
outp
ut
sign
al
from
a
5
V
sign
al
ge
ne
rated
by
a
micr
opr
ocess
or
or
micr
oc
on
t
ro
ll
er
t
o
dri
ve
M
O
SFET
s
a
nd
I
GBTs
ope
rati
on.
The
IR
2110
dri
ver
co
ns
ist
s
of
a
le
vel
-
s
hiftin
g
ci
rcu
it
r
y
a
nd
a
bootstra
p
ci
r
cuit
to
al
low
th
e
po
wer
s
witc
he
s
to
tur
n
ON.
Addi
ti
on
al
ly,
the
ga
te
capaci
ta
nce
of
MOS
FETs
or
I
GBTs
nee
d
to
be
c
harge
d
an
d
discha
rge
d
for
them
to
t
urn
ON
a
nd
tu
rn
OF
F
res
pecti
ve
ly.
Hi
gher
c
urre
nt
pro
vid
e
s
to
the
gate
(si
nk
/s
ource
)
wil
l
cause
the
switc
hi
ng
act
ivit
y
of
MO
SFETs
or
IG
B
Ts
bec
om
e
fas
te
r.
To
a
void
t
he
ris
k
of
dam
agin
g
the
MO
SFET,
the g
at
e
dri
ve must
be desig
ne
d
to
s
upply l
ow c
urre
nt at a
ppr
opriat
e volt
a
ge
le
vel.
Figure
3
sho
ws
the
e
xperi
mental
te
st
-
rig
and
t
he
sc
he
mati
c
diagr
a
m
of
t
he
ad
va
nc
e
gate
dri
ve
sy
ste
m.
T
he
I
R211
0
de
vice
receives
in
put
sign
al
s
in
a
f
orm
of
P
ulse
Wi
dth
M
od
ulati
on
(PW
M
)
th
r
ough
th
e
pin
12
for
lo
w
side
input
an
d
the
pin
10
for
high
side
in
put
sign
al
s.
T
hes
e
IR2110
are
c
onnected
t
o
th
e
DC
su
ppl
y
vo
lt
age
thr
ough
a
n
i
so
la
te
d
N
M
A
0515
dev
ic
e
[
21].
The
IR
2110
will
boos
t
the
in
pu
t
sign
al
of
the
co
ntr
ol
ci
r
cuit
is
from
5
V,
t
o
the
outp
ut
of
15
V
.
T
he
TC4
422
de
vice
is
us
e
d
to
fi
lt
er
the
noise
a
nd
f
or
so
ft
dri
ve
r
ope
rati
on.
T
he
us
e
of
the
pro
pos
ed
dri
ve
ci
rc
uit
will
cut
the
num
ber
of
re
quired
dr
ive
ci
rc
ui
ts
of
the
S
PM
C
f
rom
ei
ght
to
4
ci
rcu
it
s
only.
T
hus,
it
re
du
ce
s
t
he
num
ber
of
com
pone
nts
a
nd
ci
rc
uit
c
omplexit
ie
s
for
ac
hieving l
ow po
wer
l
os
s
es an
d
high
-
po
wer
de
ns
it
y sy
ste
m [25].
Table
1
sho
w
s
the
numb
e
r
of
gate
dr
i
ve
ci
rcu
it
s
t
hat
c
onnected
t
o
t
he
H
I
GH
a
nd
LO
W
si
des
te
rmin
al
s
of
t
he
SP
M
C
ci
rc
uit
topolo
gy;
they
are
la
belle
d
as
S
1a,
S
1b,
S
2a,
S
2b,
S3
a,
S3b,
S
4a
,
S4b.
Sw
i
tc
hes
t
hat
hav
e
bee
n
co
nnect
ed
to
t
he
HIGH
side
te
r
minal
are
S
1a,
S1b,
S
2a
a
nd
S
2b,
w
hile
switc
hes
tha
t
hav
e
bee
n
co
nnect
ed
to
t
he
LO
W
side
te
r
minal
are
S
3a,
S3b,
S
4a
a
nd
S4b.
S
o,
for
t
he
gate
dr
i
ve
1,
it
has
been
co
nnect
e
d
to
the
pair
of
s
witc
hes
S1
a
an
d
S
3a.
M
ea
nwhile
,
the
ga
te
dr
i
ve
2,
has
bee
n
c
onnect
ed
to
the
pai
r
of
swit
ches
S1b
a
nd
S
3b.
T
he
n,
f
or
t
he
gate
dr
ive
3,
it
has
bee
n
co
nn
ect
e
d
t
o
the
pair
of
s
witc
he
s
S
2a
and S
4a.
Last
ly,
t
he gate
driv
e 4
has
b
ee
n
c
onnecte
d
to
the
pair of
s
witc
he
s S2b
a
nd S
4
b.
Table
1.
Ci
rc
ui
t Arran
geme
nt
Sid
es
Gate D
rive 1
Gate D
rive 2
Gate D
rive 3
Gate D
rive 4
HIGH
S1
a
S1
b
S2
a
S2
b
LOW
S3
a
S3
b
S4
a
S4
b
3.
RESU
LT
S
A
ND
DI
SCUS
S
ION
S
Figure
4
sho
ws
the
ex
per
ime
nt
resu
lt
of
the
outp
ut
PWM
si
gnal
.
I
n
order
t
o
ver
if
y
the
pro
po
s
ed
gate
dr
i
ve
ci
rcu
it
f
or
t
he
SP
M
C
ci
rcu
it
t
opolog
y,
a
sim
ple
in
ve
rter
operati
on
has
bee
n
te
ste
d.
T
he
P
WM
s
ign
al
s
(PWM
1
an
d
PWM
2)
are
f
ed
t
o
the
M
OSFETs
acco
r
ding
t
o
the
switc
hi
ng
al
gorith
ms
ta
bula
te
d
in
T
able
2.
The
outp
ut
vo
l
ta
ge
wav
e
form
f
or
the
i
nverte
r
op
e
rati
on
is
a
s
sho
wn
in
Fig
ur
e
5.
It
s
hows
that
the
ou
t
put
A
C
vo
lt
age
w
ave
f
orm
f
ollo
ws
t
he
sh
a
pe
of
the
PWM
si
gn
al
s
.
In
ad
diti
on,
the
fr
e
quenc
y
of
t
he
ou
t
pu
t
A
C
vo
lt
age
wav
e
f
or
m
ca
n
be
directl
y
con
t
ro
ll
ed
by
va
r
ying
t
he
fr
e
qu
e
nc
y
of
the
P
W
M
sig
nals.
I
n
t
his
work
,
the max
i
mum f
reque
ncy
of
t
he
p
r
opos
e
d gate dr
i
ve
ci
rc
uit can b
e i
ncr
ea
se
d
up to 1
00
kH
z. Thus,
it
is sui
ta
ble
for
me
dium a
nd
high
fr
e
qu
e
nc
y powe
r
el
ec
tro
nics c
onve
rters
op
e
rati
on.
Evaluation Warning : The document was created with Spire.PDF for Python.
In
t J
P
ow Elec
& Dri S
ys
t
IS
S
N:
20
88
-
8
694
A n
ew
gate
dri
ve for
a
si
ng
le
-
phas
e
matri
x c
on
ve
rte
r
(R
ahimi B
aharom
)
825
Figure
3
.
Ci
rcui
t arrange
ment
for
e
xp
e
rime
ntal t
est
-
rig
Figure
4
.
Ex
pe
rimental
resu
lt
of the
outp
ut P
W
M
sig
nal
for
the pr
opos
e
d o
f gate
drive
ci
r
cuit. (
Scal
e:
X
axis: 1
5V/div
, Y
axis: 5
0µs/di
v)
Table
2.
Sw
it
c
hing alg
ori
thm
s for
t
he DC t
o AC c
onve
rter
of the
SP
M
C c
ircuit
to
po
l
ogy
Mod
e of
Op
eration
Switch
e
s
PW
M
Op
eration
Po
sitiv
e cycle
S1
a
PW
M
1
-
S1
b
OFF
-
S2
a
OFF
Neg
ativ
e cycle
S2
b
PW
M
2
-
S3
a
OFF
Neg
ativ
e cycle
S3
b
PW
M
2
Po
sitiv
e cycle
S4
a
PW
M
1
-
S4
b
OFF
Figure
5
.
Ex
pe
rimental
resu
lt
of the
outp
ut volt
age
wav
e
f
orm for
the
DC t
o AC c
onver
te
r of
t
he
S
P
M
C
ci
rcu
it
to
po
l
ogy (Scale
: X
ax
i
s: 1
5V
/
div
,
Y a
xis: 2
0µs/di
v)
4.
CONCL
US
I
O
N
The
ne
w
ge
ne
rati
on
of
a
dv
a
nced
gate
dri
ve
ci
rcu
it
that
cou
l
d
reduce
t
he
numb
e
r
of
com
pone
nts
us
e
d,
th
us
,
i
ncrea
se
the
pow
er
den
sit
y
of
SP
M
C
ci
rc
uit
has
been
pr
e
sente
d.
T
his
is
in
li
ne
with
the
inc
r
easi
ng
dema
nd
for
s
mall
er
siz
e,
li
gh
t
in
weig
ht
an
d
high
e
f
f
ic
ie
ncy
co
nve
rters
in
rece
nt
yea
rs,
ca
us
e
d
by
the
co
ntin
ual
de
velo
pm
e
nt
of
powe
r
de
ns
it
y
for
power
el
ect
ronic
c
onver
te
r
s.
T
he
propose
d
gate
dri
ve
ci
rcu
it
capab
le
to
e
nhance
the
reli
ab
il
it
y
of
t
he
SP
M
C
ci
rcu
it
.
A
dd
it
io
nal
is
olati
on
be
twee
n
hi
gh
a
nd
l
ow
si
des
of
powe
r
s
witc
he
s
co
nnect
ion
from
IR
2110
dev
ic
es
co
uld
le
a
d
t
o
high
rob
us
tne
ss
pe
rfo
rma
nc
e
of
the pr
opos
e
d
s
ys
te
m.
Evaluation Warning : The document was created with Spire.PDF for Python.
IS
S
N
:
2088
-
8
694
In
t J
P
ow
Ele
c
&
Dr
i
S
ys
t
,
V
ol
.
1
1
, N
o.
2
,
J
un
e
2020
:
8
2
3
–
8
2
6
826
ACKN
OWLE
DGE
MENTS
Finan
ci
al
sup
port
from
In
s
ti
tute
of
Re
se
arch
M
an
age
ment
an
d
I
nnov
at
io
n
(
IRMI)
U
niv
e
rsit
i
Tek
no
l
og
i
MA
RA Gra
nt No:
600
-
IR
M
I/
DANA 5/
3/BEST
ARI (K
Y
)(001
/2019) is
grat
ef
ully ac
knowle
dge.
REFERE
NCE
S
[1]
D.
Var
aj
ão
,
e
t
a
l
.
,
“Modul
at
ion
S
tra
t
egy
f
or
a
Sin
gle
-
Stag
e
B
idi
r
e
ct
ion
al
and
Isola
te
d
AC
–
DC
Mat
rix
Conv
ert
e
r
fo
r
Ene
rgy
Stor
age
Sys
te
ms,”
I
EEE
Tr
ansacti
ons on Indus
trial
E
le
c
tronic
s
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vo
l. 65, p
p.
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–
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Apr 2018.
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N.
T
aka
ok
a,
e
t
al
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,
“Isol
ated
Single
-
Phase
Matri
x
Conver
te
r
Us
ing
C
ent
er
-
Ta
pped
Tr
ansfo
rme
r
for
Pow
er
Dec
oupli
ng
Cap
abi
lity,
”
I
EE
E
Tr
ansacti
ons on
I
ndustry
Applications
,
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.
1523
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Zuc
ker
b
erg
er
,
et
a
l.
,
“Single
-
phase
matrix
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nver
te
r
,
”
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EE
Pr
oc.
—
Elec
t
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er
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Bah
aro
m,
et
a
l.
,
“A
high
po
wer
factor
bid
irecti
on
al
b
at
t
ery
c
har
ger
using
sin
gle
-
phase
matrix
conve
rt
er,”
201
5
IEE
E
10th
Conf
ere
nce on
Indust
rial
Elec
tronic
s
and
Applications (ICIE
A)
,
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.
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97
-
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[5]
A.
Idris,
e
t
al
.
,
“Studi
es
on
per
forma
nc
e
of
Proportiona
l
Int
e
gra
l
and
Hys
te
resis
Control
in
Curre
nt
Control
Loop
for
ACD
C
conv
ert
er
using
SP
MC
fed
PM
DC
Motor,
”
2014
I
EEE
Int
ernati
onal
Confe
renc
e
on
Powe
r
and
Ene
r
gy
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Con)
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.
[6]
R.
Bah
aro
m,
et
al.
,
“A
new
sa
fe
-
com
mutat
ion
t
e
chni
que
for
AC
-
DC
conve
rt
er
op
era
t
ion
using
sin
gle
-
phase
matrix
conve
rt
er”,
2012
IEEE
In
te
rnatio
nal
Conf
ere
nce
on
Powe
r and
E
nergy
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ECon)
,
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12.
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R.
B
aha
ro
m,
et
al
.
,
“Adva
nc
ed
singl
e
-
phase
A
C
-
DC
conve
rte
r
using
single
-
ph
ase
matrix
conv
ert
er
topol
ogy,
”
Inte
rnational
Co
nfe
renc
e
on
Elec
tric
al
,
Control
a
nd
Computer
En
gine
ering
2011
(
InECCE
)
,
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33
-
38,
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.
[8]
R.
B
aha
ro
m,
e
t
al.
,
“Studi
es
on
safe
-
commutatio
n
sw
it
ch
ing
seq
uenc
e
for
cont
ro
ll
ed
re
ctifie
r
op
e
rat
ion
of
Singl
e
-
Phase
Matri
x
Co
nver
te
r
,
”
2009
I
EE
E
Symposium on
Industria
l
E
l
ec
troni
cs
&
App
li
cations
,
pp
.
12
8
-
133,
2009
.
[9]
R.
B
aha
ro
m,
e
t
al
.
,
“Boost
recti
fier
using
sing
le
-
phase
ma
tr
ix
conve
rt
er
with
bipol
ar
outpu
t,”
2008
IE
EE
2n
d
Inte
rnational
Po
wer
and
En
ergy
Confe
renc
e
,
pp.
1141
-
1146,
200
8.
[10]
R.
Baha
ro
m,
et
al.
,
“A
New
Single
-
Phase
Contr
oll
ed
R
ec
t
ifi
er
Us
ing
Single
-
Phase
Matri
x
Conv
ert
er
,
”
2006
I
EEE
Inte
rnational
Po
wer
and
En
ergy
Confe
renc
e
,
pp.
1477
-
1482,
200
6.
[11]
M.
Q.
I
.
M.
Z
amani,
et
al
.
,
“Concept
ua
l
study
on
Grid
-
to
-
Vehicle
(G2V
)
wire
l
ess
power
t
ran
sfer
u
sing
singl
e
-
phas
e
mat
rix
conve
rt
er
,
”
Inte
rnat
ional
Journal
of
Pow
er
Elec
tronic
s
a
nd
Dr
iv
e
Syst
e
ms
(IJ
PE
DS)
,
v
ol.
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3,
p
p.
1382
-
1388,
Sept
2019.
[12]
F.
Fang,
et
a
l.
,
“Fini
te
Control
Set
Model
Pr
edicti
v
e
Contro
l
fo
r
AC
-
DC
Matrix
Converter
wit
h
Virtual
Spac
e
Vec
tors,
”
IE
EE
Jour
nal
of
Eme
r
ging
and
S
elec
t
e
d
Topics
in
Pow
er
Elec
troni
cs
,
p
p.
1
-
13
,
Aug 201
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[13]
P.
Whe
e
le
r
,
e
t
al
.
,
“Ma
tri
x
converte
rs:
a
technolo
gy
rev
ie
w
,
”
I
EEE
Tr
ansacti
ons
on
Industrial
Elec
troni
cs
,
vol
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9,
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2
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276
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U.
Nasir,
et
al
.
,
“A
L
ea
k
age
-
In
duct
an
ce
-
To
le
r
a
nt
Comm
u
ta
t
ion
Strategy
for
Is
ola
t
ed
AC/AC
Convert
ers,”
I
E
EE
Journal
of
Eme
r
ging
and
S
elec
t
e
d
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er
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et
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.
,
“G
at
e
Dr
ive
rs
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-
Freque
ncy
Applicati
on
of
Sili
con
-
Carbi
d
e
MO
SF
ET
s:
Desig
n
conside
ra
ti
ons
f
or
fast
er
growth
of
LV
and
MV
applic
at
ions,
”
I
EE
E
Pow
er
Ele
ct
ronics
Magazi
ne
,
vol.
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–
31,
Sept
2019.
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A.
Bind
ra;
“Re
c
ent
Advanc
es
in
Gate
Drive
r
In
tegrat
ed
C
irc
ui
ts
f
or
W
ide
-
B
andgap
FETs:
Manuf
a
ct
ure
rs
in
troduc
e
gat
e
driv
ers
fo
r
squee
zi
ng
th
e
be
st
per
for
ma
n
ce
out
of
WBG
d
e
vic
es,
”
IEEE
Po
wer
E
le
c
tronic
s
Magazine
,
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32
–
38
,
Sept
2019.
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M.
Yuhendri
,
e
t
al
.
,
“Dir
ec
t
T
orque
Contro
l
Strat
egy
of
PM
SM
Em
ployi
ng
Ultra
Sparse
Matri
x
Conv
erter,
”
Inte
rnational
Jo
urnal
of Powe
r
El
e
ct
ronics
and
Dr
iv
e
Syst
ems (I
JP
EDS)
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A.
Sangwongw
a
nic
h,
e
t
a
l.
,
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ontrol
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e
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Phase
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Thr
ee
-
Phas
e
DC/AC
Converters,”
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e
ct
ronic
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[19]
R.
Sasika
la
an
d
R.
Seyez
h
ai,
“Re
v
ie
w
of
A
C
-
DC
power
e
l
ec
tron
ic
conve
r
t
er
topo
logi
es
f
or
power
f
actor
cor
recti
on
,
”
Inter
nati
onal
Journal
of
Pow
er
E
lectronic
s
and
Dr
i
ve
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ems
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PE
DS)
,
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0
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2019.
[20]
S.
Morrison,
“
Analysis
of
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h
ybrid
seri
es
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al
l
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r
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nt
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ridge
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rt
er,”
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EE
Tr
ansacti
ons
on
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El
e
ct
ronics
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R.
Bah
aro
m
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e
t
al.
,
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ve
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a
G
at
e
D
rive
with
Over
c
urre
nt
Prote
ct
io
n
Circ
uit
using
IR2110
for
Fast
Sw
it
chi
ng
Ha
lf
-
Bridge
Conv
ert
e
r,
”
ARPN
Journ
al
of
Engi
n
ee
rin
g
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li
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ens,
“U
sing
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e
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ide
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ents
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orpor
ate
d
,
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exa
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[23]
F.
Hat
tori
,
“A
Novel
high
-
eff
i
c
ie
ncy
ga
te
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e
circui
t
for
nor
ma
ll
y
off
-
type
GaN
FET,”
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ansacti
ons
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9,
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Zh
ang,
et
al
.
,
“A
new
re
liable
su
ppli
ed
gate
dri
ve
ci
r
cui
t
for
S
CRs
with
bre
ak
over
d
iode
s
for
prote
c
ti
on,
”
200
4
IEE
E
Inte
rnat
io
nal
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on
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ts
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ms
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.
[25]
S.
Kaka
r,
e
t
al.
,
“A
nove
l
sing
l
e
-
phase
PWM
a
symme
trica
l
mu
lt
ilevel
inve
r
te
r
with
nu
mbe
r
of
sem
ic
onduc
to
r
sw
it
che
s
r
educti
on,
”
Int
ernati
on
al
Journal
of
P
ower
E
lectronics
and
Dr
iv
e
Sy
stems
(IJ
PE
DS)
,
vol
.
10,
no
,
3,
pp.
1133
-
1140
,
2019.
Evaluation Warning : The document was created with Spire.PDF for Python.