Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l. 5,
N
o
.
1
,
Ju
ly 20
14
, pp
. 56
~62
I
S
SN
: 208
8-8
6
9
4
56
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
A Novel Topology of Multile
vel In
vert
er with Redu
ced
Number of Switches and DC Sources
Nakul Th
omb
re, Ratika sin
g
h
Rawa
t,
Pri
y
ank
a
Rana, Umash
a
nk
ar S
School of
Electr
i
cal Engin
eer
ing,
VIT
University
,
Vellore Tamilnadu, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Feb 17, 2014
Rev
i
sed
May 17
, 20
14
Accepted
May 29, 2014
This paper
intro
duces new topo
log
y
of c
a
scade
d
m
u
ltilev
e
l in
v
e
rter
, wit
h
considerab
le
red
u
ction
in
the
nu
m
b
er
of switch
e
s and DC voltage sources
.
The proposed to
polog
y
is based
on as
y
m
m
e
trical m
u
ltil
evel inv
e
rter which
produces 21
lev
e
ls of ou
tput with th
e
use o
f
11
unidir
ectional switches,
3
diodes and 4
DC voltage sources. The adv
a
ntages of this topolog
y
ar
e
reduction in the number of switches (2 nos.)
and
gate driv
er circu
its (2 nos.),
reduction in the number of DC
sources
(2 nos
.) als
o
cos
t
, com
p
lexit
y
,
an
d
space r
e
quired
f
o
r hardware
is re
duced wi
thout s
acrif
icing
the
qu
alit
y
output
of the
inver
t
er
.
To redu
ce
the
THD further Level shifting
SPWM techniqu
es
s
u
ch as
P
D
, P
O
D & AP
OD are us
ed and
compar
ison is shown on
the basis of
THDs obtained
from the above SPWM t
echniques. Frequen
c
y
of car
rier
waves is 1KHz, and modulatio
n index
is 1.0. To valid
ate th
e proposed
topolog
y
the
cir
c
uit is
simulated
and verif
i
ed
b
y
us
ing MATLAB/Simulink.
Keyword:
21
l
e
vel
s
Asymmetric mu
ltilev
e
l
in
v
e
rter
Mu
ltilev
e
l in
v
e
rters
PW
M T
e
chn
i
qu
es
Tot
a
l
ha
rm
oni
c di
st
o
r
t
i
o
n
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Nak
u
l
T
h
om
bre,
Sch
ool
o
f
El
ec
t
r
i
cal
En
gi
neer
i
ng,
VIT Un
iv
ersity, Vellore,
Tam
i
l
n
adu,
I
n
di
a.
Em
a
il: n
a
k
1
2
8
9
00@g
m
ail.co
m
1.
INTRODUCTION
No
w-a
-
day
s
, i
n
i
n
dust
r
i
e
s,
po
we
r co
nve
r
s
i
on sy
st
em
s becom
e
ver
y
po
pul
ar a
n
d are
use
d
extensi
v
ely. The power c
o
nversion system
include
s
AC
-
D
C, DC
-AC
,
DC-
D
C, AC
-
A
C co
nv
ersi
o
n
s. M
a
ny
hi
g
h
an
d m
e
dium
vol
t
a
ge ap
pl
i
cat
i
ons re
q
u
i
re suc
h
p
o
we
r
con
v
er
si
o
n
sy
st
em
s. Those a
ppl
i
cat
i
o
ns are
HV
DC
t
r
ansm
i
ssi
on,
FAC
T
S
,
AC
/
D
C
dri
v
es,
rene
wabl
e e
n
er
gy
s
o
urces s
u
c
h
as
PV s
o
lar cells
, wind, fuel ce
lls etc.
[2]
-
[
4]
. T
h
i
s
p
a
per c
o
ncent
r
a
t
es on
DC
-
A
C
con
v
e
r
si
o
n
(
I
n
vert
er
act
i
o
n
)
.
A co
n
v
e
n
t
i
ona
l
si
ngl
e
phase
i
nve
rt
er
i
s
abl
e
t
o
pro
d
u
ce v
o
l
t
a
ge l
e
vel
s
of +
V
dc
, 0, -
V
dc
, so t
h
e out
p
u
t
wa
ve
fo
rm
of t
h
e i
nvert
er i
s
q
u
asi
-
sq
ua
re
wave
, w
h
i
c
h i
s
not
ad
vi
sabl
e
t
o
use as an i
n
put
t
o
any
AC
sy
st
em
. Hence,
t
o
get
nearl
y
si
nus
oi
dal
wa
ve
fo
rm
,
m
u
l
tilev
e
l in
v
e
rter is in
tro
d
u
c
ed
in
1
975
[1
0]. Th
e ou
tp
u
t
of m
u
lti
lev
e
l in
v
e
rter is a staircase wave, which
is
n
early sinu
so
id
al. By in
creasin
g
t
h
e nu
m
b
er of
o
u
t
p
u
t
vo
ltag
e
lev
e
ls i
n
m
u
ltilev
e
l in
v
e
rter th
e THD can be
min
i
mized
. Al
so
ri
p
p
l
e co
n
t
en
t in
th
e
o
u
t
p
u
t o
f
m
u
ltilev
e
l
in
v
e
rter is lesser th
an
th
at of
co
nv
en
tio
n
a
l i
n
v
e
rter
[9].
One m
o
re
adva
ntage t
h
at MLI posses
s
es over th
e co
nv
en
tio
n
a
l inv
e
rter is
v
o
ltag
e
stress across th
e
i
ndi
vi
dual
s
w
i
t
c
h i
s
l
e
sser i
n
case of M
L
I
[5
]
.
M
a
ny
t
o
p
o
l
o
gi
es o
f
M
L
I a
r
e devel
o
p
e
d a
n
d st
u
d
i
e
d
.
T
h
e
y
are
g
e
n
e
rally classified
in
t
o
:
a)
Fl
y
i
ng-ca
paci
t
o
r
i
n
vert
er
b)
Diode-clam
ped inve
rter
c)
C
a
scaded
H
-
br
i
dge i
nve
rt
er
Fro
m
th
ese in
v
e
rter t
o
po
logies cascad
ed
H-Bri
d
g
e
m
u
l
tilev
e
l in
v
e
rter is wid
e
ly used
[6
]-[7
].
Cascaded i
nve
rter has
‘n’ num
ber of series
connected
cell
s
, with a
n
indi
vidual DC voltage source connected
to each cell. There a
r
e two groups
of ca
scade m
u
ltilev
e
l converters,
the symm
e
t
ric and the asymmetric
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
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:
208
8-8
6
9
4
A Novel Topol
ogy
Of
Multilevel Inverter Wi
th Re
duce
d
N
u
mber Of
Switches An
d DC… (Nakul
Thombre)
57
m
u
ltilevel converters. In sym
m
e
tric MLI all the DC volta
ge sources use
d
are of e
qual m
a
gnitude,
whe
r
eas in
asym
m
e
t
r
i
c
M
L
I m
a
gni
t
u
des
of
DC
v
o
l
t
a
ge
sou
r
ces
are
u
n
e
qual
.
In
th
e asymme
tric to
po
log
i
es, th
e v
a
lu
es
o
f
DC
v
o
l
t
a
ge s
o
urces m
a
gni
t
u
des are
u
n
eq
ua
l
.
B
y
gi
vi
ng
pr
o
p
er swi
t
c
hi
ng se
qu
ence t
o
t
h
e gat
e
d
r
i
v
er ci
rc
ui
t
s
, d
e
si
red n
u
m
b
er
of o
u
t
p
ut
v
o
l
t
a
ge l
e
vel
s
can be
obt
ai
ne
d.
So t
h
e n
u
m
b
er o
f
po
we
r el
ect
ro
n
i
c com
ponent
s
req
u
i
r
e
d
, wi
l
l
be re
duce
d
as
com
p
ared t
o
t
h
at
of
MLI
with
symmetrical DC vo
ltag
e
sou
r
ces
[8
].
On
e
o
f
th
e
adva
ntages
of asymmetrical
MLI is t
h
at wi
th the
sam
e
num
ber of s
w
i
t
c
hes an
d DC
v
o
l
t
a
ge
sou
r
ces
, t
h
e n
u
m
b
er of o
u
t
put
v
o
l
t
a
ge l
e
vel
obt
ai
ned i
s
m
o
re,
wh
en
co
m
p
ared
to th
e
symme
trical to
po
log
y
.
Thi
s
pa
per
pr
o
pos
es ne
w asy
m
m
e
t
r
i
c
t
opol
ogy
f
o
r 2
1
- l
e
v
e
l
vol
t
a
ge
out
p
u
t
wi
t
h
re
d
u
ce
d n
u
m
b
er of
swi
t
c
hes. T
h
e pr
o
pose
d
t
o
pol
ogy
has
been a
l
so anal
y
zed w
i
t
hout
usi
n
g an
y
PW
M
t
ech
ni
que
. B
u
t
aft
e
r usi
n
g
SP
W
M
t
e
c
hni
que
s T
HD
of
t
h
e
out
put
ca
n
be re
d
u
ced
f
u
rt
her
.
T
h
ree t
e
c
h
ni
q
u
es
of
SP
W
M
are u
s
ed
he
r
e
an
d
com
p
ared am
ong them
selves,
to
figu
re
ou
t t
h
e techn
i
qu
e wh
ich
g
i
v
e
s least THD.
2.
PROP
OSE
D
TOPOLOG
Y
Fi
gu
re
1.
Pr
o
p
o
se
d t
o
p
o
l
o
gy
The propose
d topology has
be
en su
cces
sful in significantly reducing
the s
w
itch count a
n
d no. of DC
v
o
ltag
e
sou
r
ces. It co
nsists of four
asy
m
m
e
trical DC v
o
ltag
e
sou
r
ces for 21
lev
e
ls. Increm
en
ts in
th
e DC
voltage s
o
urce
s are in the fas
h
ion n,
2n, 3n,
4n.
...
Wh
e
r
e n = lowest DC voltage s
o
urce
m
a
gnitude
. Pr
opos
e
d
t
o
p
o
l
o
gy
fol
l
o
w
s o
n
e rel
a
t
i
o
n bet
w
een
n
u
m
ber of o
u
t
p
u
t
vol
t
a
ge l
e
vel
s
and
n
u
m
b
er of
DC
so
urce
s. The
relatio
n
is,
N
lev
e
l =
N
DC
(
N
DC
+1) +
1
Whe
r
e,
N
lev
e
l= Nu
m
b
er of l
e
v
e
ls,
N
DC
= Num
b
er
of DC
s
o
urces.
The f
o
l
l
o
wi
ng
t
a
bl
e sho
w
s t
h
e swi
t
c
hi
ng s
e
que
nce gi
ven
t
o
t
h
e pr
op
os
ed t
o
p
o
l
o
gy
t
o
gene
rat
e
2
1
lev
e
l vo
ltag
e
ou
tpu
t
.
Tab
l
e 1
.
Sw
itch
i
ng
states o
f
pr
opo
sed
top
o
l
og
y
Sr
.
No
Output Voltage L
e
vel
S1 S2 S3 S4 S5 S6 S7
1
0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
2 +
Vdc
ON
OFF
OFF
OFF
OFF
OFF
OFF
3 +
2Vdc
OFF
OFF
ON
OFF
OFF
OFF
OFF
4 +
3Vdc
OFF
OFF
OFF
OFF
ON
OFF
OFF
5 +
4Vdc
OFF
OFF
OFF
OFF
OFF
OFF
ON
6 +
5Vdc
ON
OFF
OFF
OFF
OFF
ON
OFF
7 +
6Vdc
OFF
OFF
ON
OFF
OFF
ON
OFF
8 +
7Vdc
OFF
OFF
OFF
OFF
ON
ON
OFF
9 +
8Vdc
ON
OFF
OFF
ON
OFF
ON
OFF
10
+
9Vdc
OFF
OFF
ON
ON
OFF
ON
OFF
11
+
10Vdc
ON
ON
OFF
ON
OFF
ON
OFF
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 5
,
No
. 1
,
Ju
ly 20
14
:
56
–
62
58
3.
PULSE WIDTH
MODUL
A
TIO
N
METHODOLOG
Y
For
an
n
– l
e
v
e
l
i
nvert
e
r
t
h
e
m
u
lt
i
carri
er P
W
M
m
e
t
hod
u
s
es n
-
1 t
r
i
a
n
g
u
l
ar carri
e
r
si
g
n
a
l
s
and
o
n
l
y
one
m
odulating si
nus
oidal
signal is
applied as re
fere
nce.
The ze
ro re
ference is
placed in the
m
i
ddle of the
carrier set.
At
every insta
n
t each carrier s
i
gnal is
com
p
ared
with the
m
odulating si
nus
oi
dal signa
l. Each
com
p
ari
s
on
gi
ves
one
i
f
t
h
e
m
odul
at
i
ng si
g
n
al
i
s
g
r
eat
er t
h
an
t
h
e t
r
i
a
ng
u
l
ar car
ri
er si
g
n
a
l
,
ot
he
rwi
s
e
z
e
ro
. T
h
e
M
u
l
t
i
carri
er
P
W
M
m
e
t
hod i
s
cat
ego
r
i
zed
i
n
t
o
2
g
r
ou
ps:
1
)
Phase sh
ifted
PWM m
e
th
od
,
wh
ere th
e m
u
ltip
le carriers
are
p
h
a
se sh
ifted
acco
r
d
i
ng
ly.
2) C
a
rri
er
di
sp
osi
t
i
on m
e
t
hod
s (C
D
)
w
h
ere
t
h
e refe
re
nce s
i
gnal
i
s
sam
p
l
e
d t
h
ro
u
gh a
num
ber
o
f
carrier signals
displace
d
by continuous i
n
crem
ents of
the re
fe
re
nce si
gnal
am
pl
i
t
ude. Fu
rt
he
r
c
a
rri
er
d
i
spo
s
itio
n PWM m
e
th
o
d
is gro
u
p
e
d
in
t
o
three:
a) Phase
Di
sp
osi
t
i
on (
P
D
)
M
e
t
h
o
d
- The
pha
se di
sp
osi
t
i
on m
e
t
hod ha
s
an equal
n
u
m
b
er
of car
ri
er
si
gnal
s
a
b
ove
a
n
d
bel
o
w
t
h
e z
e
ro
re
fere
nce a
n
d
are
i
n
p
h
ase
wi
t
h
t
h
e sam
e
am
pl
i
t
ude a
n
d
fre
que
ncy
.
Fi
gu
re
2.
P
D
P
W
M
b
)
Altern
ativ
e Ph
ase Oppo
sitio
n
Dispo
s
ition
(APOD)
Metho
d
- All carrier wav
e
fo
rm
s in
th
is APOD
m
e
thod a
r
e
phase-dis
placed by 180°
alternat
ively.
Fi
gu
re
3.
A
P
O
D
P
W
M
c) Ph
ase
O
ppositio
n
D
i
spo
s
itio
n
(POD) Meth
od
- A
ll
carrier sig
n
a
ls ab
ove th
e zero
referen
ce are in
th
e sam
e
p
h
a
se bu
t th
e carrier
sig
n
a
ls
b
e
low t
h
e ze
ro re
fere
nce are
phase s
h
ifted
by 180
de
grees
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
A Novel Topol
ogy
Of
Multilevel Inverter Wi
th Re
duce
d
N
u
mber Of
Switches An
d DC… (Nakul
Thombre)
59
Fi
gu
re 4.
P
OD P
W
M
4.
PULSE GEN
E
RATIO
N CI
RC
UIT
For
t
h
e
pul
se
g
e
nerat
i
o
n i
n
t
h
e new
t
o
pol
og
y
20 ca
rri
e
r
s si
gnal
s
a
r
e em
pl
oy
ed
wi
t
h
t
h
e
am
pl
i
t
ude o
f
each triangular carrier as
0.1 and freque
nc
y 1KHz.
One
sinusoidal
wa
ve of am
plitude
1 a
nd
fre
quency 50
Hertz is em
ployed as a
refe
re
nce signal.
In
order to t
u
rn
on
th
e switch
e
s in
th
e
p
a
rticu
l
ar d
e
sired
in
st
an
ts,
pul
se
ge
nerat
i
o
n ci
rc
ui
t
i
s
use
d
.
In
t
h
i
s
circ
ui
t, the re
fere
nce
signal is c
o
m
p
ared
with t
h
e c
a
rrier
signal and the
out
put
of t
h
e c
o
m
p
ari
s
on i
s
f
e
d t
o
t
h
e l
o
gi
c
gat
e
s an
d t
h
e r
e
qui
red
pul
se
pat
t
e
rn i
s
gene
rat
e
d at
t
h
e o
u
t
put
o
f
th
e log
i
c
g
a
tes to
tri
g
g
e
r t
h
e switch
e
s. Th
e pu
lse
gene
rat
i
on ci
rcui
t
i
m
pl
em
ent
i
ng P
D
P
W
M
t
e
c
h
n
i
que i
s
sho
w
n i
n
Fi
gu
r
e
5.
Fi
gu
re
5.
P
u
l
s
e Ge
nerat
i
o
n C
i
rcui
t
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60
5.
SIMULATION RESULTS
Propo
sed
circuit is v
a
lid
ated
o
n
M
A
TLAB/Si
m
u
lin
k
p
l
atfo
rm
. IGBT in
p
a
rallel with
th
e series RC
snu
b
b
er ci
rc
ui
t
i
s
used as a swi
t
c
h. T
h
e m
a
gni
t
u
des
of D
C
vol
t
a
ge so
u
r
ces t
a
ken are
10
V,
20
V,
30
V, 4
0
V
.
Loa
d
resi
st
an
c
e
i
s
t
a
ken as
1
0
O
h
m
.
R
e
peat
i
ng se
q
u
ence
bl
oc
k i
s
use
d
t
o
ge
ne
rat
e
t
h
e
swi
t
c
hi
n
g
se
q
u
ence
.
Pul
s
e ge
nerat
o
rs are use
d
t
o
gi
ve p
u
l
s
es t
o
t
h
e H - b
r
i
d
ge.
Fi
gu
re 3 sh
o
w
s t
h
e ci
rcui
t
di
ag
ram
of pro
pos
ed
t
o
p
o
l
o
gy
. Fi
g
u
r
e 4 sh
ow
s t
h
e 21 l
e
vel
o
u
t
p
ut
of t
h
e i
nve
rt
er
. Fi
gu
re 5 sh
o
w
s TH
D co
nt
ent
i
n
t
h
e out
p
u
t
. It
i
s
12
.6
9
%
. Fi
gu
r
e
sh
ow
s T
H
D
of
t
h
e
o
u
t
p
ut
w
a
vef
o
rm
s aft
e
r
usi
n
g P
D
,
P
O
D,
AP
O
D
P
W
M
t
echni
ques
.
Fi
gu
re
6.
TH
D
o
f
t
h
e
o
u
t
p
ut
wave
f
o
rm
wi
t
hout
a
n
y
P
W
M
t
echni
que
Fi
gu
re
7.
TH
D
o
f
t
h
e
o
u
t
p
ut
wave
f
o
rm
usi
n
g
PDP
W
M
t
e
c
h
n
i
que
Fi
gu
re
8.
TH
D
o
f
t
h
e
o
u
t
p
ut
wave
f
o
rm
usi
n
g
PODP
W
M
Fi
gu
re
9.
TH
D
o
f
t
h
e
o
u
t
p
ut
wave
f
o
rm
usi
n
g
AP
OD
P
W
M
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6
9
4
A Novel Topol
ogy
Of
Multilevel Inverter Wi
th Re
duce
d
N
u
mber Of
Switches An
d DC… (Nakul
Thombre)
61
Tabl
e 2.
C
o
m
p
ari
s
on
o
f
SP
WM
t
ech
ni
q
u
e
s
Sr
.
No.
PWM
T
e
chnique
T
HD
(
%
)
1.
PD
5.
67
2.
POD
5.
93
3.
APOD
6.
15
6.
CO
NCL
USI
O
N
I
n
t
h
is
p
a
p
e
r
,
a n
e
w
topo
logy f
o
r
2
1
lev
e
ls is pr
opo
sed with
r
e
d
u
c
ed
num
b
e
r
o
f
sw
itch
e
s and
D
C
sources. Thus, this new circ
uit will require lesser hardwa
re space, lesser cost; also
the com
p
lexity of the
circu
it will red
u
ce.Th
e FFT an
alysis d
o
n
e
with
th
e fu
n
d
a
m
e
n
t
al switch
i
ng frequ
en
cy resu
lted
in
th
e THD
o
f
1
2
.69
%
. Fro
m
th
e FFT
an
al
ysis, it is fo
und
th
at PDPWM tech
n
i
qu
e
giv
e
s least THD. Th
e
n
e
w
circu
it is
ex
am
in
ed
in
MATLAB/Simu
lin
k. It is
obs
erve
d t
h
at
eve
n
aft
e
r t
h
e re
d
u
ct
i
on i
n
s
w
i
t
c
hes an
d so
urce
s, t
h
e
desi
re
d out
put
i
s
o
b
t
a
i
n
ed
.
REFERE
NC
ES
[1]
Ba
yat
,
Z.
; Baba
ei,
E.
, "A new cas
caded m
u
lt
ile
ve
l inver
t
er with reduced numb
e
r of switches,"
Power Ele
c
troni
cs
and Drive S
y
stems Technology (
PEDSTC)
, 2012
3rd
, vol., no
., pp
.416-421, 15-16
Feb. 2012
.
[2]
S. Lai and F.Z.
Peng, "Multil
eve
l
conve
rt
ers -a n
e
w breed of power conver
t
ers," I
EEE Tr
ans. Ind
Appl., vol
. 32, n
o
.
3, pp
. 509-17
,M
ay
/June 1996
.
[3]
Ebrahim
i
, E
.
Babaei
, and G.B.
Gharehpet
i
an "
A
new
m
u
ltilev
e
l convert
er topol
og
y
with redu
ced num
ber of po
wer
electronic components,"
Accepted
and will be pu
blished on
IE
EE Trans. Ind.
Electron.
[4]
S.
De,
D.
Banerjee I ,
K.
Si
va k
u
mar, K. Gopakumar, R.
Ramchand, and C. Pa
t
e
l, "Multi
lev
e
l i
nverters for low
-
power applicatio
n," lET
Power
Electron., vol. 4
,
n
o
. 4
,
pp
. 384-39
2, 2011
.
[5]
E. B
a
ba
ei
and
S.H. Hosseini,
"New casc
a
ded
m
u
ltileve
l
invert
er topo
log
y
wit
h
m
i
nim
u
m
num
ber of switch
e
s,"
Elsevier Journal
of Energ
y
Conv
ersion and
Ma
nagement, vol. 50,
no. II
, pp
. 2761-
2767,N ov. 2009
.
[6]
S. Mekhilef an
d M.N. Abdul
Kadir,
"Novel vector con
t
rol
m
e
thod for thr
ee-stage h
y
brid
cascad
ed m
u
ltil
evel
inverter,"
I
E
EE Trans. Ind.
Electron.,
vol. 58, no. 4, pp. 1339-134
9, April 2011.
[7]
S.D.G. Jay
a
sing
hal, D.M.
Vi
lath
gam
u
wal,
and U
.
K. Mad
a
wala, "
C
ascad
e m
u
ltil
evel st
ati
c
s
y
nchr
onous com
p
ensator
configuration
for
wind farms," lET Power El
ectro
n
., vol. 4, no. 5,p
p. 548-556,201
1.
[8]
Ranjan
, S.; Mishra, S.K., "Anal
y
sis of as
y
m
m
e
tric
al
cas
caded
m
u
ltileve
l inver
t
er for tra
c
tion
s
y
stem
s,"
En
erg
y
Effi
ci
ent Techno
logies for Susta
i
nabilit
y
(
I
CEETS)
, 2013 Interna
tional Con
f
eren
ce on
, vol., no.,
pp.708,713
, 10-
12
April 2013
[9]
Lakshmi, T.V
.
V.S.; George,
N.;
Um
as
hankar, S
.
; Kothari
,
D.
P
., "Cas
cad
ed seven level
inverter with redu
ced
number of switches using lev
e
l shifting PWM technique,"
Power,
Energy and
Con
t
rol (
I
CPEC)
,
2013 Internationa
l
Conference on
,
vol., no., pp
.676,680, 6-8
Feb. 20
13
[10]
Ned m
ohan, Tore.M, undeland,
and Willia
m
.
P.
Robbins “power
electronics
, co
n
v
erters, Appli
c
at
ions and Design”,
Third
edit
ion,
New Delhi
,
W
i
l
e
y India (P.)Ltd. R
e
print.
[11]
M.H.Rashid “
P
ower el
ec
tronics
:
Circu
its,
Devic
e
s
and app
l
i
cat
ion
s
. Third
ed
ition
,
Prentic
e ha
ll
, 20
04
BIOGRAP
HI
ES OF
AUTH
ORS
Nakul Thombre
was born in
Thane, Mah
a
rashtr
a
.
Curren
t
ly
, he is pursuing a Master’s Degree
in P
o
wer Ele
c
tr
onics
and Drive
s
at VIT Univer
s
i
t
y
, Vel
l
ore
.
He
rece
ived his
B
ache
l
or Degre
e
in Electrical En
gineer
ing in the
y
e
ar 2012 at C
o
lleg
e
Of Engineering A’nag
a
r affiliated
to
Universit
y
of Pune, Mahar
a
shtra
.
His research
int
e
rests are
casc
a
d
e
d m
u
ltilev
e
l In
verter
, SMPS,
Batter
y
oper
a
ted
vehicles
and el
e
c
tri
cal
driv
es
.
Ratika Singh Rawat was born in Hapur, Uttar Pr
ad
esh. Curren
t
ly, she is pursuing a Master’s
Degree in P
o
wer Electr
onics
an
d Drives
at VIT
Univers
i
t
y
, Vel
l
o
re. S
h
e rece
ive
d
her Bachelor
Degree in E
l
ect
r
onics and Instrum
e
ntation Eng
i
neer
ing in the
y
e
ar 2013 at th
e Institut
e
Of
Techno
log
y
and
Management co
lleg
e
affiliated
to Rajiv Gandhi
Techn
i
cal University
, Mad
h
y
a
Pradesh. Her research in
terests a
r
e cascad
ed m
u
ltilev
e
l Invert
er a
nd control of power elec
tronic
converters.
Evaluation Warning : The document was created with Spire.PDF for Python.
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62
Priy
ank
a
Rana
was born in Gwalior
,
Madh
y
a
Pr
ades
h. Curren
t
l
y
, s
h
e
is
purs
u
ing a M
a
s
t
er’s
Degree in P
o
wer Electr
onics
an
d Drives
at VIT
Univers
i
t
y
, Vel
l
o
re. S
h
e rece
ive
d
her Bachelor
Degree in E
l
ect
r
onics and Instrum
e
ntation Eng
i
neer
ing in the
y
e
ar 2013 at th
e Institut
e
Of
Techno
log
y
and
Management Co
lleg
e
aff
iliated
to Rajiv
Gandhi
Techn
i
cal Univ
ersity
, Madh
y
a
P
r
ades
h. Her
res
earch
int
e
res
t
s
ar
e c
a
s
cad
ed m
u
lt
i
l
eve
l
Inve
rter
an
d DC to DC
con
v
erter
.
Um
as
hankar S
rece
ived B
.
E.
D
e
gree
in
Ele
c
tri
cal
and El
ec
tro
n
ics
Engin
eerin
g from
Govt.
College of Technolog
y
,
Coim
batore
in th
e
year 2001
and
M.
Tech.,
and P
h
D in Power
Electronics from VIT University
,
Vellor
e
in
th
e
year 2004
and 20
13 respectively
.
Currently
h
e
is working as
A
s
s
o
ciate
Pr
ofes
s
o
r
in the School of Electrical
Engineer
ing at V
I
T University
,
Vellore. He worked as
Asst. Professor-Senior,
S
e
nior R&D Engineer and Senio
r
Application
Engineer in the
power electronics,
renewable Energ
y
and
electrical
drives field for
more than 10
y
e
ars.
He has been one of the
Editorial Board
m
e
mbers in Internation
a
l journal of electronics
,
communication
and electrical en
gi
neer
ing
and
reviewer
in r
e
puted journals lik
e
Elsevier
, I
E
EE
and IET. He has
published
/
presented 98
papers in
nation
a
l
an
d intern
ation
a
l
journals/conferences. He h
a
s also co-authored
/co-edited 10 bo
oks/chapters an
d 10 techn
i
cal
arti
cles
on power
el
ec
tronics
a
pplic
ations
in
renewabl
e en
erg
y
and all
i
e
d
areas
. His
current
ar
eas of
research
ac
ti
vities
in
clud
e
power ele
c
tr
onics appli
c
a
t
i
ons in wind
and s
o
lar
en
erg
y
, m
odern
ele
c
tr
ic
al dr
ives
and
con
t
rol, smart grid
and power qu
ality.
Evaluation Warning : The document was created with Spire.PDF for Python.