Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l.
7, N
o
. 1
,
Mar
c
h
20
16
,
pp
. 12
4
~
13
3
I
S
SN
: 208
8-8
6
9
4
1
24
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Desi
gn of Three-
Phase T
h
ree-Swi
t
ch Buck
-Type Recti
f
ier f
o
r
Pre-Charging Application
A
n
a
n
dh
S*
, Vij
a
y
a
n
S**
,
Para
ma
s
i
va
m*
**
* Anna Univ
ersity
of
Technolog
y
,
Chenn
a
i, Ind
i
a
** Sur
y
a Eng
i
neering Co
lleg
e
, Erode,
India
*** Danfoss Industries Pvt.
Ltd,
Chennai, Ind
i
a
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
J
u
l 11, 2015
Rev
i
sed
D
ec 20
, 20
15
Accepte
d Ja
n
9, 2016
The m
a
in obj
ect
i
v
e of a pre-
charg
i
ng circu
it in v
a
r
i
abl
e
frequen
c
y
drives
is
to
pre-charg
e
the DC-bus
capacito
r
wit
hout an
y
v
o
ltag
e
and
curr
ent overshoo
t
within the s
p
eci
fied tim
e. In exi
s
iting variab
le fr
equenc
y driv
es
s
e
pert
e pre-
charging circuits (or) thy
r
istor bridges were used due to this drives power
density
,
cost becomes high and
contro
l
techn
i
q
u
e becom
e
s
co
m
p
lex. This
paper pr
esents
about th
e d
e
sign of
thr
ee-ph
ase thr
ee-switch buck-ty
p
e
rect
ifier
for p
r
e-
charging
appl
ic
a
tion us
ed
in v
a
ri
able
frequ
enc
y
d
r
ives
which
elim
at
es
the
dis
a
dvant
ages
of
existing techniqu
es.
In
this pap
e
r we will
discuss about
design procedu
r
e of pre-
charg
i
ng circu
it of
an 800KW
converter with d
c
-link outpu
t voltage of
775V at
an input
ac voltage of 550V,
60Hz, selection
of power and passive co
mponents, voltag
e
a
nd current stress
of power transis
t
ors. In th
e final this
paper
discu
sses a
bout loss distribution
of the
components and comparis
on of new conv
erter techn
i
que w
ith ex
isting
pre-charg
i
ng techniques.
Keyword:
Peak c
u
rre
nt detection
V
a
r
i
ab
le fr
equen
c
y dr
iv
es
Zero
cr
ossi
ng
det
ect
i
o
n
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Ana
n
dh
S,
Research Sc
holar,
Ann
a
Un
iv
ersity,
Ch
enn
a
i.
Em
a
il: an
an
dh
.siv
anp
a
n
d
i
@gmail.co
m
1.
INTRODUCTION
In all high
po
w
e
r varia
b
le fre
q
u
ency
d
r
ives (
V
F
D
’s
);
d
c
-link
cap
acitors were u
s
ed
to
m
a
i
n
tain
a stiff
DC-link
vo
ltage acro
ss th
e rectifier o
u
t
pu
t, fed
v
i
a an
un
con
t
ro
lled
rectifier fro
m
th
ree-ph
ase ac v
o
ltage. Th
e
main
u
s
ag
es
o
f
d
c
-lin
k-capacito
r
were;
Loa
d
-balanci
ng e
n
ergy stora
g
e elem
ent
To com
p
ensat
e
t
h
e di
ffe
renc
e bet
w
een t
h
e
po
wer re
q
u
i
r
e
m
ent
of t
h
e i
n
vert
er a
nd t
h
e
out
p
u
t
p
o
we
r
of
in
pu
t-u
n
c
on
trolled
bridg
e
rectifier;
To t
a
ke i
n
t
h
e
dem
a
gnet
i
zat
i
o
n
en
er
gy
o
f
t
h
e
dri
v
e
i
n
ca
se o
f
a
n
em
ergency
sh
ut
d
o
w
n
of
al
l
co
n
v
er
t
e
r
transistors;
To s
u
pply tra
n
sient-power pe
aks;
To
pr
ot
ect
t
h
e
i
nve
rt
er
fr
om
t
r
ansi
ent
pea
k
s
o
f
t
h
e
m
a
i
n
s vol
t
a
ge.
The size
of t
h
is dc-link
or
filter capacitor depends
on the
am
ount
of ac
energy it
m
u
st abs
o
rb t
o
m
a
intain a require
d am
ount of current ri
pple
at
the dc-lin
e
and the level of rm
s current it can tolerate because
of E
S
R heating.
When a capa
c
itor ba
nk
is initially connect
ed to a
voltage
source a tra
n
si
ent cha
r
gi
ng
(i
nrus
h)
cu
rren
t
will flow. Inru
sh
cu
rren
t is a
m
a
x
i
m
u
m
,
in
stan
ta
n
e
ou
s inp
u
t
cu
rrent d
r
awn
b
y
d
c
-lin
k
cap
acito
rs
wh
en
i
t
’
s fi
rst
t
u
r
n
ed
o
n
. T
h
e m
a
gn
i
t
ude a
n
d
f
r
eq
u
e
ncy
o
f
t
h
i
s
ch
argi
ng
cu
rre
nt
depe
n
d
s
u
p
o
n
t
h
e t
o
t
a
l
ca
paci
t
a
nc
e
an
d ind
u
c
tan
c
e of th
e circu
it as well as m
a
g
n
itu
d
e
o
f
th
e app
lied
v
o
ltag
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
: 1
2
4
–
13
3
12
5
As an a
p
plication case a
pre
-
charging circ
uit for
VF
D ap
p
l
i
cat
i
on shal
l
b
e
di
m
e
nsi
oned
i
n
suc
h
a
way th
at it’s i
n
p
u
t
vo
ltag
e
U
l-l
,
rms
=550
V
±
1
0
%
,
O
u
t
put
DC
l
i
nk vol
t
a
g
e
U
0
= 77
5V
and
P
0
=8
00KW
.
Fi
gu
re 1.
B
a
si
c
p
o
we
r
ci
rc
ui
t
of
a Vari
abl
e
fr
eque
ncy
dri
v
e
Basically there are diffe
rent
pre
-
ch
a
r
ging topologies avai
lable to
m
eet
this specification s
u
ch as;
Resistor-c
ontactor arrangement, Th
yrist
o
r switch
arrang
em
en
t, Th
yristo
r Bridg
e
as rectifier, Mag
n
e
tic
resistive-elem
e
n
t
and propos
ed new
top
o
l
og
y Thr
e
e-
ph
ase th
r
e
e-
sw
itch bu
ck
typ
e
rectifier [1
]. The m
a
in
adva
nt
age
o
f
t
h
e
pr
o
pose
d
n
e
w t
ech
ni
q
u
es
i
s
l
e
ss n
u
m
b
er
of
act
i
v
e a
n
d
p
a
ssi
ve c
o
m
pon
ent
s
, l
e
ss
ex
pe
nsi
v
e
,
si
m
p
le in
con
t
ro
l and
con
t
ro
llab
ility an
d
ab
l
e
to
d
e
tect all failu
re co
nd
ition
s
.
In
t
h
is p
a
p
e
r
we will d
i
scu
s
s abo
u
t
t
h
e d
e
sig
n
of
three-ph
ase three-swit
ch
b
u
c
k
rectifier sh
own in
Fi
gu
re 2 use
d
f
o
r
p
r
e-c
h
ar
gi
n
g
a
ppl
i
cat
i
o
n.
Figure
2. Thre
e –
phase T
h
re
e-switch buc
k
rec
tifier circu
it fo
r
d
c
-lin
k capacito
r
p
r
e-ch
arg
i
ng
Th
e m
a
in
ob
j
e
ctiv
es of
p
r
e-
ch
a
r
g
i
ng
c
i
r
c
u
it
w
e
r
e
;
To
ch
arg
e
t
h
e
d
c
-link
cap
acito
r with
i
n
th
e allo
wed
tim
e
To
lim
i
t
b
o
t
h th
e
p
eak d
c
link and
ac i
n
pu
t li
n
e
cu
rren
t t
o
an
y d
e
sired limi
t
(pre-d
efi
n
ed
v
a
lu
e).
Fu
rt
h
e
rm
o
r
e i
n
th
is p
a
p
e
r we will d
i
scu
ss
ab
ou
t u
s
ag
e
o
f
rectifier fo
r
pre-ch
arg
i
ng
app
licatio
n
in
Sect
i
on I
I
, sel
ect
i
on o
f
p
o
w
er sem
i
conduc
t
o
r,
passi
ve
c
o
m
ponent
s i
n
S
ect
i
on I
II, l
o
ss
di
st
ri
b
u
t
i
on
o
f
t
h
e
com
pone
nt
s d
u
r
i
n
g a pre-
de
fi
ned
pre
-
cha
r
gi
ng ci
rc
ui
t
curr
ent
l
i
m
i
t
i
n
Sect
i
on IV a
nd fi
nal
l
y
t
h
e perf
o
r
m
a
nce
co
m
p
ariso
n
of
ex
istin
g conv
erters with th
e
pro
p
o
s
ed
con
v
e
rter.
2.
RECTIFIE
R AS A
P
R
E-
C
H
A
R
GI
NG
C
I
RC
UIT
The
b
a
sic op
eratin
g
p
r
icip
le of three
ph
ase t
h
ree switc
h bu
ck rect
i
f
i
e
r f
o
r pre
-
cha
r
gi
n
g
a
ppl
i
cat
i
o
n
i
s
sim
i
l
a
r t
o
t
h
e s
t
anda
rd t
h
ree
p
h
ase
bri
dge
rec
t
i
f
i
e
r. T
h
e m
a
in
di
ffe
ren
ce i
s
base
d o
n
c
o
nt
r
o
l
t
ech
ni
q
u
e
us
ed f
o
r
pre
-
cha
r
gi
n
g
t
h
e DC
-l
i
nk ca
paci
t
o
r
,
n
o
o
f
po
we
r sem
i
co
nd
uct
o
rs
used
.
The swi
t
c
hi
n
g
seq
u
e
n
ce (
1
10
-
0
1
1
-
10
1
)
of t
h
e p
r
op
ose
d
co
nve
r
t
er were sh
o
w
n i
n
Fi
g
u
re 3
,
whe
r
e
i=R, S, T
indicates a com
b
ination of three
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Design
o
f
Th
ree-Pha
s
e Th
ree-S
w
itch
Bu
ck-Ty
p
e
Rectifier for Pre-C
h
a
r
g
i
ng
App
lica
tio
n
(
A
na
ndh
S
)
12
6
swiches
S
i
, When
S
i
=0
m
ean
s th
e co
rrecpon
d
i
n
g
swicth
in
th
e bridg
e
leg
is tu
rn
ed
o
ff an
d
S
i
=
1
indiates the
sw
itch
is in
tur
n
ed
on
state.
Fo
r
ex
am
p
l
e, b
y
con
s
id
er
ing o
n
e
sw
ich
i
n
g
sequ
en
ce
(
101)
th
e cur
r
e
n
t
f
l
o
w
s i
n
t
h
e bri
dge l
e
g
S
R
o
f
t
h
e rectifier, d
c
link
in
du
ctor
,
d
c
l
i
nk c
a
paci
t
o
r a
nd
b
r
i
d
ge l
e
g
S
T
o
f
th
e
rectifier
S
R
- L
4
-
C
0
-S
T
. The
re
ctifier input curre
nt can be ca
lculated for
ea
ch of the switc
hing sequ
e
n
ce
s as shown in
below
eq
u
a
tion
s
;
g
e
nerally th
e three-ph
ase
r
ectifier in
pu
t cu
rren
t
is d
e
fin
e
d
as
i
T
rec
e
j
i
S
rec
e
j
i
R
rec
i
rec
,
.
3
/
4
,
.
3
/
2
,
3
2
(
1
)
Figu
re
3.
C
o
nd
uction
states
of
the T
h
ree
-
pha
se Th
ree-
switc
h
buc
k
P
W
M
r
ectifier, (a
)
I
dc
du
rin
g
s
w
itchi
ng
sequ
n
c
e (1
10)
,
(
b
)
I
dc
du
r
i
n
g
switcin
g
sequ
ence (0
11
),
(
c
)
I
dc
d
u
ri
ng
switchi
ng
se
que
nce
(1
01
),
(d
)
I
dc
duri
ng freewheeling
For t
h
e switching state
j
=(1
0
1
) the
rectifier
input c
u
r
r
ents
are
i
rec,R
=
I
,
I
rec,s
=
0
and
i
rec,T
=
-I,
the
r
efore the
rectifier
input current for
t
h
e
switching state
s
will be;
e
j
I
i
rec
6
/
3
2
.
)
101
(
,
(
2
)
e
j
I
i
rec
6
/
3
2
.
)
110
(
,
(
3
)
e
j
I
i
rec
3
/
4
3
2
.
)
011
(
,
(
4
)
2.
1. Propose
d
Contr
o
l
Tech
nique
The
pr
o
pose
d
cont
rol alg
o
r
ithm
show
n in
F
i
gu
re 4 c
o
nsists of
tw
o bl
ock
s
i). Zer
o
c
r
o
ssing
detectio
n
and ii).
Peak c
u
rrent m
ode c
ont
rol. T
h
e zero crossing
detection circ
uit is use
d
f
o
r
gen
e
rating P
W
M
pulse
s
req
u
ire
d
fo
r no
rm
al
operatio
n of
the
c
o
nve
rte
r
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN:
2
088
-86
94
I
J
PEDS Vo
l.
7,
No
.
1,
Mar
c
h
2
016
: 1
2
4
–
13
3
12
7
Figu
re
4.
Ne
w
pr
o
pose
d
s
o
ft c
h
ar
gin
g
c
o
nt
rol
techni
que
wit
h
c
o
n
s
tant c
u
r
r
e
nt co
ntr
o
l
The basic swit
ching
se
quenc
e
of
three
pha
s
e three switch
buc
k converter is sim
ilar t
o
the sta
nda
rd
three phase bridge rectifier. T
h
e
re
q
u
ired
P
W
M
gate
puls
e
s were
ge
nera
ted thr
o
ug
h
pa
ssing t
h
e in
put
three
pha
se ac
volta
ge to a
zero crossing
de
tector (ZCD) circ
uit, falling edge i
n
tegrator and l
ogical
gate circuits.
Initially, three
pha
se input ac
volta
ge
s we
re
applied through the
Z
C
D cir
c
uits which
gener
a
ted
a ser
i
es of
pulses
b
a
sed o
n
the zer
o cr
ossing o
f
ac voltage.
Figu
re 5.
Wa
v
e
fo
rm
s
at
diffe
rent sta
g
es
of
p
r
e-c
h
ar
gin
g
c
o
ntr
o
l circ
uits,
(
a
) Line
v
o
ltage
, (
b
)
Zer
o
c
r
oss
i
ng
detection
circu
it o/p,
(c)
L
ogi
cal OR
gate o/
p,
(
d
)
Lo
gical
o/p
fr
om
curre
nt fee
d
back
, (
e
) I
G
B
T
gate
pu
lses
The p
u
lses f
r
o
m
ZC
D were furt
her sam
p
led th
ro
u
gh
falling ed
ge integ
r
ator t
h
r
o
ug
h w
h
ich
synchronized
ra
m
p
signals will be generate
d for both
positive and ne
gative ac voltage
s. Finally, the ram
p
signals we
re c
o
m
p
ared through c
o
m
p
arator and logic gat
e
s through
wh
ich pulses
were gene
rated for each
cy
cle of ac inp
u
t volta
ge. I
n
peak c
u
r
r
e
n
t
m
ode c
ont
ro
l the
DC link induc
tor curre
nt was com
p
ared wit
h
the
req
u
ire
d
pre
-
d
e
fine
d re
fere
nc
e set cu
rre
nt,
whe
n
t
h
e
DC
link i
n
ductor c
u
rrent is le
ss than the set c
u
rrent
a
pulse
will be generate
d and vice versa. T
h
e
resultant
pul
se
s from
the zero crossi
ng
detec
tion circ
uit and pea
k
current c
o
ntrol
were
logically com
p
ared th
ro
u
gh a
n
AN
D gate a
n
d
ge
nerates
res
u
ltant P
W
M
p
u
ls
es fo
r
IGBT
’s as shown i
n
Figure
5. Sepa
rate cont
rol circ
uits
(ze
r
o c
r
ossing &
peak c
u
rre
nt detection circuit
)
will
b
e
im
p
l
e
m
en
ts f
o
r
ind
i
v
i
d
u
a
l
p
h
a
ses thro
ugh wh
ich
t
h
e ind
i
v
i
du
al IGBT’s
will b
e
co
n
t
r
o
ll
ed
.
3.
SYSTE
M
DESIGN
In this section
we will discus
s about selection
of active a
nd
passi
ve com
ponents w
h
i
c
h are m
a
inly
depe
n
d
s
o
n
the
v
o
ltage a
n
d
c
u
rre
nt stress
o
f
t
h
e c
o
m
pone
nts
.
3.
1
Vol
t
age Stress
e
s
The
voltage st
r
e
sses o
n
the ac
tive and
passi
v
e
co
m
pone
nts
m
a
inly
depen
d
s
on t
h
e m
a
ins line to line
voltage
, howe
ver, for selecting IGBT
’s and powe
r diod
e
s
and additional
m
a
rgin of
double the line to line
voltage
ha
s to
be c
o
n
s
idere
d
.
V
V
U
l
l
855
%
10
550
*
2
max
,
(
5
)
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I
J
PEDS
I
S
SN:
208
8-8
6
9
4
Design
of Thre
e-Phase
Three-Switch B
u
ck-Ty
pe Rectifier for Pre-C
h
argi
ng A
p
plication
(
A
na
ndh
S
)
12
8
The o
u
tp
ut vol
tage is contr
o
lled to a consta
n
t
value of
U
0
=
7
7
5
V
, there
f
or
e the inductio
n
L
4
and capacitor
C
0
were
selected f
o
r
this value pl
us 10
%
m
a
rgin
f
o
r o
v
ers
h
oot m
a
rgin of
co
nt
rol
l
o
o
p
.
3.
2
Current Stres
ses
In order to select the active
a
nd
passive com
ponents it is
necessa
ry to calculate the device avera
g
e
and rm
s currents. For e
x
act ca
lculation
of a
v
erage c
u
rre
nt
it is necessa
ry to know th
e
currents during
differe
n
t
in
ter
v
als
of
the pr
e-
ch
arg
i
ng ph
ase
[
2
] ar
e
sh
own
in Figur
e
6
.
Th
e in
ducto
r
d
c
cu
rr
en
t du
r
i
n
g
pr
e-
char
g
i
ng
pha
se ha
ve th
r
ee intervals;
1.
In
d
u
ctor c
u
rre
nt be
fo
re
reac
hing the
pre
-
set curre
nt
lim
i
t
,
2. Inductor current
reaches the
pre
-
set val
u
e,
3. Inductor c
u
rre
n
t reac
hes a
f
ter t
h
e
pre
-
set
value.
The a
v
er
age
a
n
d
rm
s cur
r
ent
flo
w
s t
h
r
o
ug
h
the
po
we
r se
m
i
cond
ucto
r
d
u
ri
ng
this i
n
terval
I
fo
r a
pulse
pe
rio
d
a
r
e sh
ow
n i
n
Fig
u
re
7;
T
p
R
dt
I
T
p
i
avg
T
0
1
,
=
R
I
.
(
6
)
T
p
R
dt
I
T
p
i
rms
T
0
2
1
2
,
=
R
I
.
2
(7
)
Fig
u
r
e
6
.
(
a
)
.
DC link
cu
rr
ent li
mited
to
2
00A,
(
b
)
.
DC lin
k
vo
ltag
e
o
f
770V acr
o
ss th
e cap
acito
r
Figu
re 7.
Wa
v
e
fo
rm
du
rin
g
pre
-
cha
r
gin
g
I
n
ter
v
al I,
(a
) R
-
p
h
ase
Line
v
o
ltage
U
R,N
=
550
V,
(b)
R
-p
h
a
se IGBT
cur
r
ent,
(c
)Ze
r
o c
r
ossi
n
g
detection circ
uit lo
gical OR
gate
o/p,
(
d
)
Pea
k
c
u
r
r
ent
detectio
n lo
gical c
u
r
r
e
n
t
feed
bac
k
o/p,
(
e
)
I
G
B
T
gate p
u
lses
Du
rin
g
inter
v
a
l
I the DC
link induct
o
r c
u
r
r
e
n
t is less th
an the pre
-
set cur
r
ent lim
it, so the DC
link in
duct
o
r
current
will be
in
discontinuous c
o
nduction
m
ode. In in
te
rval II,
once t
h
e DC link
i
n
ductor c
u
rrent
reaches
the pre-set c
u
rrent
value t
h
e
pre
-
cha
r
ging c
o
nve
r
ter will
ope
rate in
swi
c
h m
ode of
operation as shown in
Figu
re 8,
9. T
h
e DC
link in
d
u
cto
r
cur
r
e
n
t duri
ng the inte
r
v
al II is fu
rthe
r divide
d into t
w
o s
ub inter
v
a
l
s, the
first sub interval is the c
u
rrent rise
from
zero t
o
pr
e
-
set
curre
n
t li
m
it
and the se
cond sub interval
is the
In
terv
al III
In
terv
al II
In
terv
al I
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I
S
SN:
2
088
-86
94
I
J
PEDS Vo
l.
7,
No
.
1,
Mar
c
h
2
016
: 1
2
4
–
13
3
12
9
switch
e
d
o
p
e
r
a
tio
n
o
f
th
e pr
e-
ch
ar
g
i
n
g
conver
t
er
wh
er
e
the DC link
in
du
ctor
cu
rr
en
t is switch
i
n
g
b
e
tween
zero and t
h
e
pre-set curre
nt li
m
it. The
DC li
nk induct
o
r current
during t
h
e
fi
rst sub interval can
be
defi
ned as;
L
t
U
l
l
T
s
d
i
T
s
d
i
*
0
(
8
)
During the sec
o
nd sub interval, the
DC link induct
o
r c
u
rrent c
h
anges
with
the essentiall
y constant
values
provide
by e
q
.
8.
He
nce the
value at
the
end
of second inte
rval is;
L
t
U
L
T
s
d
dT
s
i
T
s
i
4
*
'
(
9
)
Finally the DC
link i
n
duct
or c
u
rrent
duri
ng inte
rv
al II
is th
e su
m
o
f
sub
in
ter
v
als
I
& II
;
t
U
L
t
d
t
U
l
l
t
d
L
T
s
i
T
s
i
4
'
0
(1
0)
In
practical the ave
r
age
DC li
nk induct
o
r curre
nt is eq
ual t
o
the
pre-set c
u
rrent lim
i
t
which will be
use
d
for
selecting the
a
c
tive an
d
passi
ve c
o
m
pone
nts
.
Figu
re 8.
Wa
v
e
fo
rm
duri
n
g
p
r
e-c
h
ar
gin
g
Int
e
rval II
,
(a
) R
-
pha
se I
G
B
T
c
u
rre
nt,
(b
) Ze
ro
crossi
n
g
detection
circuit logical OR gate o/
p,
(c
) Pea
k
c
u
rre
n
t
detectio
n logical current
fee
d
back o/
p
,
(d
)
IGBT g
a
te
pu
lses
Figu
re 9.
Wa
v
e
fo
rm
duri
n
g
p
r
e-c
h
ar
gin
g
Int
e
rval II
(Z
o
o
m
-
o
u
t versi
o
n
)
, (
a
)
R
-
p
h
ase IG
B
T
cu
rre
nt, (b
)
Zer
o
crossi
n
g
detection ci
rcuit lo
gi
cal OR
gate o/
p,
(c)
P
e
ak
cu
rr
e
n
t
d
e
t
e
c
t
i
o
n l
o
g
i
c
a
l
cu
rr
en
t
fe
e
d
b
a
ck
o
/
p,
(d
) IGB
T
gate pulses
3.
3
Selection of
Capacitor C
0
The
dc-link
bus capacitor is
use
d
in c
o
nve
rters and
i
nve
rt
ers to dec
o
upl
e the effect
of inductance
fr
om
the DC
v
o
ltage so
urc
e
to the p
o
we
r b
r
idge. T
h
e b
u
s
link capacito
r pr
o
v
ides a low
im
pedance pa
th fo
r
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PEDS
I
S
SN:
208
8-8
6
9
4
Design
of Thre
e-Phase
Three-Switch B
u
ck-Ty
pe Rectifier for Pre-C
h
argi
ng A
p
plication
(
A
na
ndh
S
)
13
0
the ripple current associat
ed with in
ve
rter har
d
s
w
itchi
ng
, play
s a m
a
jo
r r
o
le in r
e
ductio
n
of le
akage
ind
u
ctance
o
f
the in
verte
r
p
o
we
r
bri
dge
w
h
ich i
n
tu
r
n
re
duce
s
the
swit
chin
g lo
ses
of
the
po
we
r
de
vices.
Havi
ng
a lo
w i
m
pedance DC
bus
is the
ba
sis f
o
r
desi
gni
ng
an e
fficient c
o
nve
rter
[
3
]
.
The DC link bus capacitor is selected
on th
e basis of allo
wed
rip
p
le cur
r
ent,
rip
p
le vol
tage an
d th
e
DC bus capacit
o
r voltage;
f
V
t
L
U
C
2
*
5
.
0
*
*
32
0
(
1
1
)
Whe
r
e
Δ
V
0.5t
is the m
a
xim
u
m
peak-
p
ea
k r
i
pple
voltage
a
c
ross
the
dc-
b
us lin
k ca
pacitor at
50
%
P
W
M
duty
cycle,
V
bus
is the bus
voltage,
L
is the
inducta
nce a
n
d
f
is the
PW
M
freque
ncy.
3.
4
Selection
of I
n
ductor L
4
A DC c
hoke between t
h
e input rec
tifier a
nd the DC link
bus ca
pac
itor affects the
DC bus
voltage
wave
f
o
rm
and the AC
inp
u
t c
u
r
r
ent w
a
ve
fo
r
m
.
It reduce
s
the am
ount o
f
AC
rip
p
le o
n
the DC
b
u
s
volt
a
ge an
d
the AC input line harm
onics.
Additionally it offers
protec
tion a
g
ai
nst nuisance tripping
due
to voltage
spikes,
suc
h
as th
ose
cause
d by
p
h
a
s
e ad
vanci
n
g
capacitor
swit
chin
g.
DC
lin
k c
h
o
k
es ca
n
be
used
in
divi
dually
,
typically on the positive
DC
bus, or in
pairs with one in the positive a
n
d
one i
n
the
negative DC bus
branc
h
.
Whe
n
t
w
o DC
reactors are
used
on the
bus, the inductance
is additive [4].
V
I
con
f
U
L
*
*
*
2
*
3
0
*
%
(
1
2
)
Whe
r
e
Δ
V
%
is
the perce
n
tage
am
ount o
f
ac-
r
i
pple v
o
ltage a
c
ross t
h
e ind
u
c
t
or,
U
0
is the dc-b
us link
volt
a
ge,
f
is the switching
frequency
of the
converte
r, and
I
con
is th
e
dc in
du
ctor
cu
rren
t
.
For selection
of c
o
m
pone
nts
the worst cas
e ope
ra
ting c
o
nditions
has t
o
be
conside
r
ed. F
o
r the
cur
r
ent stre
sse
s of
p
o
we
r se
m
i
cond
ucto
r the w
o
rst case
is give
n by
th
e
m
a
xim
u
m
pre-set cu
rre
nt lim
it set
du
rin
g
the
pre
-
char
gin
g
c
o
n
d
i
tion.
Acco
r
d
in
g to e
quatio
n.
5, c
onsi
d
eri
ng
a
m
a
rgin f
o
r p
o
we
r sem
i
conduct
o
r
tur
n
-
o
f
f
an
d f
o
r an
ove
rs
ho
ot
of th
e
rectifier
input voltage, t
h
e IGBTs a
nd dio
d
es
with d
o
ubl
e the line-to-line
voltage bl
ocking capability ha
ve been
chosen. The
sel
ected power
sem
i
c
o
nductors
and passive
de
vices were
listed in Table
I.
Table 1. Activ
e
an
d
Pa
ssive C
o
m
pone
nts se
lection a
n
d
spe
c
ifications
Co
m
p
onen
ts
Specification
IGBT
S
i
I
G
BT
M
odule FD400R3
3
KF2C,
330
0V,
400A
Diodes
D
N
Diode M
odule DD400S3
3
KL
2C,
DD400S3
3
K2C,
3300
V,
400A
Diode
D
F
Diode M
odule DD400S3
3
K2C,
3300
V,
400A
Output I
nductor
L
4
M
a
gnetics,
Fer
r
ite-0T
4992
8E
C,
4x1.
2
m
H,
N=
37 tur
n
s,
14AW
G
Output Capacitor
C
0
E
p
cos B2562
0B,
80x10
00µF,
132
0VDC
4.
PERFO
R
MA
NCE E
V
ALU
A
TIO
N
The
perform
a
nce of three-
phase three-swi
t
ch buc
k
recti
f
ier wh
ic
h has
desig
n
e
d
in t
h
e p
r
e
v
io
us
section is e
v
al
uated
base
d
o
n
the
p
o
w
er
lo
sses, c
o
n
d
u
ction
an
d
switchi
ng
losse
s ca
n
be
deri
ved
acc
urately
base
d
on
the a
n
aly
tical de
riv
a
tions a
n
d calc
u
lations
.
4.
1
Conduc
tion
L
o
sses
The co
n
ducti
o
n
loss
of
IGB
T
and
dio
d
e has
been
calc
u
lated base
d the
forward cha
r
acteristics of the
sem
i
cond
ucto
r
(fo
r
w
ar
d v
o
ltage d
r
o
p
a
nd
fo
rwa
r
d resi
sta
n
ce of the de
vices) [5].
T
h
e
avera
g
e conduction
losses of
the IGBTs
a
n
d diodes
are;
I
rms
r
ce
I
av
U
ceo
P
cT
2
*
*
(
1
3
)
I
rms
r
d
I
av
U
do
P
cD
2
*
*
(
1
4
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN:
2
088
-86
94
I
J
PEDS Vo
l.
7,
No
.
1,
Mar
c
h
2
016
: 1
2
4
–
13
3
13
1
Whe
r
e
U
ceo
,
U
do
is the forw
ar
d v
o
ltage d
r
o
p
of I
G
B
T
a
nd
d
i
ode,
r
ce
,
r
d
is the IGBT, di
ode forwa
r
d
resistance
and
I
ac
,
I
rms
is t
h
e a
v
era
g
e, rm
s curre
nts.
During different
inte
rvals of
pre-chargi
ng condition,
conduction losses
will be
hi
gh duri
ng i
n
terval
II as rectifier
will be operating in switc
hed m
ode of operat
ion. In interval
I and III the conduction l
o
sses will
be less, as
the
powe
r sem
i
conduct
o
rs
will ON for a short
duration as t
h
e
dc link induc
t
o
r curre
nt is les
s
than
the pre-set current li
m
it.
4.
2
Switching Lo
sses
The s
w
itchin
g
losses
of
p
o
w
e
r
sem
i
cond
ucto
rs a
r
e
th
e pr
odu
ct of
switch
i
ng
en
erg
y
an
d switch
i
ng
fre
que
ncy
of
th
e
rectifier [
6
]
.
f
sw
E
offT
E
onT
P
swT
*
(
1
5
)
f
sw
E
offD
E
onD
P
swD
*
(
1
6
)
Whe
r
e E
on(T,D)
, E
off
(T,D)
is the IGB
T
an
d di
ode
on a
nd
of
f state energy
losses an
d f
sw
is the switching
fre
que
ncy
.
During interva
l
II of
pre
-
c
h
arging
condition, the dc link induct
o
r c
u
rrent reaches
t
h
e
pre
-
set curre
n
t
li
mit, due t
o
this the rectifier is
operating i
n
switched m
ode
of
operatio
n where switchi
ng losses will
be m
o
re.
In interval I
& III the dc link inductor
current
is less than the pre-set curr
ent li
mit, due to this switchi
ng l
o
sses
is less as the
rectifier operates fo
r a m
o
m
e
ntary
tim
e
depe
nds
o
n
t
h
e th
ree phase line
voltage
and
re
ctifier
cont
rol se
quence.
4.
3
Passi
ve Com
p
onen
ts
L
o
sses
In a
ddition to the losses
of ac
tiv
e com
pone
nts, losses of pa
ssive com
pone
nts ha
ve to be
considere
d
.
Generally the dc output inductor (
L
4
) and dc link capacitor (
C
0
) losses needs to be considere
d
. T
h
e core a
n
d
co
p
e
r
lo
sses
of th
e
d
c
indu
ctor
wer
e
;
10
3
*
*
*
*
4
,
W
tfe
n
B
ac
sw
f
m
k
L
P
fe
(
1
7
)
I
R
l
rms
L
P
cu
*
2
4
,
(
1
8
)
Whe
r
e
k
,
m
,
f
were
the em
pirical values
available in c
o
re
datasheet,
B
ac
is the
flux
density,
W
tfe
is t
h
e core
weig
ht an
d
R
l
is the
resistance
of the
wi
ndi
ng [7].
The l
o
sses
o
f
t
h
e
out
put ca
pa
citor
C
0
ca
n
be
calculated
via;
I
rms
co
ESR
co
P
co
2
*
(
1
9
)
Figu
re
1
0
. B
r
e
a
kd
o
w
n
o
f
t
o
tal losses at
dif
f
e
r
ent c
o
m
pone
n
t
s at
U
R,N,
U
S,N,
U
T,N
= 550
V an
d
I
dc
=2
00A
1.
23
4.
44
0.
043
5.
718
0
1
2
3
4
5
6
7
IGB
T
losses
D
iode
losses
Passive
comp.
losses
T
otal
losses
Power
Lossoes
(in
KW)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PEDS
I
S
SN:
208
8-8
6
9
4
Design
of Three-Phase Thr
ee-Switch Buck-Type Rectifier fo
r Pre-C
h
argi
ng Application
(
A
na
ndh
S
)
13
2
Wit
h
the
a
n
aly
tical equatio
ns m
e
ntione
d
fr
om
(1
3)
– (1
9)
p
r
ov
id
es th
e lo
sses
o
f
activ
e an
d p
a
ssiv
e
com
pone
nts th
ro
u
gh
w
h
ich t
h
e total losses
of t
h
e c
o
n
v
er
ter can
be eas
ily
evaluated.
The total los
s
e
s
an
d
brea
kdown of t
h
e total losses are de
picted
in
Figure
10 at a pre
-
set current li
mit of
I
dc
=200A. Additionally the
losses distrib
u
t
i
on o
f
passi
ve and activ
e co
m
ponents at diffe
rent p
r
e-set
cu
r
r
ent lim
i
t can be eval
uated base
d
on
the a
b
ove
e
quatio
ns
.
5.
DIS
C
USSI
ON
In t
h
e
pre
v
io
us
sections
the c
o
n
v
e
r
ter
wo
rki
n
g
p
r
inci
ple, s
e
lection o
f
acti
v
e a
n
d
pas
s
ive
com
pone
nts
and thei
r loss distrib
u
tion at a pre-
de
fine
d char
gin
g
cu
rre
nt of the th
ree
-
phase buc
k
-ty
p
e rectifier ha
s bee
n
analyzed.
In t
h
is section we
will com
p
are advantages,
perform
a
nce of
proposed c
onvert
e
r with existing pre-
charging techniques like Resistor-c
o
n
tactor a
rra
ngem
e
nt, Th
yristor switch and Thyris
tor bridge
rectifier
ar
r
a
n
g
e
m
e
n
t
.
Wh
ile co
m
p
ar
in
g th
e
p
r
op
osed
an
d ex
isting to
po
log
i
es,
the p
r
op
osed topo
log
y
h
a
s advan
t
ag
e
like easy in controllability as the prop
osed t
o
pology
uses IGBT’s, si
nce
IG
BT’s is a
voltage
controlled device
the gate charge, gate current
requi
re
m
e
nts
were less and gate circuit is
very sim
p
le not like thyristor based
techniq
u
es
w
h
ich re
quir
e
d c
o
m
p
lex gate c
i
rcuits. T
h
e p
r
op
ose
d
to
p
o
lo
gy
re
quire
s o
n
ly
three c
ont
rolled
switches so the control circuit requirem
e
nt is also le
ss, whereas the thyristor br
idge rectifier
requires
six
num
bers of
th
y
r
istor whic
h r
e
qui
res
c
ont
rol
circuits do
u
b
le the tim
es of
pr
o
pose
d
t
o
p
o
l
ogy
.
I
n
gene
ral
w
h
en
com
p
aring e
x
i
s
ting an
d
pr
op
ose
d
top
o
lo
gie
s
with res
p
ect to cost,
vol
um
e, p
o
we
r dissi
pation a
n
d r
o
b
u
stnes
s
th
e p
r
op
osed
co
nv
er
ter
is b
e
t
t
er than the existing topol
ogi
es. The
pr
oposed topol
ogy is cost effective as it
requires
only three IGBT
’s and less co
ntrol
circuits while other topologies
like thyristor bri
dge requires six
thyristors and double the
control circuits, thyristor switch and
resi
sto
r
co
ntactor a
rra
n
g
e
m
ent requi
res
bul
ky
resistor
ban
k
s
to lim
i
t the
pre
-
cha
r
gin
g
cur
r
ent
d
u
ri
ng
DC
link capac
itor pre
-
ch
ar
ging tim
e.
The po
we
r
dissipation of three-phase
three-switch
buck rectifier and
thyristor bridge
rectifier
is
alm
o
st sa
m
e
, as the
pr
o
pose
d
to
pol
ogy
uses
one
IGB
T
an
d f
o
u
r
po
we
r dio
d
e
s
for eac
h leg due to than t
h
e p
o
we
r dissi
pation
al
m
o
st si
m
i
lar but it’s less
com
p
ared
with
other topol
o
g
ies w
h
ic
h u
s
es resisto
r
ba
nks
f
o
r
p
r
e-c
h
argi
ng
applicatio
n. Th
e pr
op
ose
d
to
p
o
lo
gy
and t
h
y
r
istor b
r
id
ge
rectifier is less robust com
p
are
d
with resist
or bank
topologies as these uses cont
rolled switche
s whe
r
e re
sist
or c
ontact
or arrangem
ent uses electro-m
echanical
d
e
v
i
ces.
I
n
indu
str
i
al h
i
gh
p
o
wer
dr
iv
es
appr
ox
im
ate
l
y
six to se
ve
n term
inals we
re a
v
a
ilable fo
r c
u
st
om
er
access in orde
r to connect input AC supply, DC cap
acitor banks
and out
put
term
inals for c
o
nnecting the
dri
v
es, t
h
ese
term
inals wer
e
live term
inals so
bef
o
re
the
pre
-
cha
r
gin
g
ope
ratio
n
begi
ns
diag
nosis
is
mandatory to
detect the
fault
s
like
DC
b
u
s
sho
r
t,
I
nve
rter
out
put
fa
ult, P
h
ase
v
o
ltage i
m
balance, Part
ial dc
link discha
rge
.
The pr
o
p
o
s
ed top
o
lo
gy
an
d Thy
r
isto
r
B
r
i
d
ge
as rectifier can detect
th
ese faults as i
n
both t
h
e
topologies the DC link current were
m
onitored, but in
th
y
r
istor
bri
d
g
e
arra
ngem
e
nt and
othe
r ex
isting
topologies it’s not possi
ble to switch
of
f th
e contr
o
lled s
w
itched im
m
e
diatel
y as it’s
using thyristor, but in
pr
o
pose
d
t
o
p
o
l
ogy
it p
o
ssi
ble
since it uses
I
G
B
T
’s
by
s
w
itchin
g
of
f the
g
a
te pulses it is
pos
sible to
swi
t
ch o
ff
the IGBT’s the
r
eby t
h
e
DC bus pre-
c
h
ar
gin
g
is stop
pe
d im
mediately
.
The
proposed soft charging cont
rol algorith
m
us
es simple logic
gate functionalitie
s unli
k
e the
existing control techni
que uses nonlinear
d
i
sco
n
tinuo
us cu
rr
en
t co
ntrol in
thyris
tor
b
r
id
g
e
to
pol
ogies
etc, f
o
r
detecting zer
o
crossi
n
g
detection o
f
inp
u
t ac line voltage
and
detection o
f
dc link ind
u
ct
or pea
k
cu
rre
n
t
. The
pr
o
pose
d
al
g
o
r
ith
m
can
be e
a
sily
im
plem
ented t
h
r
o
ug
h l
o
w
co
st m
i
crocont
roller
(
o
r
)
FP
GA
de
vice
as the
detection technique is through logic
gates.
6.
CO
NCL
USI
O
N
In this
pa
per a
detailed o
v
er
view
of th
ree
-
pha
se
three
-
s
w
itch buc
k c
o
n
v
e
rter, its desi
g
n
p
r
oc
ed
ure
and
perform
ance was analyze
d
at a pre
-
set c
h
arging c
u
r
r
en
t and
give
n d
r
ive ratin
g,
follo
wed
by
com
p
aris
o
n
of
p
r
o
p
o
se
d t
o
p
o
lo
gy
with
existing
to
pol
ogies
we
re
do
ne.
The
R
e
sistor
co
ntactor
,
Thy
r
isto
r s
w
itch a
n
d
Magnet
o
resistance elem
ent
type soft cha
r
ging circ
uits
we
re olde
r tech
nique
s eve
n
th
ou
gh
th
ey
are robust
,
it’s n
o
t p
o
ssi
ble to c
ont
rol t
h
e dc li
nk
in
du
ctor
pea
k
c
u
r
r
e
nt an
d
dc
-b
us
capacito
r
volt
a
ge
precisely
witho
u
t
overshoot. Duri
ng di
fferent fault conditi
ons l
i
ke; brownout
condition, fault
to ground, bus fault and
part
iall
y
charged capacitors it’s
diffic
ult to detect the
fault cond
itions as there is
no possib
ility of
cont
rolling the input
DC inductor current and
capacitor charging curre
nt. The
propose
d
th
re
e
-
phase thre
e-switch buck c
o
nve
rter
type soft cha
r
ging techni
que
elim
inates the above m
e
ntio
ned
dem
e
rits and
pos
sible to
contr
o
l the d
c
bus
capacitor voltage ste
p
by
step and lim
it the DC link inductor cu
rrent wit
h
in a
peak li
m
i
t
with sm
all DC link
ind
u
cto
r
. A
ddi
tion to the ab
ove m
e
n
tioned
m
e
rits the
m
a
in adva
ntage
of pr
o
p
o
s
ed top
o
lo
gy
an
d cont
ro
l
technique
for
pre
-
cha
r
ging a
pplicatio
n is
because
of its sim
p
le in ope
r
a
tion,
less power density
c
o
m
p
ared
with existing pre-c
h
arging
c
o
ncepts a
n
d pos
s
ibility of using sam
e
c
onve
rter for both
operations
, i.e)
for
pre
-
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN:
2
088
-86
94
I
J
PEDS Vo
l.
7,
No
.
1,
Mar
c
h
2
016
: 1
2
4
–
13
3
13
3
char
gin
g
a
p
plication a
n
d
d
r
iv
ing t
h
e
VF
D.
From
the
a
b
ove m
e
ntioned a
n
alysis, the t
h
ree-phase t
h
ree
-
switc
h
buck
ty
pe rectifier
is suitable for high
powe
r drives pre-c
h
a
r
gi
ng applica
tion since
it’s
possibl
e to
pre-set the
con
v
e
r
ter c
h
ar
gin
g
c
u
r
r
ent t
o
any
pre
-
defi
ned
val
u
es
.
F
u
rt
her researc
h
is
o
n
goi
ng
, on usi
ng
t
h
ree
-
p
h
ase
three-switch
converter for bo
th
pre-c
h
argi
ng application and
dri
v
in
g
t
h
e VFD. Whe
n
we use
t
h
re
e-phase
three-switch converter fo
r
both application, two sepa
rate cont
rol m
echanism
were
required i) to
control the
peak
cha
r
gi
ng
cur
r
ent
d
u
rin
g
pre
-
cha
r
gin
g
a
nd ii) t
o
c
ont
ro
l and m
a
intain the co
nstant
dc
bu
s v
o
ltage ac
ros
s
the dc
b
u
s
link
capacitor
d
u
r
in
g
dri
v
in
g
ope
ra
tion
of
the
VF
D.
REFERE
NC
ES
[1]
Anandh S, Vijayan S, Paramasi
v
a
m S, “Bench Marking of Altern
ate Soft
-Ch
a
rgin
g Circuits for Variable-Frequen
c
y
Drives
”,
Resear
ch Journal of Ap
plied
Sc
iences, Engineering
and Technology
, Vol. 10
, (8)
2015, p
p
. 871-881
.
[2]
Anandh S, Vijay
a
n S, Par
a
ma
sivam S, “A New Approach on Three-Phas
e Thr
e
e-Switch Buck-
T
y
p
e Rectifier For
Variable-Frequency
Drives
Pre-
Charging Application”,
International Journal of A
pplied Engin
e
ering Research
,
Vol. 10
, Number
9 (2015)
pp. 23
715-23726.
[3]
Michael Salcone and Joe Bond,
“Selecting Film Bus Link Capacitors For
High Per
f
ormance Inverter Applications”,
Electronic Concepts Inc
.
[4]
Yas
k
awa El
ec
tri
c
Europ
e
,
Gm
bH, “
H
ow to
cal
cul
a
te
DC chok
e”
,
[5]
Thomas Nussbaumer, Martin
a B
a
umann and Johann W. Kolar, “ Compre
hans
ive Des
i
gn of a Three-P
h
as
e Thr
e
e
-
S
w
ith Buck-T
yp
e P
W
M
Rect
ifie
r”,
IEEE Transaction
on Pow
e
r
Electronics
, Vol. 22, No. 2
,
Mar
c
h 2007.
[6]
Dr.Duš
an Graovac, M
a
r
c
o P
ü
rs
chel, “
I
GBT P
o
wer Los
s
e
s Calculation Using the
Da
ta-Sheet Parameters”,
Infineo
n
,
Applica
tion
Note
, V1.1
, Janu
ar
y
2009.
[7]
Colonel Wm. T.
Mc Ly
m
a
n, “
Tra
n
sformer and Inductor design
ha
ndbook
”,
Th
ird
Edition
,
R
e
vised
and
Expand
ed.
BIOGRAP
HI
ES OF
AUTH
ORS
Anandh. S was born in Krishnapuram, India, in
1980. He received the B
.
E d
e
g
r
ee in
electr
i
cal
engineering fro
m N.I Colleg
e
o
f
Engineering
,
Na
gercoil,
India in 2002
and th
e M.E degree
in
Power Electron
ics and Dr
ives fr
om A.C. Colleg
e of Eng
i
neering
and Technolo
g
y
, India in
2005.
He is
pres
entl
y a
Res
earch S
c
hol
ar in Anna Univ
er
sit
y
, Ch
ennai
.
His m
a
in area of
interest
is DC-
DC Converters
,
Pre-Charging C
i
rcuits, High Pow
e
r Drives
, Contr
o
l S
y
stem Desig
n
.
Dr. Vijay
a
n
.
S was born in Tamil Nadu, India,
on
Januar
y
17
, 1968. He received the B.E. d
e
gree
from Mepco Sc
hlenk Engineeri
ng College, Siv
a
kasi, in 1989 and the M.E. d
e
gree in Power
S
y
stem from Annamalai Univ
ers
i
ty
, Ch
idambaram,
in 1993. He
was awarded Ph
.D in Electrical
Engineering fro
m College of
Engineer
ing Guin
d
y
, Anna University
Chennai in
2008. He h
a
s
published 7
pap
e
rs in Internatio
n
a
l Journa
ls and
1
0
papers
in In
ter
n
ation
a
l Conf
ere
n
ces.
He has 20
y
e
ars of experience in
the teaching prof
e
ssion. At present, he is working
as a Principal
at Sur
y
a Engin
e
ering Co
lleg
e
, Erode. His
area of
int
e
res
t
includ
es
P
o
wer El
ect
roni
cs
and Driv
es
,
DS
P
,
F
P
G
A, S
p
eci
al M
a
chin
es
a
nd Control
.
Dr. Paramasivam. S was
born in Coimbatore, I
ndia in
1971.
He receiv
e
d
the B
.
E. degr
ee f
r
om
GCT, Coimbator
e
, in 1995
, th
e
M.E. deg
r
ee fro
m
P.S.G College of Techno
log
y
,
Coimbatore,
in
1999, and
th
e P
h
.D. d
e
gree fro
m College of
Engi
neer
ing, Anna University
, Ch
ennai, in
2004.
His inter
e
sts include power
electr
onics, AC moto
r
drives, DSP- and FPGA-based motor controls,
power-factor cor
r
ection,
magnetic
design, fuzzy
logic, neur
al ne
tworks, and controller design for
wind energ
y
co
nversion s
y
stem
s. He has publis
hed over 32 pap
e
rs on various aspects of SR
M
and induction motor drives in in
ternational journ
a
ls and conf
eren
ces worldw
ide. Presently
he is
working at Danf
oss Industries,
Ch
ennai. He
is also a R
e
view
er
for man
y
IEEE journals
, Acta
Press, Inderscien
ce
journals
, Elsevier
journa
ls
, Hindwai journ
a
ls,
and IE
EE
conf
er
ences
.
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