Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
Vol
.
6
,
No
. 2,
J
une
2
0
1
5
,
pp
. 30
5~
31
7
I
S
SN
: 208
8-8
6
9
4
3
05
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Desi
gn and Cont
rol
for t
h
e Buck-
B
oost Converter
Combining 1-Plus-D Converter
and Synchronous Rectified
Buck Convert
ers
Jeevan Naik
Project Engin
eer
, CSIR -
Nation
a
l Aerospac
e
Lab
o
ratories, B
a
ngalore –
560 017
, I
ndia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
J
u
n 21, 2014
Rev
i
sed
Feb 9, 20
15
Accepte
d
Mar 5, 2015
In this paper
,
a d
e
sign and contro
l for
the buck-bo
ost converter, i.e., 1-plus-
D
convert
er with a positive output
voltag
e
,
is presented, which
com
b
ines the 1-
plus-D converter and the s
y
n
c
hronous
rectified (SR) buck converter
. B
y
doing so, th
e pr
oblem in voltag
e
bucking
of th
e 1-plus-D conv
erter
can
b
e
solved, thereb
y
incr
easing the
application capability
of the
1-plus-D
converter. Since such a converter ope
rates in continuous conduction mode
inheren
t
ly
,
it po
ssesses the nonpulsati
ng outpu
t current, th
ereb
y
not o
n
l
y
decreasing the
current stress on the out
put cap
acitor but also r
e
ducing th
e
output voltag
e
ripple. Above all, both
the 1-plu
s
-D converter and the SR
buck conv
erter, combined
into
a bu
ck–boost converter
with
no
right-h
alf
plane
zero
,
us
e
t
h
e s
a
m
e
power s
w
itches
,
ther
eb
y caus
i
ng
the r
e
q
u
ired c
i
rcu
it
to be compact and the corr
esponding cost
to b
e
down. Further
m
ore, durin
g
the magnetizatio
n period
,
the
inp
u
t volta
ge of
the 1-plus-D converter
comes
from the input
voltag
e
source, whereas
during
the demagnetization period
,
the inpu
t voltage of the 1-p
l
us-D conve
rter comes
from the output voltag
e
of
the S
R
bu
ck
con
v
erter
.
Keyword:
1-
pl
us
-D
c
o
n
v
e
rt
er
B
u
ck
- bo
ost
c
o
nve
rt
er
Right-half plane
zero
Syn
c
hro
nou
s rectif
ied
(
S
R
)
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Jeeva
n
Naik
Project E
n
gine
er,
CSIR - National Aeros
p
ace L
a
boratories,
B
a
ngal
o
re – 5
6
0
01
7,
I
n
di
a.
Em
a
il: j
eev
annaik
@h
o
t
m
a
il.c
o
m
1.
INTRODUCTION
As ge
neral
l
y
r
ecog
n
i
zed
, m
a
ny
appl
i
cat
i
o
n
s
req
u
i
r
e v
o
l
t
a
ge-
b
ucki
ng/
bo
ost
i
n
g co
nve
rt
ers, s
u
ch as
po
rt
abl
e
devi
c
e
s, car el
ect
r
o
ni
c de
vi
ces, et
c. Thi
s
i
s
beca
use t
h
e
bat
t
e
ry
has
qui
t
e
l
a
r
g
e vari
at
i
o
ns i
n
out
put
vol
t
a
ge
, a
nd
h
e
nce, t
h
e ad
di
t
i
onal
s
w
i
t
c
hi
n
g
p
o
w
er
su
p
p
l
y
i
s
i
ndi
spe
n
sa
bl
e f
o
r
pr
ocess
i
ng t
h
e va
ri
ed
i
n
p
u
t
vol
t
a
ge
s
o
as
t
o
ge
nerat
e
t
h
e st
a
b
i
l
i
zed
out
put
v
o
l
t
a
ge
. T
h
ere
are
se
veral
t
y
pe
s
of
n
o
n
i
s
ol
at
ed
v
o
l
t
a
g
e
b
u
c
k
/
boo
sting co
nv
er
ter
[1
]
–
[9
], su
ch
as b
u
c
k–
boo
st con
v
e
r
t
er
, sing
le-
e
nd
ed
p
r
im
ar
y-
in
du
ctor
conv
er
ter
(SEP
IC),
Cu
k
con
v
e
r
ter, Zet
a
con
v
e
r
ter,
L
uo c
o
nv
erte
r a
nd its
deri
vatives, etc.
Howe
ver, these c
onverters,
ope
rat
i
n
g i
n
t
h
e cont
i
n
u
ous c
o
n
d
u
ct
i
on m
ode (C
C
M
),
po
ssess ri
g
h
t
-
hal
f
pl
ane ze
ros
,
t
hus ca
usi
n
g s
y
st
em
stab
ility to
b
e
lo
w. C
o
n
s
equ
e
n
tly, a
KY
b
u
c
k–
boo
st con
v
e
rter
[10
]
has b
e
en
presen
ted
t
o
conq
uer the
afo
r
em
ent
i
one
d
pr
o
b
l
e
m
s
, but
i
t
has
a se
r
i
ous
p
r
o
b
l
e
m
in
fo
ur
po
wer
swi
t
c
hes
use
d
,
t
h
ere
b
y
ca
usi
n
g
t
h
e
corres
ponding
cost to be
up.
In
or
der t
o
re
d
u
ce t
h
e
num
ber o
f
p
o
we
r s
w
i
t
c
hes i
n
[
1
0]
, t
h
e 1
-
pl
us-
D
c
o
nve
rt
er a
nd t
h
e SR
buc
k
co
nv
er
ter
,
co
mb
in
ed
in
t
o
a
bu
ck–b
oo
st co
nv
er
ter,
b
o
t
h
u
s
e th
e sam
e
p
o
wer
switch
e
s.
Asid
e
fro
m
th
is, th
e
pr
o
pose
d
c
o
n
v
e
rt
er ha
s n
o
ri
ght
-hal
f
pl
ane
zero
du
e t
o
the in
pu
t con
n
e
cted
to
th
e
o
u
t
pu
t du
ring
th
e t
u
rn
-on
p
e
ri
o
d
, an
d
t
h
is con
v
e
rter al
ways o
p
e
rates in CCM d
u
e
to
t
h
e
p
o
s
itiv
e and n
e
g
a
tiv
e indu
cto
r
cu
rren
ts ex
i
s
tin
g
at lig
h
t
lo
ad
si
m
u
ltan
e
o
u
s
ly. As co
m
p
ared with
th
e c
onverters previ
o
usly stated
, this co
nv
erter has th
e
no
n
pul
sat
i
n
g
out
put
i
n
d
u
ct
o
r
cu
rre
nt
, t
h
e
r
eby
causi
ng t
h
e cu
rre
nt
st
r
e
ss o
n
t
h
e
ou
t
put
capaci
t
o
r
t
o
be
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
305
–
3
17
30
6
decrease
d
,
an
d
hence
,
t
h
e
co
rr
esp
o
n
d
i
n
g
out
p
u
t
v
o
l
t
a
ge
ri
p
p
l
e
t
o
b
e
sm
al
l
.
M
o
re
ove
r,
suc
h
a c
o
nve
rt
er
h
a
s t
h
e
p
o
s
itiv
e
o
u
t
p
u
t
v
o
ltag
e
d
i
fferen
t
fro
m
th
e n
e
g
a
tiv
e ou
tpu
t
v
o
ltag
e
o
f
t
h
e b
u
c
k–
boo
st con
v
e
rter.
In
t
h
is p
a
p
e
r,
th
e d
e
tailed
illu
stration
of th
e o
p
e
ration
of th
is conv
erter
is g
i
v
e
n
,
along
with
so
m
e
si
mu
lated
resu
lts prov
ided
t
o
ve
ri
fy
t
h
e
ef
fect
i
v
enes
s
of t
h
e
pr
o
pose
d
t
o
pol
ogy
.
Prior to
th
e end
of th
is section
,
th
ere is a com
p
arison bet
w
een the converters pre
s
ente
d in [11] and
t
h
e
pr
op
ose
d
con
v
e
r
t
e
r.
Si
n
ce t
h
e
p
r
o
p
o
se
d c
o
nve
rt
er i
s
use
d
t
o
b
u
ck/
b
o
o
st
v
o
l
t
a
ge,
t
h
e
v
o
l
t
a
ge
b
oost
i
n
g
ran
g
e i
s
n
o
t
so hi
g
h
, t
h
at
i
s
, t
h
e vol
t
a
ges a
c
ross t
w
o e
n
er
gy
-t
ra
nsfe
rri
ng
capaci
t
o
rs C
1
and C
2
a
r
e b
o
t
h
D
ti
m
e
s
th
e in
pu
t v
o
ltag
e
, wh
ere D is th
e d
u
t
y
cycle o
f
th
e gate d
r
iv
ing
sign
al for th
e m
a
i
n
switch. Reg
a
rd
i
ng
th
e conv
erters shown in
[1
1], th
e
v
o
ltag
e
s acro
ss t
w
o
en
ergy
-t
rans
fer
r
i
n
g
capa
c
itors
C1a a
n
d
C1
b
fo
r the
hy
b
r
i
d
C
u
k
co
nve
rt
er,
t
h
e
hy
bri
d
Zet
a
c
o
nv
ert
e
r, a
n
d t
h
e h
y
b
ri
d
SEP
I
C
c
o
n
v
e
r
t
e
r a
r
e
1/
(1
−
D)
, D/(1
−
D)
, and
1/
(
1
−
D) ti
m
e
s
th
e in
pu
t vo
ltag
e
, resp
ectiv
el
y. There
f
ore, t
h
e converters
sh
o
w
n i
n
[
1
1]
have
hi
g
h
er
v
o
l
t
a
ge
co
nv
er
sion
r
a
t
i
o
s
th
an
th
at
o
f
t
h
e pr
opo
sed
conv
er
ter.
There
f
ore, from
an
indu
st
ri
al
poi
nt
of vi
ew,
t
h
e
conve
r
ters s
h
own i
n
[11] are
suitable for s
u
stainable
ene
r
gy applications
, whe
r
eas the
proposed c
o
nve
rter is
suitable for
portable products.
Furt
herm
ore,
since the propos
ed c
o
nvert
e
r co
m
e
s fro
m
t
h
e 1-pl
u
s
-
D
co
nve
rt
er,
t
h
e det
a
i
l
e
d
com
p
ari
s
on
s b
e
t
w
een t
h
e p
r
op
ose
d
buc
k
–
b
o
o
st
c
o
n
v
e
r
t
e
r an
d t
h
e 1
-
pl
us
-D c
o
nv
er
t
e
r are
descri
bed
as
fo
llows.
1)
Bo
th
co
nv
erters always op
erate in
CCM. That is, th
e
n
e
g
a
ti
v
e
cu
rren
t can
b
e
allowed at lig
h
t
lo
ad
, bu
t t
h
e
co
rresp
ond
ing
av
erag
e cu
rrent
m
u
st b
e
po
sitiv
e.
2)
B
o
t
h
c
o
nve
rt
er
s ha
ve i
ndi
vi
d
u
a
l
out
put
i
n
duc
t
o
rs,
t
h
e
r
eby
ca
usi
n
g t
h
e
out
p
u
t
cu
rre
nt
s t
o
b
e
n
o
n
p
u
l
s
at
i
n
g
.
3)
Th
e propo
sed co
nv
erter h
a
s o
n
e
ad
d
ition
a
l in
du
ctor
an
d
on
e add
itio
n
a
l cap
acito
r so
as to
ex
ecu
t
e vo
ltag
e
buc
ki
n
g
/
b
o
o
st
i
ng as c
o
m
p
are
d
wi
t
h
t
h
e 1
-
pl
us-
D
c
o
n
v
ert
e
r
.
The m
a
xim
u
m
vol
t
a
ge co
n
v
ersi
on
rat
i
o
s
fo
r
bot
h a
r
e ide
n
tical, equal to 2.
Both t
h
ese
c
o
n
v
ert
e
r
s
ca
n
ope
rat
e
bi
di
rect
i
o
n
a
l
.
4)
Th
e pro
p
o
s
ed
co
nv
erter work
s with
t
h
e b
a
ck
w
a
rd
vo
ltage co
nv
er
sion
ra
t
i
o
of
0.
5/
(
1
-
D
),
w
h
ereas t
h
e 1-
pl
us
-D
co
n
v
ert
e
r
wo
rks
wi
t
h
t
h
e
back
wa
rd
v
o
l
t
a
ge c
o
n
v
e
r
si
on
rat
i
o
o
f
1/
(
2
-
D
)
.
2.
PROP
OSE
D
CO
NVE
RTER
ST
RU
CT
U
R
E
Fi
gu
re 1
s
h
ow
s
a pr
op
ose
d
b
u
ck
–
b
o
o
st
c
o
n
v
ert
e
r
,
whi
c
h com
b
i
n
es
t
w
o con
v
e
r
t
e
rs usi
n
g
t
h
e sam
e
p
o
wer switch
e
s. On
e is th
e
SR bu
ck
co
nverter
,
wh
ich
is bu
ilt u
p
b
y
t
w
o power swi
t
ch
es S
1
and
S
2
, one
in
du
ctor
L
1
,
one ene
r
gy-tra
nsferring capaci
tor C
1
, wh
ereas th
e o
t
h
e
r is
th
e 1-p
l
u
s
-D co
nv
erter,
wh
ich
is
con
s
t
r
uct
e
d by
t
w
o p
o
we
r s
w
i
t
c
hes S
1
and S
2
, on
e po
wer
d
i
od
e D
1
w
h
i
c
h i
s
di
sco
n
n
ect
ed f
r
om
t
h
e i
nput
vol
t
a
ge
s
o
u
r
ce
an
d c
o
n
n
ect
e
d
t
o
t
h
e
out
p
u
t
of
t
h
e
SR
bu
ck
co
nv
er
ter
,
on
e en
erg
y
-tra
n
s
fer
r
in
g ca
pacitor C
2
,
o
n
e
ou
tpu
t
indu
ctor
L
2
, a
n
d
o
n
e
out
put
ca
pa
ci
t
o
r C
0
. T
h
e
o
u
t
p
ut
l
o
a
d
i
s
si
gni
fi
ed
by
R
0
. Furt
herm
ore,
d
u
ri
ng
t
h
e
m
a
gnet
i
zat
i
on pe
ri
o
d
, t
h
e
i
nput
vol
t
a
ge
of t
h
e
1-
pl
us
-
D
co
nve
rt
er c
o
m
e
s from
t
h
e inp
u
t
v
o
l
t
a
ge s
o
u
r
ce,
whe
r
eas
d
u
ri
n
g
t
h
e
dem
a
gnet
i
zat
i
on pe
ri
o
d
, t
h
e i
n
p
u
t
v
o
l
t
a
ge
of
t
h
e
1-
pl
us
-D
c
o
n
v
e
rt
er c
o
m
e
s fr
om
t
h
e
out
put
v
o
l
t
a
ge of
t
h
e SR
b
u
c
k
co
nve
rt
er.
Fig
u
r
e
1
.
Propo
sed
b
u
c
k–
boost
con
v
e
r
t
er
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
D
e
sign
an
d Con
t
ro
l f
o
r th
e Bu
ck-
Boo
s
t Converter Com
b
i
n
in
g 1-
Plus-D
C
o
n
v
erter and
…
(Jeevan N
a
ik)
30
7
In
add
ition
,
du
ri
n
g
th
e start
u
p
p
e
ri
o
d
wit
h
S
1
bei
n
g O
N
an
d S
2
bei
n
g OF
F, L
1
and L
2
are bot
h
magnetized.
At the sam
e
time, C
1
i
s
cha
r
g
e
d, a
n
d he
nce,
t
h
e v
o
l
t
a
ge a
c
ross
C
1
is positiv
e, wh
ereas C
2
is
reve
rsi
n
g c
h
ar
ged
,
an
d
hence
,
t
h
e v
o
l
t
a
ge a
c
ross C
2
i
s
neg
a
t
i
v
e. Seq
u
e
n
t
i
a
l
l
y
, duri
ng t
h
e st
art
up
pe
ri
o
d
wi
t
h
S
1
bei
n
g OFF and S
2
bei
ng
ON
, L
1
and L
2
are both
dem
a
gnetized. At t
h
e sam
e
time, C
1
i
s
di
schar
g
e
d
. Si
nce
C
2
is co
n
n
ected
in
p
a
rallel with
C
1
, C
2
is re
v
e
rse ch
arg
e
d
with
th
e vo
ltage acro
ss C
2
bei
ng
fr
om
negat
i
v
e t
o
p
o
s
itiv
e, and
fi
n
a
lly, th
e v
o
ltag
e
acro
ss C
2
is the sa
m
e
as the voltage across C
1
. After th
is ti
m
e
o
n
w
ard
,
th
e
work
i
n
g
b
e
h
a
vio
r
o
f
th
is con
v
erter
will fo
llow th
e ti
m
i
n
g
seq
u
e
n
ce
shown
in
Figure
2
.
Fi
gu
re
2.
Key
wave
f
o
rm
s of t
h
e
pr
o
pose
d
c
o
nve
rt
er
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
305
–
3
17
30
8
3.
BASI
C OPE
R
ATIN
G P
R
I
N
CIPLES
Before th
is sectio
n
is tak
e
n u
p
,
t
h
ere are so
m
e
assu
mp
tio
ns are g
i
ven
as fo
llo
ws:
1
)
all th
e
com
pone
nt
s ar
e i
d
eal
;
2
)
t
h
e
bl
an
ki
n
g
t
i
m
es bet
w
ee
n
S
1
an
d S
2
are o
m
it
ted
;
3) th
e
vo
ltag
e
d
r
o
p
s across the
swi
t
c
hes an
d d
i
ode d
u
r
i
n
g t
h
e t
u
rn
-o
n pe
ri
o
d
are ne
gl
i
g
i
b
l
e
;
4) t
h
e val
u
e
s
of C
1
and C
2
are large enough t
o
keep V
C1
and
V
C2
al
m
o
st con
s
tan
t
, t
h
at is,
v
a
riation
s
in
V
C1
and
V
C1
are
qui
t
e
sm
al
l
dur
i
ng t
h
e
cha
r
gi
n
g
an
d
d
i
sch
a
rg
i
n
g p
e
riod
; 5) th
e d
c
in
pu
t vo
ltag
e
i
s
sign
ified b
y
V
i
, t
h
e
dc
out
p
u
t
v
o
l
t
a
ge i
s
re
prese
n
t
e
d
by
V
0
, the
dc o
u
t
p
ut
c
u
r
r
e
nt
i
s
ex
press
e
d by
I
0
, th
e
g
a
te driv
ing
si
g
n
a
ls
for S
1
a
nd
S
2
are indi
cated by M
1
a
nd M
2
,
respect
i
v
el
y
,
t
h
e vol
t
a
ges
on
L
1
and L
2
are
denoted by
v
L1
and v
L2
,
res
p
e
c
tively, the currents i
n
L
1
and L
2
are
si
gni
fi
e
d
by
i
L1
and i
L2
, respectiv
ely, an
d
th
e in
pu
t curren
t
is e
x
p
r
essed
b
y
ii; an
d
6
)
th
e cu
rren
t
s flo
w
i
ng
th
ro
ugh
L
1
and L
2
are bo
th positiv
e.
Sin
ce
t
h
is
co
nv
erter
always o
p
e
rates
i
n
CC
M in
h
e
ren
tly,
th
e tu
rn-o
n
type is (D, 1
−
D
)
,
whe
r
e D is
t
h
e d
u
t
y
cy
cl
e of t
h
e
gat
e
dri
v
i
n
g si
gnal
fo
r
S
1
and
1
−
D is th
e
d
u
t
y cycle o
f
th
e
g
a
te
d
r
iv
in
g sign
al for S
2
.
Fi
gu
re 2 s
h
o
w
s t
h
e key
wave
fo
rm
s of t
h
e pr
op
ose
d
co
n
v
ert
e
r wi
t
h
a swi
t
c
hi
n
g
pe
ri
o
d
o
f
Ts un
de
r i
L1
and i
L2
b
e
ing
p
o
sitiv
e
for an
y ti
m
e
. It is no
ted th
at t
h
e inpu
t current wav
e
fo
rm
is p
u
l
sating
.
4.
OPERATING STATES
There
are
t
w
o
ope
rat
i
n
g st
at
e
s
t
o
be
desc
ri
b
e
d
State 1:
As s
h
ow
n i
n
F
i
gu
re
3,
S
1
is
t
u
rn
ed
ON bu
t S
2
is tu
rn
ed
OFF.
Du
ring
t
h
i
s
state, th
e i
n
pu
t vo
ltag
e
prov
id
es
energy for L
1
a
nd C
1
.
He
nce,
the voltage across L
1
is V
i
m
i
nus
V
C1
,
th
er
eb
y c
a
u
s
i
n
g
L
1
t
o
be m
a
gnet
i
z
e
d
a
n
d
C
1
is charge
d.
Fi
gu
re
3.
C
u
rre
nt
fl
ow
i
n
st
at
e
1
At th
e
sam
e
ti
me, th
e inpu
t
v
o
ltag
e
, t
o
g
e
t
h
er
with
C
2
,
pr
ov
id
es th
e en
erg
y
fo
r L
2
a
n
d t
h
e
out
put
.
Hen
ce, t
h
e
vol
t
a
ge
acr
oss
L
2
is
V
i
pl
us
V
C2
m
i
nus V
0
, th
er
eb
y causin
g L
2
t
o
be
m
a
gnet
i
zed,
a
n
d
C
2
is
d
i
scharg
ed
.
There
f
ore,
t
h
e
rel
a
t
e
d e
quat
i
o
ns a
r
e
depi
ct
e
d
as f
o
l
l
o
ws:
v
V
V
(1
)
v
V
V
V
(2
)
State 2:
As s
h
ow
n
i
n
F
i
gu
re
4,
S
1
is tu
rn
ed
OFF bu
t
S
2
is t
u
rn
ed
ON.
Du
ri
n
g
th
is state, th
e energ
y
stored
in
L
1
and C
1
is re
leased to C
2
an
d t
h
e
out
put
vi
a L
2
. He
nce, the voltage ac
ros
s
L
1
i
s
m
i
nus V
C1
, th
er
eb
y cau
s
i
ng
L
1
t
o
be dem
a
gnet
i
zed
a
n
d
C
1
is d
i
sch
a
rg
ed.
At th
e sam
e
ti
me, th
e
v
o
ltage acro
s
s L
2
is
V
C2
m
i
nus V
0
, there
b
y
causing L
2
t
o
be
dem
a
gnet
i
zed a
nd C
2
is
charge
d. T
h
e
r
efore
,
the as
s
o
ciated e
quati
ons
are
desc
ribed as
fo
llows:
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
D
e
sign
an
d Con
t
ro
l f
o
r th
e Bu
ck-
Boo
s
t Converter Com
b
i
n
in
g 1-
Plus-D
C
o
n
v
erter and
…
(Jeevan N
a
ik)
30
9
v
V
(3
)
v
V
V
(4
)
V
V
(5
)
B
y
appl
y
i
n
g
t
h
e v
o
l
t
a
ge-se
c
o
n
d
bal
a
nce t
o
(
1
)
an
d
(3
),
t
h
e
fol
l
o
wi
n
g
e
q
ua
t
i
on ca
n
be
o
b
t
a
i
n
ed a
s
V
V
∗D
∗T
V
∗
1D
∗T
0
(6
)
Fi
gu
re
4.
C
u
rre
nt
fl
ow
i
n
st
at
e
2
There
f
ore,
by
s
i
m
p
l
i
f
y
i
ng (
6
)
,
t
h
e f
o
l
l
o
wi
n
g
e
quat
i
o
n ca
n
be
obt
ai
ne
d a
s
V
∗D
∗T
D∗V
∗T
V
∗T
D∗V
∗T
0
V
∗D
∗T
V
∗T
0
V
∗D
∗T
V
∗T
V
D
∗
V
(
7
)
Seq
u
ent
i
a
l
l
y
, by
appl
y
i
ng t
h
e
vol
t
a
ge
-seco
n
d
bal
a
nce t
o
(
2
) an
d (
4
)
,
t
h
e
fol
l
o
wi
ng e
q
u
a
t
i
on can b
e
obt
ai
ne
d a
s
V
V
V
∗D
∗T
V
V
∗
1
D
∗T
0
(8
)
Hen
c
e, b
y
substitu
tin
g
(5
) and
(7
) in
t
o
(8
),
th
e vo
ltag
e
con
v
e
rsion
ratio
o
f
th
e
p
r
op
o
s
ed
con
v
erter
can be obt
ai
ne
d
as
V
∗D
∗T
V
∗D∗
T
V
∗D
∗
T
V
V
∗
1D
∗T
0
V
∗D
∗T
V
∗D∗
T
V
∗D
∗
T
V
∗T
V
∗D
∗
T
V
∗T
V
∗D
∗
T
0
V
∗D
∗T
V
∗T
V
∗T
0
V
∗D
∗T
V
∗T
V
∗T
T
V
∗D
V
V
∗T
V
∗D
V
V
Using
equ
a
tio
n (5
) and
(7), t
h
e fo
llo
wi
n
g
equ
a
tio
n can be
ob
tain
ed as
V
∗D
V
V
V
∗D
D∗
V
V
2∗V
∗D
V
2
∗
D
(
9
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
305
–
3
17
31
0
There
f
ore,
s
u
c
h
a c
o
nve
rt
er
c
a
n
ope
rat
e
i
n
t
h
e
buc
k m
ode
as the
duty cycle D is sm
aller than
0.5, whe
r
eas it
can
o
p
e
rate in th
e
b
o
o
s
t m
o
d
e
as D is larg
er t
h
an 0.5.
In
add
itio
n, b
a
sed
on
(5), (7),
and
(9),
t
h
e d
c
vo
ltag
e
s across C1
and
C
2
can
b
e
ex
pressed
to
b
e
V
V
D
∗
V
V
V
D
∗
V
2
∗
D
V
V
0
.
5
V
(
1
0
)
5.
DESIG
N
C
A
L
CUL
ATIO
N
In
t
h
is sectio
n, th
e d
e
si
g
n
o
f
in
du
ctors and cap
acito
rs are
m
a
in
ly tak
e
n
in
to
accoun
t.
Before th
is
sectio
n
is tak
e
n
up
, th
ere are so
m
e
sp
ecificatio
n
s
to
b
e
g
i
v
e
n
as fo
llows: 1
)
th
e d
c
in
pu
t v
o
ltag
e
Vi is fro
m
10
V t
o
1
6
V;
2
)
t
h
e dc
o
u
t
p
ut
vol
t
a
ge
V
0
i
s
12
V;
3
)
t
h
e
rat
e
d dc l
o
ad c
u
r
r
e
nt
I
0
rated
is 3
A
;
4
)
th
e swit
ch
i
ng
fre
que
ncy
fs i
s
20
0
k
H
z;
an
d
5
)
t
h
e
nam
e
of
S
1
a
n
d
S
2
i
s
M
O
SFE
T a
n
d
di
ode
D
.
5.
1. I
nduc
tor
Deisgn
From
an expe
r
i
m
e
nt
al
poi
nt
of vi
e
w
, t
h
e i
n
duct
o
r i
s
desi
g
n
ed
un
der t
h
e
con
d
i
t
i
on t
h
at
no
negat
i
v
e
cu
rren
t i
n
t
h
e
in
du
ctor ex
ists abo
v
e
2
5
%
of th
e rated
d
c
lo
ad
curren
t
.
Th
erefo
r
e, in th
is letter, t
h
e
critical
p
o
i
n
t
b
e
tween
p
o
s
itiv
e cu
rrent an
d
n
e
g
a
tiv
e
cu
rren
t in
th
e
i
n
du
ctor is assumed
at 2
5
%
of th
e rated
d
c
l
o
ad
current. T
h
ere
f
ore
,
the
p
eak
-t
o-
pea
k
val
u
es
of
i
L1
and i
L2
a
r
e expre
ssed
by
Δ
i
L1
and
Δ
i
L2
,
respectively, a
n
d ca
n
be
obt
ai
ne
d
ac
cor
d
i
n
g t
o
t
h
e
f
o
l
l
o
wi
ng
eq
uat
i
on:
∆i
∆
i
0
.
5
I
(
1
1
)
∆i
∆
i
0
.
5
∗
3
There
f
ore,
∆i
and
∆i
ar
e 1.5A
.
Sin
ce t
h
e
h
i
gh
in
pu
t
v
o
ltag
e
mak
e
s th
e indu
ctor
n
o
t
easier to escap
e
from
th
e n
e
g
a
tiv
e curren
t
th
an
th
e lo
w inpu
t v
o
ltag
e
, th
e ind
u
c
t
o
r
d
e
sign
is
m
a
in
ly d
e
te
rm
in
ed
b
y
th
e h
i
gh
in
pu
t voltag
e
, n
a
m
e
ly,
1
6
V.
Hence
,
t
h
e co
r
r
esp
o
ndi
ng m
i
ni
m
u
m
dut
y
cycl
e D
mi
n
i
s
0.375
. M
o
re
o
v
er
, base
d o
n
(1
0
)
,
V
C1
and
V
C2
are bot
h
0.
5V
0
,
nam
e
ly, 6V.
Also, t
h
e
values
of L
1
and
L
2
ca
n
be
obt
a
ined ac
cordi
n
g to the
followi
ng equations:
L
D
∗
V
V
∆i
∗
f
(1
2)
L
0
.
375
∗
16
6
1
.
5
∗
200k
L
1
5
μ
H
Si
m
ilarly, L
2
L
D
∗
V
V
V
∆i
∗
f
(1
3)
L
0.375
∗
16
6
1
2
1
.
5
∗
200k
L
1
5
μ
H
There
f
ore, the
values
of L
1
and
L
2
bo
th
are calcu
l
ated
to b
e
n
o
t
less th
an
12
μ
H,
he
re we use
d
14µ
H.
5.
2. C
a
p
a
ci
t
o
r
Dei
s
gn
1
.
Ou
tpu
t
Capacito
r
Design
Pri
o
r t
o
desi
gn
i
ng C
o
, it is as
su
m
e
d
th
at th
e o
u
t
pu
t vo
ltag
e
rip
p
l
e
Δ
v
o
is smaller th
an
1
%
o
f
th
e dc
out
put
v
o
l
t
a
ge
, t
h
at
i
s
,
Δ
v
o
i
s
sm
aller than 120 m
V
. He
nce, the e
q
ui
val
e
nt series
resis
t
ance of t
h
e
output
capacitor
ESR can be represe
n
ted by
ESR
∆
v
∆i
(1
4)
ESR
120m
1.5
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I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
D
e
sign
an
d Con
t
ro
l f
o
r th
e Bu
ck-
Boo
s
t Converter Com
b
i
n
in
g 1-
Plus-D
C
o
n
v
erter and
…
(Jeevan N
a
ik)
31
1
ESR
80m
Accord
ing
l
y, ESR is calcu
la
ted
to
b
e
sm
a
l
l
e
r th
an
40
m
Ω
, and eve
n
t
u
al
l
y
, one Ni
pp
o
n
C
h
em
i
-
C
on (N
C
C
)
1-
plus-D
series ca
pacitor of
370
μ
F wi
t
h
ESR
e
qual
t
o
36m
Ω
is ch
ose
n
fo
r C
0
.
2. Ene
r
gy
-Tra
n
s
fer
r
in
g
Ca
pacitor Desig
n
Prio
r t
o
desig
n
i
ng
the e
n
e
r
gy
-tran
s
fe
rrin
g
c
a
pacitors
C
1
an
d C
2
, it is assu
m
e
d
th
at th
e
v
a
lu
es of C
1
and C
2
are large e
n
ough t
o
keep V
C1
a
nd
V
C2
alm
o
st
at
6V
, an
d
he
nce
,
va
ri
at
i
ons i
n
V
C1
and
V
C2
are quite
sm
al
l
and are
defi
ned t
o
be
Δ
V
C1
and
Δ
V
C2
,
resp
ect
i
v
el
y
.
B
a
sed on
t
h
i
s
assum
p
t
i
on,
Δ
V
C1
and
Δ
V
C2
are
bot
h
set to
sm
a
ller t
h
an
1
%
o
f
V
C1
and
V
C2
,
res
p
e
c
t
i
v
el
y
,
nam
e
ly
, bot
h are sm
al
l
e
r than 60m
V
. Also, in State
1, C
1
is charge
d
whe
r
eas C
2
is
discharge
d
. The
r
efore, t
h
e
values
of C
1
an
d C
2
m
u
st satisfy th
e
follo
wing
eq
u
a
ti
o
n
s
:
C
I
∗D
∆V
∗
f
(1
5)
C
I
∗D
∆V
∗
f
(1
6)
∴
C
3∗0
.
6
60m
∗
200k
C
150
μ
F
Si
m
ilarly
C
3∗0
.
6
60m
∗
200k
C
150
μ
F
Since the m
a
xim
u
m duty cycle D
ma
x
occurs
at
t
h
e i
nput
v
o
l
t
a
ge o
f
1
0
V
,
nam
e
ly
, 0.6
,
bot
h t
h
e
val
u
e
s
of C
1
and C
2
are
n
o
t less th
an
150
μ
F. Finally, C
1
and C
2
ha
ve
i
ndi
vi
d
u
al
Ni
p
p
o
n
C
h
em
i-C
o
n
1-plus-D
series
capacitors
of
470
μ
F.
6.
CO
NTR
O
L D
E
SIGN
Th
e aim
o
f
th
e feedb
ack
con
t
ro
l circu
it is to
regu
late th
e ou
tpu
t
vo
ltag
e
v
0
. Th
is vo
ltag
e
is co
m
p
ared
with
t
h
e refe
re
nce value
V
0
, an
d th
e resu
lting
erro
r is
feed t
o
PI con
t
ro
ller
o
u
t
p
u
t
of t
h
e PI si
g
n
a
l co
m
p
ared to
a triang
le sign
al u
s
ing
a co
m
p
arato
r
, as illu
strated
i
n
Fi
g
u
re
5
.
Fi
gu
re
5.
Ge
ne
rat
i
o
n
o
f
t
h
e
s
w
i
t
c
hes
gat
e
si
gnal
s
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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:
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94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
305
–
3
17
31
2
th
ere are three
step
s to
on
lin
e tu
n
e
th
e p
a
rameters o
f
th
e vol
t
a
ge c
o
nt
rol
l
er t
o
be desc
ri
bed i
n
t
h
e fol
l
owi
n
g
.
St
ep 1:
t
h
e pr
o
p
o
r
t
i
o
nal
gai
n
kp i
s
t
une
d f
r
o
m
zero t
o
t
h
e val
u
e whi
c
h m
a
kes t
h
e o
u
t
p
ut
vol
t
a
ge
very
cl
ose t
o
abo
u
t
8
0
% o
f
t
h
e pre
s
cri
b
e
d
out
put
vol
t
a
ge
.
St
ep 2:
aft
e
r
t
h
is, th
e in
teg
r
al g
a
in
k
i
is tu
ned
fro
m
zero
to
th
e
val
u
e
w
h
i
c
h m
a
kes t
h
e o
u
t
p
u
t
vol
t
a
ge
ve
ry
cl
ose t
o
t
h
e
pr
escri
b
e
d
out
pu
t
vol
t
a
ge
b
u
t
s
o
m
e
what
osci
l
l
at
e.
Th
en
, k
i
will b
e
red
u
c
ed
to
so
m
e
v
a
lu
e with
ou
t o
s
cillati
o
n
.
Step
3
:
from th
is ti
me o
n
w
ard
,
th
e
d
i
fferen
tial
gain
kd is tune
d from
zero to
the value
which accelerates
t
h
e dy
nam
i
c res
p
onse
but somewhat
oscillate. The
n
,
k
d
will b
e
reduced
to so
m
e
v
a
lu
e withou
t oscillatio
n
.
7.
E
X
PERI
MEN
T
AL RES
U
L
T
S
Fi
gu
re
6 (a
) a
nd
(
b
) s
h
ow
s t
h
e
gat
e
d
r
i
v
i
n
g si
g
n
al
s S
1
a
nd
S2
f
o
r M
O
SFET
1
a
nd M
O
SFE
T2
. T
h
e
PW
M g
a
te sign
al g
e
n
e
rated
fro
m
PIPW
M co
n
t
ro
lling
tech
n
i
q
u
e
it’s
redu
ced
t
h
e system o
u
t
pu
t erro
r and
gives accurate
response a
n
d better efficiency. Both gat
e
signals are opposite to each othe
r as shown in
Fi
gu
re 6.
(a)
(b
)
Fig
u
r
e
6
.
PWM
g
a
te
sign
als (
a
)
PW
M
1(
b)
PW
M 2
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
D
e
sign
an
d Con
t
ro
l f
o
r th
e Bu
ck-
Boo
s
t Converter Com
b
i
n
in
g 1-
Plus-D
C
o
n
v
erter and
…
(Jeevan N
a
ik)
31
3
The wa
ve
fr
om
s of t
h
e sy
st
e
m
i
nput
v
o
l
t
a
g
e
sho
w
n i
n
Fi
g
u
re
7. I
n
t
h
i
s
f
i
gu
re 0 t
o
0.
4 sec t
h
e i
n
p
u
t
vol
t
a
ge i
s
1
6
V
o
l
t
and 0
.
4 t
o
0.
6sec v
o
l
t
a
ge
i
s
10V
ol
t
.
Fi
gu
re 8 sh
o
w
s t
h
e sy
st
em
co
nst
a
nt
o
u
t
p
ut
vol
t
a
g
e
12
V
o
l
t
du
ri
n
g
0 t
o
0
.
4 sec i
n
put
v
o
l
t
a
ge i
s
16
v
o
l
t
t
h
e sy
st
em
i
s
st
art
bucki
n
g
an
d d
u
ri
n
g
0.
4 t
o
0.
8 se
c t
h
e
sy
st
em
st
art
s
b
oost
i
ng
an
d s
h
ow
n i
n
a
b
o
v
e
f
i
gu
re.
Fi
gu
re
7.
Sy
st
em
Input
v
o
l
t
a
g
e
o
f
10
V a
n
d
1
6
V
Fi
gu
re 8.
Sy
st
em
respon
se of out
put
v
o
l
t
a
ge of
1
2
V
o
l
t
The
wa
vef
o
rm
s i
n
Fi
g
u
re
9
s
h
o
w
s t
h
e sy
st
e
m
rat
e
d const
a
nt
o
u
t
p
ut
c
u
r
r
e
n
t
are
m
easured
un
de
r t
h
e
in
pu
t vo
ltag
e
10
vo
lts to
16
v
o
lts it g
i
v
e
s co
nstan
t
3Am
p
s. Fig
u
re
1
0
shows th
e system
o
u
t
p
u
t
p
o
wer in
watt
s
i
t
gi
ves
3
6
wat
t
s. It
ca
n
be s
h
ows
t
h
at
t
h
e
pr
op
ose
d
b
u
ck
–
b
oost
co
n
v
ert
e
r
can
ope
rat
e
st
a
b
l
y
i
n
C
C
M
f
o
r a
ny
load unde
r
t
h
e closed-loop
control.
0
0.
1
0.
2
0.
3
0.
4
0.
5
0.
6
0.
7
0.
8
0
5
10
15
Ti
m
e
i
n
Se
c
Vol
t
age i
n
v
o
l
t
In
put
V
o
l
t
a
g
e
0
0.
1
0.
2
0.
3
0.
4
0.
5
0.
6
0.
7
0.
8
0
2
4
6
8
10
12
14
Ti
m
e
i
n
Se
c
Vol
t
age i
n
v
o
l
t
O
u
t
put
V
o
l
t
a
g
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
305
–
3
17
31
4
Fi
gu
re 9.
Sy
st
em
respon
se of out
put
c
u
rre
nt
3Am
p
s
Fi
gu
re 1
0
. Sy
st
em
out
p
u
t
po
w
e
r
The
wave
fr
om
Fi
gu
re
11
(a)
and
(
b
) s
h
ows
t
h
e sy
st
em
i
nduct
o
r c
u
rre
nt
,
du
ri
n
g
0 t
o
0
.
4 sec t
h
e
syste
m
start bucking c
o
ndition
because
of t
h
e input voltage is
16volt a
n
d the tim
e period
of
duty cycle D is
l
e
ss t
h
en t
h
e 1
-
D s
h
o
w
n i
n
F
i
gu
re 1
2
(a) a
n
d d
u
ri
ng
0.
4 t
o
0.8 sec t
h
e sy
st
em
st
art
boo
st
i
ng beca
use
of t
h
e
in
pu
t vo
ltag
e
is less th
e system o
u
t
pu
t vo
ltag
e
i.e.
1
2vo
lts
at that time period the
duty c
y
cle D is greater tha
n
th
e 1-D
sh
own
in
Figur
e
1
2
(b)
.
0
0.
1
0.
2
0.
3
0.
4
0.
5
0.
6
0.
7
0.
8
0
0.
5
1
1.
5
2
2.
5
3
3.
5
Ti
m
e
i
n
Se
c
Cur
r
ent
i
n
Am
ps
Out
put
Cur
r
e
nt
0
0.
1
0.
2
0.
3
0.
4
0.
5
0.
6
0.
7
0.
8
0
10
20
30
40
Ti
m
e
i
n
Se
c
Power
i
n
wat
t
s
I
nput
Cur
r
e
nt
Evaluation Warning : The document was created with Spire.PDF for Python.