Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l.
7, N
o
. 1
,
Mar
c
h
20
16
,
pp
. 94
~106
I
S
SN
: 208
8-8
6
9
4
94
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
VHDL I
m
plementation of Capaci
tor Volt
age B
a
l
a
ncing Control
with Level-Shifted PWM for Mo
dular Multilevel Converter
Chue
n Ling T
o
h,
Lars
Einar Norum
Department o
f
Electrical Power
Engi
neering, No
rwegian Univ
ers
i
ty
of
Scien
c
e an
d Technolog
y
(
N
TNU), Norway
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Sep 29, 2015
Rev
i
sed
Jan
6, 2
016
Accepte
d
Ja
n 22, 2016
Power electronics conver
t
ers ar
e a ke
y
component in
high vo
ltag
e
dir
e
ct
current (HVDC) power transmission.
The modular multilev
e
l converter
(MMC) is one of the
lat
e
st topo
l
ogies to b
e
prop
osed for this
app
lic
ation
.
An
MMC generates
m
u
ltilev
e
l out
put volt
a
ge wa
veform
s which reduces t
h
e
harmonics contents significantly
.
This paper presents
a VHDL
implementation
of the capacitor
voltage
b
a
lancing control and level-shif
ted
pulse width mo
dulation (
L
SPWM) for MM
C. The objec
tive is
t
o
m
i
nim
i
ze
the processing time with minimum gate
counts
.
The design d
e
tails are fully
described and
v
a
lid
ated e
xperimentally
. An ex
peri
ment is con
ducted on
a
s
m
all s
cale M
M
C protot
ype wi
t
h
two units
of p
o
wer cel
ls
on ea
ch arm
.
Th
e
te
st re
sults
a
r
e enc
l
ose
d
a
nd discusse
d.
Keyword:
Cap
acito
r vo
ltag
e
b
a
lan
c
i
n
g
cont
rol
Lev
e
l-sh
ifted
PWM
Mo
du
lar m
u
ltil
ev
el conv
erter
Vh
dl
Xilin
x
7-series
FPGA
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
C
hue
n Li
ng
T
o
h,
Depa
rt
m
e
nt
of
El
ect
ri
cal
Po
w
e
r E
ngi
neeri
n
g
,
Norweg
ian
Univ
ersity of Scie
n
c
e
an
d T
e
ch
no
log
y
(N
TN
U),
Tro
n
dhei
m
, N
o
r
w
ay
Em
a
il: ch
u
e
n
lin
g@u
n
iten.edu.my, to
h
c
h
u
e
n
l
in
g@yaho
o.com
1.
INTRODUCTION
Hig
h
v
o
ltage direct
cu
rre
nt (H
VDC
) has been rec
o
gniz
ed as a c
o
st
effective s
o
lut
i
on
for long
d
i
stan
ce po
w
e
r
tr
an
sm
issio
n
[1
],
[2
].
Fi
gu
re 1
(a) s
h
ows a si
ngl
e l
i
n
e ci
rcui
t
di
a
g
r
a
m
of an
HV
D
C
sy
st
em
[3]
.
The t
e
rm
i
n
al
s
of a
n
H
V
D
C
transm
ission s
y
ste
m
are formed by
powe
r electronics c
o
nve
rters
.
T
h
e
ac powe
r is
fi
rst converte
d i
n
to
dc
po
we
r at
t
h
e
se
ndi
ng
en
d
usi
n
g a
n
ac-
dc
p
o
w
e
r c
o
n
v
ert
e
r. T
h
e
dc
po
wer
i
s
t
h
en c
o
nve
rt
ed
bac
k
i
n
t
o
ac
p
o
w
e
r
at the recei
ving e
n
d wit
h
the
cont
rol
of a
dc
-ac
power
c
o
nverter. T
h
e m
o
st recent
powe
r
c
o
nverte
r topologies
u
s
ed
in tod
a
y’s HVDC
syste
m
s are m
o
du
lar
m
u
l
tilev
e
l co
nv
erters (MMCs)
[4
],
[5
], [6
].
M
M
C
s are const
r
uct
e
d
usi
n
g a seri
es o
f
i
d
ent
i
cal
p
o
we
r
el
ect
roni
cs b
u
i
l
d
i
ng
bl
oc
ks (
P
EB
B
s
). It
s
basi
c st
r
u
ct
u
r
e
and
t
h
e
f
unct
i
o
nal
bl
ock
di
a
g
r
a
m
of a
PEB
B
are s
h
o
w
n i
n
Fi
gu
re 1
(b
) a
nd
(c)
.
PEB
B
i
s
a ful
l
y
i
n
t
e
grat
e
d
de
vi
ce fo
rm
ed by
di
f
f
ere
n
t
gr
o
u
p
s
of
har
d
w
a
re
com
pone
nt
s, i
n
cl
u
d
i
n
g
po
w
e
r cel
l
,
gat
e
dri
v
er,
heat
si
nk
an
d
sens
o
r
s [
7
]
,
[
8
]
.
Ea
ch P
E
B
B
act
s
as a
cont
rol
l
a
bl
e
v
o
l
t
a
ge so
urce
. C
o
m
m
ut
at
i
on o
f
t
h
ese P
E
B
B
s
enabl
e
s
t
h
e s
u
m
m
a
t
i
on o
f
t
h
e
capaci
t
o
r
vol
t
a
ges t
o
reach
high
voltage levels at t
h
e
out
put term
inal
. MMCs produce low
ha
rm
onic conte
n
t
out
put voltages by
in
creasing
th
e
n
u
m
b
e
r of PEBBs [9
], [10
]
. Th
is min
i
m
i
ze
s th
e ac h
a
rm
o
n
ics filter size, wh
ich
con
s
equ
e
n
tly
r
e
du
ces t
h
e
f
o
o
t
pr
in
t
o
f
HVD
C statio
ns.
An
MMC w
i
t
h
m
o
r
e
th
an
t
w
o hu
ndr
ed
s un
its of
PEBB p
e
r ar
m
h
a
s
been comm
ercialized [11].
In
o
r
de
r t
o
co
n
t
rol
a l
a
r
g
e
n
u
m
ber of
PEB
B
s
, a
hi
g
h
s
p
ee
d
di
gi
t
a
l
co
nt
r
o
l
l
er i
s
re
qui
red
t
o
pe
rf
o
r
m
the com
p
lex cont
rol and m
odulation algori
thm
s
nece
ssary, exam
ples of which incl
ude a Digital Signal
Pro
cesso
r (
D
S
P
), FP
G
A
, o
r
Sy
st
em
on C
h
i
p
(S
oC
) [
12]
-
[
15]
. D
SPs are
t
y
pi
cal
l
y
used i
n
po
wer el
ect
ro
ni
cs
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
94
–
1
06
95
con
v
e
r
t
e
r c
o
nt
r
o
l
;
h
o
w
e
ve
r t
h
ey
ha
ve a l
i
m
i
t
ed
num
ber
o
f
P
W
M
o
u
t
p
ut
p
i
ns
whi
c
h i
s
i
n
suf
f
i
c
i
e
nt
t
o
c
o
nt
r
o
l
an
MMC with m
o
re th
an
h
u
n
d
red
s
un
its
of PEBBs
p
e
r phase. The
r
efore,
an FPGA has
bee
n
c
o
uple
d
wit
h
D
SP
bo
ard
s
,
main
ly to
d
i
str
i
b
u
t
e th
ese contr
o
l sign
als [16]. I
n
[
1
7
]
– [19
]
, an
FPG
A
i
s
also
u
s
ed to
sh
or
ten
t
h
e p
r
ocessi
n
g
t
i
m
e
by
execut
i
ng
si
m
p
l
e
l
ogi
c f
unct
i
o
ns
suc
h
as
pe
rf
orm
i
ng ca
rri
er
-ba
s
ed
P
W
M
.
Thi
s
pa
per
p
r
e
s
ent
s
V
H
D
L
i
m
pl
em
ent
a
t
i
on of M
M
C
co
nt
rol
.
C
a
paci
t
o
r
vol
t
a
ge
bal
a
nc
i
ng c
ont
r
o
l
and l
e
vel
-
shi
f
t
e
d p
u
l
s
e wi
dt
h m
odul
at
i
on
(LSP
WM
) a
r
e
chose
n
f
o
r i
m
pl
em
ent
a
t
i
on,
m
a
i
n
l
y
due t
o
t
h
e
si
m
p
licit
y o
f
th
e calcu
latio
ns in
vo
lv
ed
with th
ese sch
e
m
e
s. Th
e
o
b
j
ectiv
e is to
m
i
n
i
mize
th
e p
r
o
cessi
n
g
ti
m
e
whe
n
the MMC e
m
ploys a
large num
b
er of PEBBs. The
pr
o
pose
d
desi
g
n
i
s
capabl
e
t
o
sort
out
a h
u
n
d
r
e
d
u
n
its
o
f
PEBB
cap
acito
r vo
ltag
e
m
easu
r
em
e
n
ts in
less th
an ten
m
i
cro
s
econ
d
’s tim
e. In
ad
d
ition
,
t
h
e
d
e
sig
n
is
opt
i
m
i
zed t
o
save som
e
gat
e
cou
n
t
s
, f
o
r e
x
a
m
pl
e onl
y
a singl
e car
ri
er wa
ve i
s
im
pl
em
ent
e
d f
o
r LS
P
W
M
.
B
y
red
u
ci
n
g
t
h
e
u
s
e of
res
o
u
r
ces
and
p
r
oce
ssi
n
g
t
i
m
e
, som
e
ot
her c
ont
rol
al
go
ri
t
h
m
s
can b
e
con
f
i
g
ur
ed t
o
get
h
e
r
in the sam
e
FPGA. T
h
e proposed
design
is
m
odular. It ca
n be duplicated
to
confi
g
ure a t
h
ree
phase syste
m
by
introducing a balance three-pha
se
m
odulat
ing wa
ves.
An overview
of the
MMC will
be give
n in Se
ction 2.
Th
eo
ry of th
e
co
n
t
ro
l and
mo
du
latio
n
techn
i
qu
e to
b
e
imp
l
em
en
ted
in
t
h
is p
a
p
e
r
will
b
e
briefly ex
p
l
ain
e
d.
Sectio
n
3
will
d
i
scu
ss th
e op
ti
m
u
m
d
e
sig
n
d
e
tails. Th
e co
n
t
ro
ller is th
en
v
a
lid
ated
t
h
rou
g
h
a s
m
al
l scale
MMC in
Sectio
n
4
.
Xilinx
7
-
series FPGA will b
e
us
ed
fo
r im
p
l
e
m
en
tin
g
t
h
e prop
o
s
ed
co
n
t
ro
ll
er. All
ex
p
e
rim
e
n
t
al resu
lts will b
e
presen
ted
with
fu
ll d
i
scu
ssion
.
(a)
ac t
e
r
m
i
nal
Lo
w
e
r
A
r
m
A
B
C
+
_
Up
pe
r
A
r
m
i
ac
_
a
i
l_a
i
u_
a
L
L
L
L
L
L
PE
B
B
U
n
O
2
dc
V
2
dc
V
(b
)
P
N
Q
M
+
+
_
_
PE
B
B
U
1
PE
B
B
U
n
PE
B
B
U
1
PE
B
B
U
n
PE
B
B
U
1
PE
B
B
L
n
PE
B
B
L
1
PE
B
B
L
n
PE
B
B
L
1
PE
B
B
L
n
PE
B
B
L
1
P
E
BB
C
S1
S2
Po
w
e
r
C
e
l
l
Ga
t
e
D
r
i
v
e
r
Ci
r
c
ui
t
I/
O
FP
G
A
I/
O
AD
C
ana
l
og i
nput
(c
)
He
a
t
S
i
n
k
V
o
l
t
a
ge
s
e
ns
or
boa
rd
i
arm
> 0
Fi
gu
re
1.
(a
) Si
ngl
e l
i
n
e
ci
rc
ui
t
di
ag
ram
of
hi
gh
v
o
l
t
a
ge
di
re
ct
cur
r
ent
(
H
V
D
C
)
Sy
st
em
(b) M
M
C
wi
t
h
n
u
n
its
of
p
o
w
e
r el
ect
r
oni
cs
b
u
i
l
d
i
n
g
bl
oc
ks
(PEB
B
s
)
per a
r
m
;
(c) P
E
B
B
fu
nct
i
o
na
l
bl
oc
k
di
ag
ra
m
2.
MO
DUL
AR
MULTILEVE
L
CO
NVE
RT
ER (
M
M
C
)
The
basi
c st
ru
ct
ure a
n
d
pri
n
ci
pal
o
f
M
M
C
i
s
f
u
l
l
y
desc
ri
bed
i
n
[
10]
,
[
1
1]
, a
n
d
[
2
0]
.
The
ge
neral
co
n
t
ro
l and
mo
du
latio
n
sch
e
mes u
s
ed
in
MMC are su
mmarized
in
[21
]
. Th
is sectio
n
will b
r
iefly p
r
esen
t th
e
conce
p
t
of
M
M
C
s wi
t
h
t
h
e s
e
l
ect
ed co
nt
r
o
l
an
d m
odul
at
i
o
n sc
hem
e
s.
2.
1. Pri
n
ci
pl
e
An MMC alwa
ys contains an
equi
valent
num
b
er of PEBBs on upper
a
nd lowe
r arm
s
for each phase
.
Each PEBB c
onsists
of a
n
e
n
ergy storage
ele
m
ent, i.
e. th
e cap
acit
o
r
wh
ich
is co
nn
ected
in
p
a
rallel to
th
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
VHDL Implementation of
Cpacitor
Vo
ltage
Balancing C
o
ntrol with L
evel
-Shifted … (Chuen Ling
Toh)
96
po
we
r sem
i
cond
uct
o
rs (
S1
and
S2
). I
n
gen
e
ral
,
an M
M
C
cont
ai
n
s
n
units of PEBB pe
r arm
.
Each ca
pacit
o
r
v
o
ltag
e
m
u
st be m
a
in
tain
ed
as fo
llo
ws:
n
V
V
dc
C
(
1
)
Whe
n
S1
is trig
g
e
red on
, the PEBB
will co
n
t
ribu
te its
fu
ll cap
acito
r
v
o
ltag
e
,
V
c
, t
o
th
e MMC.
In
ver
s
ely
,
whe
n
S2
is switched
on
, th
is PEBB is b
y
p
a
ssed
,
con
t
ri
b
u
ting ap
prox
im
ate
l
y 0
V
to
th
e po
wer
circuit. The
r
efore
,
the en
ergy transfer
between
dc and ac ter
m
inal
s i
s
easily co
n
t
ro
lled
b
y
in
sertin
g
or
by
passi
ng
t
h
e PEB
B
s
.
Eq
uat
i
on (
2
) f
o
rm
ul
at
es t
h
e
pha
se-a o
u
t
p
ut
vol
t
a
ge by
ne
gl
ect
i
ng t
h
e v
o
l
t
a
ge d
r
o
p
ac
ross t
h
e a
r
m
in
du
ctors
referring
to MMC circu
it in
Figu
re 1 (b
).
2
)
(
2
)
(
dc
PQ
dc
NM
AO
V
t
v
V
t
v
v
(
2
)
Up
pe
r arm
current
i
u_a
is d
e
fi
n
e
d
as
po
sitiv
e wh
en
it flows
fro
m
th
e p
o
s
itiv
e d
c
term
in
al to
ward
s t
h
e
ac term
in
al. A po
sitiv
e lower arm
cu
rren
t
i
l_a
will flo
w
fro
m
th
e ac termin
al to
th
e
neg
a
tiv
e
d
c
termin
al;
hence
,
the
ac t
e
rm
inal phase
current,
i
ac_a
i
s
deri
ved
as
)
(
)
(
_
_
_
t
i
t
i
i
a
l
a
u
a
ac
(
3
)
Eq
uat
i
on
(
2
) a
nd
(
3
) a
r
e al
so
appl
i
c
a
b
l
e
t
o
ot
he
r p
h
ases
.
The m
ean val
u
e o
f
i
u_a
and
i
l_a
form
the
ci
rcul
at
i
n
g
cu
r
r
ent
,
w
h
i
c
h i
s
l
i
m
i
t
e
d by
t
h
e
a
r
m
i
nduct
o
rs.
A f
u
l
l
de
ri
vat
i
on
o
f
t
h
e
ci
rc
u
l
at
i
ng cu
rre
nt
and
i
t
s
harm
oni
cs e
x
p
r
essi
o
n
a
r
e
gi
v
e
n i
n
[
2
2]
.
2.
2.
C
a
p
a
ci
t
o
r
V
o
l
t
age
B
a
l
a
nci
n
g
C
o
nt
rol
The
m
a
in cont
rol objecti
v
e in this pape
r is to
regulate ba
lance capacitor
voltages inside each arm
[23
]
. Th
e cap
acito
r of each
PEBB will b
e
ord
e
red
fo
r ch
ar
g
i
ng
or d
i
sch
a
rg
ing
b
a
sed
on
its
cap
acito
r vo
ltag
e
lev
e
l and
arm
cu
rren
t
d
i
recti
o
n.
A sim
p
le v
o
ltag
e
-b
alan
ci
n
g
algo
rith
m
,
p
r
op
o
s
ed
i
n
[24
]
, will b
e
im
p
l
e
m
en
ted
in
th
is p
a
p
e
r. Th
is m
e
th
o
d
m
e
asu
r
es th
e arm
cu
rren
t
and
PEBB’s cap
acito
r vo
ltag
e
s p
e
riod
ically. Th
e PEBBs
o
n
each
arm
will b
e
so
rted
based
o
n
its
V
c
valu
e in
ascend
in
g
ord
e
r.
When
th
e sortin
g
resu
lt tu
rn
s
v
a
lid
, the
arm
curre
nt di
rection
will be
use
d
to
distri
bute the
duty cycle determ
in
ed from
the m
odulation schem
e
. F
o
r
in
stan
ce, if th
e sam
p
led
arm
cu
rren
t is fo
und
to b
e
po
sitive, th
e
PEBB
with
lo
west
V
c
l
e
vel
m
u
st
be a
ssi
gne
d
the longest
dut
y cycle to c
h
arge
up that
pa
rticular ca
paci
t
o
r.
In
ve
rsel
y
,
P
E
B
B
s
w
h
i
c
h
r
a
nk
at
t
h
e
bot
t
o
m
of
th
e so
rting
list sh
ou
l
d
ex
ecu
t
e th
e sh
ortest du
ty cycle. Th
is co
n
t
ro
l m
e
th
od
is si
m
p
le b
u
t
th
e p
r
o
cessing ti
me
for sorting
algo
rith
m
in
creases d
r
astically
as hu
nd
red
s
of PEBBs are
e
m
ployed in e
ach arm
.
This
pape
r
p
r
op
o
s
es a l
o
gic d
e
sig
n
wh
ich
will on
ly o
ccu
p
y
n
cloc
k cycles to sort out
n
num
b
er of PEBBs in each arm
.
By d
r
iv
ing
th
e
so
rting
algorith
m
lo
g
i
cs u
s
ing
a h
i
g
h
frequ
en
cy clo
c
k
(1
00MHz), t
h
e requ
ired
ti
m
e
to
so
rt ou
t
a hu
ndr
ed un
its of
PEBB
is less th
an
1
0
µs.
2.
3. Le
vel-S
h
ifted P
u
lse Wid
t
h
Modul
ation
(LSP
WM)
LSPW
M
is easily i
m
p
l
e
m
en
ted
u
s
ing
FPGA. Each
ph
ase of th
e MMC
r
e
qu
ir
es a
p
a
ir
o
f
1
8
0
ou
t
o
f
pha
se m
odul
at
i
ng
wav
e
s. T
h
ese si
g
n
al
s a
r
e nam
e
d as
t
h
e u
p
p
er m
odul
at
i
n
g
wave
,
v
mod_up
, and
l
o
w
e
r
m
odul
at
i
ng wa
ve,
v
mod_low
. Ea
ch
of t
h
ese m
odulating
waves
will be c
o
m
p
ared
with
n
u
n
i
t
s
of triangu
lar
carrier
wav
e
s to
d
e
termin
e
n
num
be
r of duty cycle
s
for PEBBs on each a
r
m
.
In this pape
r, the
carrier
waves
are se
t
in
p
h
a
se d
i
sp
ositio
n
.
Th
ey are id
en
ti
cal and synchronous i
n
phase [25].
The am
plitude ratio of eac
h
carrier
wav
e
is set as fo
llo
ws:
n
v
tri
1
(
4
)
Fi
gu
re
2 s
h
ow
s t
h
e a
b
ove
m
e
nt
i
one
d
co
nt
r
o
l
an
d
m
odul
at
i
on e
x
am
pl
e t
o
an M
M
C
usi
n
g
fo
ur
u
n
i
t
s
o
f
PEBBs in
on
e ph
ase.
Assume th
at th
e d
c
lin
k
vo
ltag
e
is
set at 1
0
0
V. Th
e d
a
ta sam
p
li
n
g
at ti
m
e
in
stan
t
A
are depicted in Figure
2
(a),
whic
h incl
ude
arm
curre
nts di
rection and ca
pacitor
vol
t
a
ge
m
easurem
ent
s
.
U
ppe
r
arm
’
s PEBBs
are the
n
sorted in se
qu
en
c
e
as
U1
fo
llo
w
e
d
b
y
U2
,
w
h
er
e
a
s
,
low
e
r ar
m’
s
P
E
BBs
a
r
e lis
te
d
as
L2
fol
l
o
we
d L
1
.
Fi
g
u
re
2
(
b
) p
r
ese
n
t
s
t
h
e
conce
p
t
of
LS
P
W
M
.
B
o
t
h
u
ppe
r a
n
d l
o
we
r m
odul
at
i
n
g s
i
gnal
s
m
u
st
be kept
wi
t
h
i
n
t
h
e t
w
o
carri
er
waves
t
o
ens
u
re t
h
e
M
M
C
wor
k
s i
n
l
i
n
ear m
odul
at
i
on m
ode. T
h
e gat
i
n
g
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
94
–
1
06
97
si
gnal
f
o
r swi
t
ch S
1
o
f
a PE
B
B
i
s
obt
ai
ne
d by
c
o
m
p
ari
n
g t
h
e m
odul
at
i
ng si
gn
al
s wi
t
h
a t
r
i
a
n
g
u
l
a
r
wave
.
Switch
S2 always trigg
e
r com
p
le
men
t
ally t
o
switch
S1. Fo
r in
stan
ce
b
e
tween tim
e in
st
an
t
t
1
and
t
2
,
a uni
t
o
f
up
pe
r arm
’
s PEB
B
m
u
st
be f
u
l
l
y
t
u
rne
d
on
wi
t
h
an
ot
h
e
r P
E
B
B
carri
es
o
u
t
P
W
M
m
o
d
u
l
at
i
on. C
o
n
v
er
sel
y
, a
PEBB at the lower arm
will also carry out P
W
M m
odula
tion
with anothe
r PEBB is
perm
anently switched
off.
In
su
mmary, t
h
ere are three switch
i
ng
m
o
d
e
wh
ich
will
be ap
p
lied
to
a PEBB, i.e. fu
ll
y tu
rn
-on
,
PWM o
r
perm
anently
tu
rn
-o
ff
.
As
p
o
s
itiv
e
arm
cu
rren
t
is sam
p
led
o
n
t
h
e up
p
e
r arm
at ti
me in
stan
t
A
,
PEBB U1
m
u
st fu
lly tu
rn
ed
on
f
o
r
c
h
an
gi
n
g
up
i
t
s
ca
paci
t
o
r.
P
W
M
s
w
i
t
c
hi
n
g
m
ode
wi
l
l
be ca
rri
e
d
o
u
t
by
PEB
B
U
2
.
O
n
t
h
e
ot
he
r
ha
n
d
,
PEBB L2
wh
ich
listed
at the to
p
of lower arm
so
rtin
g
li
st will b
e
p
e
rman
en
tly tu
rned
o
f
f to
m
a
in
tain
its
cap
acito
r vo
ltag
e
lev
e
l
wh
en a n
e
g
a
tiv
e arm
cu
rren
t
is sa
m
p
led
at ti
me in
stan
t
A
. PWM switch
i
ng will b
e
assi
gne
d t
o
P
E
B
B
L1.
PE
B
B
U1
a
o
53
V
i
l
_a
< 0
L
ar
m
L
ar
m
PE
B
B
U2
PE
B
B
L1
PE
B
B
L2
49
V
i
u_a
> 0
50
V
55
V
v
mo
d
_
l
o
w
v
mo
d
_
u
p
1/2
1
0
t
1
t
2
0
1
Fu
l
l
y
O
N
A
0
1
PW
M
G
a
t
e
s
i
g
n
a
l
s
fo
r Up
p
e
r
a
r
m
P
E
B
B
s
’
S
1
s
1/2
1
0
0
1
Fu
l
l
y
O
F
F
0
1
PW
M
G
a
t
e
s
i
g
n
a
l
s
fo
r
L
o
we
r
a
r
m
PE
B
B
s
’
S
1
s
Ar
m
s
Up
p
e
r
U1
U2
Lo
w
e
r
L2
L1
S
o
rt
ed
PE
B
B
Ar
m
s
cu
rr
en
t
i
u_a
>
0
F
u
lly
O
N
PW
M
i
l_a
<
0
Fu
l
l
y
O
F
F
PW
M
Sw
i
t
c
h
i
n
g
mod
e
C
a
p
a
c
ito
r
v
o
lta
g
e
b
a
la
n
c
i
n
g
c
o
ntr
o
l
a
t
ti
m
e
in
s
t
a
n
t
A:
D
a
t
a
S
a
m
p
li
ng
a
t
ti
m
e
in
s
t
a
n
t
A
:
(a)
(
b
)
Fi
gu
re
2.
A
n
e
x
am
pl
e of ca
pa
ci
t
o
r
vol
t
a
ge
b
a
l
a
nci
n
g
c
ont
r
o
l
an
d
LSP
W
M
fo
r
on
e
phas
e
o
f
M
M
C
w
h
i
c
h
em
pl
oy
s 4
PE
B
B
s
3.
MMC CONT
ROLLER
DE
SIGN
Th
e MMC contro
ller is fu
lly i
m
p
l
e
m
en
ted
in
pro
g
ramm
ab
le lo
g
i
c u
s
i
n
g
v
e
ry
h
i
gh
-sp
e
ed
in
teg
r
ated
circu
its, h
a
rd
ware d
e
scrip
tion lan
g
u
a
g
e
(VHDL). Th
is
secti
o
n
will d
i
scu
s
s th
e con
t
ro
ller
d
e
sign
fo
r
on
e
p
h
a
se
of
t
h
e M
M
C
.
Thi
s
desi
gn
(t
o
p
-l
e
v
el
w
r
ap
per
)
ca
n t
h
en be
easily duplicated for three
-
pha
se
MMC
im
pl
em
ent
a
t
i
o
n. T
h
e M
M
C
s
w
i
t
c
hi
n
g
f
r
eq
u
e
ncy
i
s
defi
ne
d
as 2
k
H
z
with
th
e in
pu
t
d
a
ta sa
m
p
lin
g
rate set as 4
kHz
.
A
fu
nct
i
o
nal
bl
oc
k
di
ag
ram
o
f
t
h
e
M
M
C
co
nt
r
o
l
l
e
r i
s
prese
n
t
e
d
i
n
F
i
gu
re
3.
Thi
s
cont
rol
l
e
r
i
s
di
vi
de
d i
n
t
o
fi
ve m
odul
es. T
h
e C
l
ock
s
m
o
dul
e i
s
esse
nt
i
a
l
t
o
pr
od
uce
app
r
op
ri
at
e cl
ock
fre
q
u
enci
e
s
and
gene
rat
e
co
nt
r
o
l
si
gnal
s
f
o
r
d
i
ffere
nt
fu
nct
i
o
nal
bl
oc
ks.
T
h
e si
ne wave ge
nerat
o
r m
odul
e
i
s
used t
o
ge
n
e
rat
e
a
5
0
H
z
sin
e
w
a
v
e
fo
r t
h
e Mod
u
l
ation
Module. Th
e Modu
latio
n
Mod
u
l
e
w
ill p
e
rfo
r
m
LSPW
M
,
wh
ilst th
e
capaci
t
o
r
v
o
l
t
a
ge
bal
a
nci
n
g
c
ont
rol
i
s
ca
rri
e
d
out
by
t
h
e
C
ont
rol
M
o
d
u
l
e
.
The
res
u
l
t
s
p
r
od
uce
d
fr
om
these
two
b
l
o
c
k
s
wil
l
b
e
sen
t
to th
e
Switch
i
ng
C
o
mman
d
s
Dist
ri
b
u
tion
M
o
d
u
l
e. A series
of mu
ltip
lex
e
rs are
u
s
ed
to
d
i
stribu
te th
e sp
ecified
d
u
t
y cycles to
th
e co
rrespon
d
i
n
g
PEBBs. Each
log
i
c b
l
o
c
k
will b
e
fu
rt
h
e
r
d
e
scribed
in
th
e fo
llowing
su
b-section
s
.
3.
1. Cl
oc
ks M
o
dul
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
VHDL Implementation of
Cpacitor
Vo
ltage
Balancing C
o
ntrol with L
evel
-Shifted … (Chuen Ling
Toh)
98
Th
e MMC co
ntro
ller
will b
e
tested
u
s
i
n
g Xi
lin
x
ZC
7
0
2
evalu
a
tio
n
bo
ard
in
th
is
p
a
p
e
r.
Th
e system
clo
c
k
so
urce on
th
e ev
al
u
a
tion
bo
ard
is prov
id
ed
b
y
a 200MH
z
o
s
cillato
r [26
]
. In
o
r
d
e
r to
p
r
ov
id
e
d
i
fferent
clock freque
ncies to other
logic
m
odules, Xilinx Logic
C
ORE IP clocki
ng wizard is im
plem
ented as a
f
r
e
q
u
e
n
c
y syn
t
h
e
sizer
[
2
7
]
, [2
8
]
. Two
ou
tpu
t
clo
c
k
f
r
e
quen
c
ies ar
e
g
e
ner
a
ted
,
i.e. 150 MH
z and
2.5 MH
z.
Sin
ce th
ey ar
e syn
t
h
e
sized
f
r
o
m
a
sa
m
e
r
o
o
t
clo
c
k
u
s
i
n
g a u
n
it o
f
clo
c
k
i
ng
w
i
zard
,
th
ey ar
e r
ecognized
as
syn
c
hr
ono
us cl
o
c
ks. Th
e clo
c
k
i
ng
w
i
zard
ensu
r
e
s th
e clo
c
k ph
ase
r
e
latio
nsh
i
p is m
a
in
tai
n
ed thr
oug
hout th
e
chip. T
h
ese clocks are phase
synchronous a
nd s
k
ew m
a
tched,
i
.
e. aft
e
r
60
ri
si
ng ed
ge o
f
fast
cl
ock t
h
e
r
e wi
l
l
al
way
s
be o
v
e
r
l
a
p of
ri
si
n
g
e
dge
fo
r
bot
h fa
st
and sl
ow cl
o
c
ks. T
h
e
15
0
M
H
z cl
ock i
s
use
d
t
o
d
r
i
v
e
m
o
st
of
t
h
e l
ogi
c bl
oc
ks i
n
t
h
e c
ont
rol
l
e
r, s
u
c
h
as
t
o
pr
o
duce a
2 k
H
z t
r
i
a
n
g
u
l
a
r car
ri
er w
a
ve, a
nd t
o
dr
i
v
e t
h
e
cap
acito
r vo
ltag
e
so
rti
n
g algorith
m
.
Altern
at
iv
ely, th
e
2
.
5
M
H
z cl
oc
k i
s
use
d
as
t
h
e
ba
se cl
oc
k t
o
pr
o
duce
a
50
Hz
m
odul
at
i
ng
wa
ve.
So
m
e
co
n
t
ro
l p
u
l
ses
will b
e
g
e
n
e
rated
p
e
ri
o
d
i
cally to
en
ab
le syn
c
h
r
o
nou
s inp
u
t
d
a
ta sa
m
p
lin
g
and
in
itializin
g
th
e
so
rting
al
g
o
rithm
in
th
is m
o
d
u
le. All of
t
h
ese sig
n
a
ls
are g
e
nerated
i
n
1
5
0
MHz
clo
c
k
domain
.
U
_
P
E
B
B
*_g
a
t
e
S
w
it
c
h
in
g
Co
m
m
a
n
d
s
D
i
st
ri
but
i
o
n
Mo
d
u
l
e
cl
k
re
s
e
t
c
l
k
_
15
0M
c
l
k
_2M
5
c
l
k
_2k
Cl
o
c
k
s
Mo
d
u
l
e
cl
k
re
se
t
Mo
d
u
l
a
t
i
o
n
M
o
d
u
l
e
(L
S
P
W
M
)
cl
k
U
_
P
E
B
B
*_V
c
U_
I
_
a
r
m
U_P
E
B
B
*_sta
tu
s
S
i
n
e
w
a
ve
ge
n
e
r
a
to
r
PE
BB
_
t
r
i
gg
e
r
C
o
nt
r
o
l M
o
du
le
(
C
ap
a
c
i
t
or
V
o
l
t
a
g
e
Ba
l
a
n
c
i
n
g
)
Lo
w
e
r
a
r
m
P
E
BB
s
i
n
put
da
t
a
(
V
c
,
I
ar
m
,
op
e
r
a
t
i
ng
st
a
t
us
b
i
t)
MMC
Co
n
t
ro
l
l
er
15
cl
k
_
1
5
0M
Up
p
e
r
a
r
m
P
E
BB
s
in
p
u
t d
a
ta
(
V
c
,
I
ar
m
,
op
erat
i
n
g
st
a
t
us
b
i
t)
Low
e
r
a
r
m
P
E
B
B
s
S
w
it
ch
ing
c
o
m
m
a
n
d
.
U
p
p
e
r
ar
m
P
E
B
B
s
S
w
itc
h
in
g
co
m
m
an
d
s
.
L_P
E
B
B
*_V
c
L_I_a
r
m
L_P
E
B
B
*_sta
tu
s
cl
k
sa
m
p
l
i
n
g
&
s
t
a
r
t
pu
l
s
e
s
sa
m
p
l
i
ng
&
st
a
r
t
pu
l
s
e
s
4
s
a
m
p
li
n
g
&
s
t
ar
t
p
u
ls
e
s
3
L_P
E
B
B
*_g
a
t
e
U
_
s
w
_c
m
d
_B
a
n
d
i
L_s
w
_c
m
d
_B
a
n
d
i
U
_
P
E
B
B
*_m
u
x
s
e
l
L_P
E
B
B
*_m
u
x
s
e
l
U
_
P
E
B
B
*_m
u
x
s
e
l
L_P
E
B
B
*_m
u
x
s
e
l
PE
BB
_
t
r
i
g
g
e
r
s
a
m
p
li
n
g
&
s
t
ar
t
p
u
ls
e
s
cl
k
_
15
0M
c
l
k
_2M
5
c
l
k
_2k
c
l
k
_
15
0M
c
l
k
_2M
5
c
l
k
_2k
cl
k
_
15
0
M
c
l
k
_2M
5
c
l
k
_2k
c
l
k
_2M
5
sin
e
_
p
h
a
se
_
a
si
n
e
_
p
h
a
se
_
a
U
_
s
w
_c
m
d
_P
W
M
L_s
w
_c
m
d
_P
W
M
U_s
w
_c
m
d
_B
a
n
d
i
L
_
s
w
_c
m
d
_B
a
n
d
i
U
_
s
w
_c
m
d
_P
W
M
L_s
w
_c
m
d
_
P
W
M
U
_
s
w
_c
m
d
_B
a
n
d
i
L_s
w
_c
m
d
_B
a
n
d
i
Fi
gu
re
3.
F
unct
i
onal
bl
oc
k
di
a
g
ram
of t
h
e M
M
C
cont
rol
(t
o
p
l
e
vel
)
3.
2.
Sine W
ave Gener
a
tor
A si
ne wa
ve
si
gnal
can
be pr
o
duce
d
usi
n
g di
f
f
ere
n
t
m
e
t
h
o
d
s, s
u
ch as
di
rect
l
o
o
k
-
u
p
t
a
bl
e, l
i
n
ear
i
n
t
e
rp
ol
at
i
o
n
,
and r
ecu
rsi
v
e
m
e
t
hods [
2
9]
. Di
rect
l
o
o
k
-
u
p
t
a
bl
e i
s
t
h
e
m
o
st
com
m
onl
y used t
ech
ni
q
u
e
. It
i
s
si
m
p
le co
m
p
ared
to o
t
h
e
r m
e
th
od
s
wh
ich
i
n
vo
lv
e co
m
p
lex
math
e
m
atica
l
fu
n
c
tion
co
m
p
utatio
n
.
Th
e accu
r
acy
o
f
th
e
d
i
rect
loo
k
-u
p tab
l
e m
e
th
od
is
propo
rt
io
n
a
l t
o
th
e table len
g
t
h
.
In
creasin
g
th
e tab
l
e
len
g
t
h
will p
r
od
u
c
e
hi
g
h
res
o
l
u
t
i
o
n
si
ne wa
ve w
h
i
c
h at
t
h
e sam
e
t
i
m
e
reduces
qua
nt
i
zat
i
on e
r
r
o
r
.
It
has
bee
n
est
i
m
at
ed i
n
[3
0]
t
h
at
, a
51
2
-
ent
r
i
e
s l
o
ok
-
u
p
-
t
a
bl
e (t
he m
i
nim
u
m
l
e
ngt
h)
w
o
ul
d a
v
oi
d s
u
b-
harm
oni
c
di
st
o
r
t
i
o
n
i
n
t
h
e g
e
nerat
e
d
si
ne wa
ve.
Usi
ng a
go
o
d
q
u
al
i
t
y
si
ne wave a
s
a refer
e
nce si
gnal
t
o
c
o
nt
rol
a po
wer el
ect
r
oni
cs c
o
n
v
e
r
t
e
r m
a
y
red
u
ce t
o
t
a
l
ha
rm
oni
cs di
st
o
r
t
i
on i
n
out
put
v
o
l
t
a
ge a
n
d
c
u
r
r
e
nt
wa
ve
fo
rm
s.
In
t
h
i
s
pa
per,
we ai
m
t
o
ge
n
e
rat
e
hi
gh
res
o
l
u
t
i
o
n si
ne
w
a
ve
wi
t
h
m
i
ni
m
u
m
desi
gn e
f
f
o
rt
.
Th
us
,
Xilin
x Log
i
CORE IP DDS (direct d
i
g
ital sy
n
t
h
e
sizer)
[3
1
]
is im
p
l
e
m
en
te
d
.
Th
e IP C
o
re will g
e
n
e
rate
a sin
e
wave
base
d
o
n
t
h
e i
n
p
u
t
p
h
a
se an
gl
e. A
1
6
-
b
i
t
co
unt
e
r
i
s
use
d
t
o
ge
ne
rat
e
t
h
e
phase
angl
e
.
Th
e re
qui
re
d
p
h
a
se in
crem
e
n
t,
,
ca
n be calculated
as follows:
clk
out
f
f
16
2
(
5
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
94
–
1
06
99
B
y
set
t
i
ng t
h
e i
n
p
u
t
cl
ock
fre
que
ncy
as 2
.
5
M
H
z (
f
clk
), the
v
a
lu
e sh
ou
ld
b
e
in
crem
en
ted
with
a v
a
lu
e
of
1.31 eve
r
y cloc
k cycle to
produce a
50
Hz
(
f
out
)
si
ne wa
ve.
An
an
alysis has b
een
carried
ou
t in
ord
e
r to
d
e
term
in
e
an
in
teg
e
r of
wh
ich
is m
u
ch
easier to
i
m
p
l
e
m
en
t in
p
r
og
ramm
ab
le
lo
g
i
c. Fi
g
u
re
4
(a) and
(b) il
lu
strates th
e analysis resu
lts fo
r th
e
first
few clock
cycles. Figure
4 (a) s
h
ows the theoretical re
sult of th
e ge
nerated phase a
ngle using 1.31 as the value
for
.
Fig
u
re
4
(b
) i
llu
strates th
at, b
y
in
crem
en
tin
g
bet
w
e
e
n an i
n
t
e
ge
r
val
u
e
of
1 a
n
d 2
,
t
h
e
pha
se
angl
e
in
creases propo
rtion
a
lly with th
e th
eore
tical v
a
lu
e.
In
ord
e
r to
fi
n
e
t
u
n
e
t
h
e con
t
ro
ller, the in
crem
en
tin
g o
f
m
u
st be reset t
o
‘1’ e
v
ery
28
th
clock. A fi
nite state m
achine (FSM
) is
d
e
sig
n
e
d
to satisfy th
e abov
e analysis.
Fig
u
re 4
(c) illu
strates th
e state tran
sitio
n
d
i
ag
ram
o
f
an
FSM. Du
ring
in
i
tializat
io
n
,
th
e
p
h
a
se ang
l
e is reset to
zero so th
at t
h
e FSM
will en
ter state S0
and
set th
e FSM cou
n
t
er (
FSMc
) t
o
ze
ro. T
h
e
FSM counter is
used t
o
keep watching for
the
28
th
clo
c
k
ev
en
t.
Wh
en
th
is ev
en
t o
c
cu
rs, th
e FSM will tran
sitio
n
fro
m
sta
t
e S2
t
o
state
S0
, reset th
e
FSMc
, a
nd
proceed to state S1; else the FSM will
rotate in the seque
nce of S1, S2, and S3
rep
eated
ly. State S1
and
S2
will o
u
t
pu
t a
val
u
e
of
1
whi
l
e
st
at
e S3 gi
ves a
valu
e o
f
2
.
In o
r
de
r
t
o
accurately produce
a
50Hz si
ne
wave
, the
phase
a
n
gle m
u
st be
reset to z
e
ro
when it re
aches
= FFEC
H
th
e
v
a
lu
e
of
wh
ich is ob
tain
ed
thro
ugh
a
sim
u
lat
i
o
n
.
Th
e
g
e
n
e
rated
sin
e
wav
e
is p
r
esen
ted
in
b
i
po
lar
15
-b
it
d
a
ta.
3.
3. Modul
ati
o
n Module (L
SPW
M
)
Thi
s
m
odul
e m
a
i
n
l
y
execut
e
s a few t
a
sks
i
n
paral
l
e
l
,
i
.
e. pr
o
duce
s
a pai
r
o
f
m
odul
at
i
ng wa
ves
,
gene
rat
e
s a t
r
i
a
ng
ul
ar
car
ri
er
wave
an
d
det
e
r
m
i
n
es t
h
e s
w
i
t
c
hi
n
g
c
o
m
m
an
ds
fo
r P
E
B
B
s
.
S1
in
c
_
c
t
r
l
=
0
S2
in
c
_
c
t
r
l
=
0
S3
in
c
_
c
t
r
l
=
1
St
a
r
t
w
i
t
h
= 0
000
H
FS
M
c
< 2
8
FS
M
c
< 2
8
FS
M
c
<
2
8
FS
M
c
= 2
8
S0
FS
M
c
= 0
FS
M
c
=
FS
M
c
+
1
FS
M
c
=
FS
M
c
+
1
FS
M
c
=
FS
M
c
+
1
(c)
Fig
u
re
4
.
(a) Ph
se ang
l
e in
cremen
t with
set as 1.31
(the
oretical val
u
e)
;
(b
)
pr
opo
sed ph
as
e i
n
crem
ent with
integer val
u
e.
(c) Phase i
n
cre
m
en
t cont
rol
Finite State Machine.
The rec
e
i
v
i
n
g
si
ne wa
ve,
v
sin
,
i
s
co
nve
rt
ed i
n
t
o
an u
p
p
e
r m
odul
at
i
ng w
a
ve,
v
mod_up
, and a l
o
we
r
m
odul
at
i
ng wa
ve,
v
mod_low
, as
fo
llows:
H
up
v
v
4000
sin
mod_
(
6
)
H
low
v
v
4000
sin
mod_
NOT
(
7
)
The converted
signals are in
uni
pola
r
m
ode. They
are then shifted according to the total num
ber of
PEB
B
s
em
pl
oy
ed i
n
eac
h ar
m
.
Thus, t
h
e l
e
vel
-
s
h
i
f
t
i
n
g
m
a
gni
t
ude
,
A
LS
,
can b
e
det
e
r
m
i
n
ed by
di
vi
di
n
g
t
h
e
am
pl
i
t
ude
of t
h
e m
odul
at
i
n
g
wave
,
A
m
, with
n
nu
m
b
er
of
PEBBs:
n
A
A
m
LS
(
8
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
VHDL Implementation of
Cpacitor
Vo
ltage
Balancing C
o
ntrol with L
evel
-Shifted … (Chuen Ling
Toh)
10
0
Th
en
a set
of l
e
v
e
l sh
ifting
ban
d
s can
b
e
cal
cu
lated
i
A
Band
LS
i
(
9
)
whe
r
e
i
=
1
,
2
,
…
,
(
n
1
)
. B
y
com
p
ari
ng t
h
e
m
odul
at
i
n
g w
a
ve wi
t
h
t
h
e l
e
vel
shi
f
t
i
n
g ba
nds
, (
n
1) n
u
m
ber
of
switch
i
ng
co
mman
d
s
will first b
e
d
e
term
in
ed
as fo
llo
ws:
0
_
_
,
1
_
_
,
mod
mod
i
i
i
i
Band
cmd
sw
Band
v
Band
cmd
sw
Band
v
(
1
0
)
whe
r
e
i
=
1,
2,
… ,
(
n
1)
.
Figu
re 5 (a
) s
h
o
w
s the u
p
p
e
r
and lo
we
r m
o
d
u
lating
wav
e
s (u
ppe
r an
d lowe
r arm
s
) for an M
M
C
whi
c
h co
nsi
s
t
s
of t
w
o PEB
B
s
per arm
(
n
=
2)
. The u
n
i
p
ol
ar si
ne wa
ve i
s
generat
e
d i
n
1
5
-
b
i
t
ful
l
scal
e (
A
m
=
7FF
F
H
). Hen
c
e,
lev
e
l-sh
ifting
m
a
g
n
itu
d
e
,
A
LS
, i
s
equi
val
e
nt
t
o
3FF
F
H
. C
o
nse
que
nt
l
y
,
Band
1
is set as 3FFF
H
.
Figure
5 (b) illustrates the s
h
ifted
m
odulating wa
ves whic
h
will
be use
d
for P
W
M. Fi
gure
5 (c
) s
h
ows the
gating signal
obtained from
(10).
To inc
r
eas
e the
resol
u
tion, t
h
e s
h
ifted m
odulating wa
ves will
be
am
plified
b
ack to
fu
ll scale (
A
m
=
7FFF
H
) before
bei
n
g com
p
ared with
the
ca
rrier
w
a
v
e
as show
n in Figu
r
e
6 (
a
)
.
Figure 6
(b) s
h
ows t
h
e m
u
lti
clocks c
r
ossing re
gion
in this
m
odule.
Since
the sine wa
ve
is gene
rated
in
2
.
5
M
H
z clo
c
k
do
m
a
in
, it
will first b
e
sa
m
p
led
u
s
i
n
g
1
5
0
M
H
z clo
c
k
b
e
fo
re t
h
e data is b
e
in
g com
p
ared.
As t
h
ese t
w
o
cl
ocks
are
sy
n
c
hr
o
n
i
zed,
t
h
e
r
e w
oul
d
be
no
dat
a
l
o
ss
whe
n
c
r
os
si
n
g
t
o
15
0 M
H
z cl
oc
k
fo
r
pr
ocessi
ng
bec
a
use t
h
e si
ne
w
a
ve i
s
ge
nerat
e
d
once
i
n
e
v
e
r
y
6
0
cy
cl
es
of t
h
e fast
cl
oc
k
[
3
2
]
.
The t
r
i
a
ng
ul
ar
carri
er
wa
ve
i
s
gene
rat
e
d
u
s
i
ng a
1
6
-
b
i
t
cou
n
t
e
r i
n
15
0
M
H
z cl
oc
k
d
o
m
a
i
n
. Thi
s
co
un
ter
will co
un
t
u
p
and
do
wn
rep
eated
l
y
after system in
itializatio
n
.
Fig
u
re
6
(a) illu
strates th
e tri
a
n
g
u
l
ar
carri
er d
e
si
g
n
i
n
t
h
i
s
pape
r. A 2 k
H
z cl
oc
k si
gnal
,
clk
sw
with
5
0
%
du
t
y
ratio
will b
e
u
s
ed
to
con
t
ro
l th
e
cou
n
t
e
r o
p
e
r
at
i
on. T
h
i
s
si
gn
al
requi
res
do
ubl
e fl
o
p
sy
nc
hr
o
n
i
zer fo
r cl
ock cr
ossi
ng i
n
t
o
1
5
0
M
H
z cl
oc
k
dom
ain as shown i
n
Figure
6 (b).
T
h
e 16-bit counter
wi
ll start count
i
n
g up at the
fa
lling edge of
clk
sw
.
In
ver
s
el
y
,
t
h
e r
i
si
ng e
dge
o
f
clk
sw
will en
ab
le th
e coun
tdown
pro
cess. Th
e in
stan
tan
e
ou
s
v
a
lu
e
o
f
t
h
e co
un
ter
form
s th
e d
e
sired
triangu
lar carrier. In
th
is
pap
e
r, th
e am
p
litu
d
e
o
f
t
h
e carrier wav
e
,
A
tri_carrier
, is esti
ma
ted
as
92
7C
H
.
2
_
sw
counter
carrier
tri
f
f
A
(
1
1
)
In
o
r
de
r t
o
c
h
ange
t
h
e s
w
i
t
c
hi
n
g
f
r
e
que
n
c
y
of M
M
C
,
a ne
w cl
oc
k s
i
gnal
whi
c
h r
e
prese
n
t
s
t
h
e
carri
e
r
fre
que
ncy
(
clk
sw
) m
u
st first be
determ
ined. The
n
t
h
e
ne
w
f
counter
can
be selected
by
tuni
ng the
desired
A
tri_carrier
. The
A
tri_carrier
m
u
st
be set
i
n
t
h
e fo
l
l
o
wi
n
g
ran
g
e
t
o
ensu
re t
h
e M
M
C
operat
e
s
i
n
l
i
n
ear
m
odul
at
i
o
n
m
ode.
A
m
<
A
tri_carrier
< FFF
F
H
(
1
2
)
whe
r
e
A
m
is de
fine
d as t
h
e m
odulating
wave
am
plitude.
The
15-bit full scale level shi
f
ted m
odulating wa
ve
will be
adjuste
d
so it
is positioned i
n
the m
i
ddle
o
f
th
e trian
g
u
l
ar wav
e
. Th
e
o
f
fset can b
e
calcu
lated
as fo
llows:
2
_
m
carrier
tri
m
A
A
offset
(1
3)
Thus, t
h
e
n
th
s
w
itching c
o
m
m
a
nd
will be
obtaine
d
by c
o
m
p
aring the
shifted m
odulating wa
ve
wit
h
th
e triangu
lar carrier u
s
i
n
g th
e fo
llo
wi
n
g
equatio
n
s
:
0
_
_
,
1
_
_
,
mod
mod
PWM
cmd
sw
v
v
PWM
cmd
sw
v
v
tri
tri
(1
4)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
94
–
1
06
10
1
s
w
_c
m
d
_B
a
n
d
1
00
00
3F
F
F
7F
F
F
Up
p
e
r
A
r
m
00
00
Ba
n
d
1
00
00
7F
F
F
Ba
nd
1
Lo
we
r
Ar
m
A
m
v
mo
d
_
u
p
S
h
i
f
t
e
d m
o
dul
a
t
i
n
g
wav
e
3F
F
F
A
LS
3F
F
F
0
1
s
w
_c
m
d
_B
a
n
d
1
00
00
Sh
i
f
t
e
d m
o
dul
a
t
i
n
g
w
a
v
e
A
LS
0
1
3F
F
F
v
mo
d
_
l
o
w
Fi
gu
re
5.
(a
)
U
ppe
r a
r
m
and l
o
we
r a
r
m
m
odul
at
i
ng
wa
vef
o
rm
s, (b)
S
h
i
f
t
e
d m
odul
at
i
n
g
wave
s f
o
r P
W
M
,
(c)
gat
e
si
gnal
s
o
b
t
a
i
n
ed
by
co
m
p
ari
ng m
odul
at
i
ng
wave
wi
t
h
t
h
e
l
e
vel
s
h
i
f
t
i
ng
ban
d
s
.
0000
FF
FF
927C
0
93D
cl
k
sw
893C
f
sw
=
2
k
H
z
f
1
= 5
0
H
z
v
mo
d
v
tr
i
09
3D
893C
of
f
s
e
t
m
v
mo
d
Sh
if
te
d m
o
dul
a
t
i
n
g
w
a
v
e
+
>=
2
.
5 MH
z
C
l
oc
k
D
o
m
a
in
a
b
a
b
cl
k
Da
t
a
in
D
a
t
a
out
16-bi
t
R
e
gi
st
er
15
2 k
H
z
C
l
oc
k
D
o
m
a
i
n
v
tr
i
f
sw
= 2
k
H
z
cl
k
D
cl
k
sw
Q
2 kH
z
cl
k
DQ
cl
k
D
Q
150 M
H
z
cl
k
C
a
rri
er W
a
v
e
G
e
n
.
f
sw
of
f
s
e
t
m
16
v
mo
d
16
PW
M
16
v
mo
d
15
0 M
H
z
C
l
oc
k
D
o
m
a
i
n
(a)
(b
)
Fi
gu
re
6.
(a
) T
h
e
desi
g
n
of
t
r
i
a
ng
ul
ar
wae
ge
nerat
i
o
n
w
h
i
c
h
al
way
s
keeps
t
h
e l
e
vel
shi
f
t
e
d
m
odul
at
i
n
g
w
a
ve
in
sid
e
it,
(b) M
u
lti clo
c
k do
main
s cro
ssi
n
g
in
Modu
latio
n
Mo
du
le
3.
4.
C
o
n
t
r
o
l
Mo
dul
e (C
ap
a
c
i
t
or
Vo
ltag
e Ba
la
ncing
Contro
l)
The l
o
gi
c
des
i
gn
di
scu
ssed
i
n
t
h
i
s
s
u
b-s
ect
i
on i
s
c
u
st
om
i
zed for i
n
di
vi
d
u
al
arm
cont
rol
.
Th
e
functional logi
c can be
dupli
cated to realiz
e the en
tire M
M
C co
n
t
ro
l by feed
ing
in t
h
e appropriate
arm
’
s
measurem
ents, i.e. each PEBB’s capac
itor voltage
s level and arm
cu
rre
nt
direction. The sa
m
p
ling event
occurs e
v
ery 250 µs
. It is finely tuned to ta
ke place
whe
n
the
carrier wa
ve
reaches
the t
op a
n
d bottom of the
wave
. The ca
pacitor voltage,
V
c
, from
each
PEBB will be sorte
d
in ascen
ding orde
r usi
n
g parallel bubble sort
(PBS) [33]. Be
fore e
n
tering t
h
e PBS proces
s, each
V
c
will b
e
tag
g
e
d
with
a
un
iqu
e
ID. Figu
re
7
shows th
e
dat
a
st
ruct
ure
.
In
ge
neral
,
P
B
S al
way
s
re
qui
res an
ev
en
nu
m
b
er
of
i
n
pu
t d
a
ta
f
o
r
th
e sor
tin
g pro
cess.
Th
erefo
r
e, MMC with
an
odd
nu
m
b
er of
PEBBs p
e
r arm
may in
clu
d
e
an ad
d
ition
a
l
V
c
(
dum
m
y
val
u
e) and set
th
e
statu
s
b
it, PEBB_NA_
h
ardware
to
‘1’. Th
e so
rti
n
g
alg
o
rith
m
will so
rt t
h
is du
mmy (
V
c
) a
s
the l
a
rgest
v
a
lu
e and
elimin
ate it at th
e
e
n
d
o
f
t
h
e s
o
rt
i
n
g
pr
ocess
.
Fig
u
re
7
.
In
pu
t
d
a
ta stru
cture
for so
rtin
g
al
go
rith
m
,
PEBB ID will
bo
t b
e
so
rted
(b
)
(a)
(c)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
VHDL Implementation of
Cpacitor
Vo
ltage
Balancing C
o
ntrol with L
evel
-Shifted … (Chuen Ling
Toh)
10
2
Fi
gu
re
8 sh
o
w
s an e
x
am
pl
e of PB
S
wi
t
h
f
o
u
r
dat
a
i
n
p
u
t
s
.
These
dat
a
wi
l
l
fi
rst
be st
ore
d
i
n
arr
a
y
a
0
,
a
1
,
a
2
, a
n
d
a
3
.
Th
en
th
ey
will b
e
g
r
ou
p
e
d
i
n
p
a
ir i
n
seq
u
en
ce (
a
x
,
a
y
) and
so
rted
in p
a
rallel. A
sortin
g sequ
en
ce
is started
wit
h
ev
en p
a
ir sortin
g. An
ev
en
pair is d
e
fi
n
e
d
by th
e first elemen
t
a
x
ha
vi
n
g
an e
v
en
su
bsc
r
i
p
t
i
o
n
num
ber, suc
h
as
(
a
0
,
a
1
) a
n
d
(
a
2
,
a
3
). Th
e
so
rted
resu
lts
will b
e
u
s
ed
by o
d
d
p
a
ir so
rtin
g
.
An
odd
p
a
ir is
defi
ned
by
a
x
hav
i
ng
an
od
d su
b
s
cr
ip
tion num
b
e
r
ele
m
en
t, i.e. (
a
1
,
a
2
). These step
s (ev
e
n-odd
so
rting)
will be
repeat
e
d
. T
h
e
desi
re
d n
u
m
b
er o
f
re
qui
red e
v
en
-
o
d
d
s
o
rt
i
n
g seq
u
e
n
ces,
n
eo
s
, i
s
al
way
s
eq
ui
val
e
nt
t
o
hal
f
of t
h
e
to
tal n
u
m
b
e
r
of inpu
t d
a
ta.
T
h
ere
f
ore, for MMC with
n
PEBBs p
e
r arm
,
n
eos
i
s
defi
ned
as
:
2
n
n
eos
(
1
5
)
Ar
r
a
y
a
0
a
1
a
2
a
3
I
nput
da
t
a
98
20
13
0
EPSR
20
98
0
13
E
PSR
:
E
v
e
n
Pa
i
r
So
r
t
i
n
g
R
e
s
u
l
t
O
P
SR
:
O
d
d
P
a
i
r
S
o
r
t
i
n
g
R
e
s
u
l
t
OP
S
R
20
0
98
13
EP
S
R
0
20
13
98
OP
S
R
0
13
20
98
S
o
r
t
i
ng S
e
que
nc
e
1
:
E
v
en
pa
i
r
:
O
dd
pa
i
r
:
E
v
e
n
-O
dd
S
o
r
t
i
ng
S
o
r
t
i
ng S
e
que
nc
e
2
Fig
u
re
8
.
Paral
l
el Bu
bb
le So
rt
in
g
ex
am
p
l
e with
fo
ur inpu
t data
Fig
u
re
9
(a) sh
ows t
h
e l
o
g
i
c d
i
agram
to
sort ou
t two
d
a
t
a
in
pu
ts. Th
is
in
pu
tted
d
a
ta
will first
b
e
co
m
p
ared
. The
co
m
p
arison
resu
lt
trigg
e
rs a
p
a
ir o
f
m
u
ltip
lex
e
rs to
p
a
ss th
e approp
ri
ate in
pu
t d
a
ta
to
th
e
corres
ponding registers
.
Regi
ster
D
out
_mi
n
keeps t
h
e smaller input dat
a
and
register
Do
ut
_
m
ax
stores the
o
t
h
e
r
d
a
ta. By
n
e
g
l
ectin
g the sign
al pro
p
a
g
a
tio
n
d
e
lay in
a con
c
u
r
ren
t
circu
it, th
e so
rting
resu
lt will be
available after
one cloc
k cycle,
T
. This logic block is nam
e
d as a 2-data
sorting m
odule. It will be used as the
m
odular bloc
k to accom
p
lis
h the PBS. For exam
ple, th
ree units of m
o
dular bl
ocks will be conne
c
ted as
sho
w
n i
n
Fi
gu
re
9
(b
) t
o
acc
om
pl
i
s
h t
h
e
fi
rst
se
que
nce
o
f
e
v
en
-o
d
d
s
o
r
t
i
ng e
v
e
n
t
s
p
r
esent
e
d
i
n
Fi
g
u
re
8
.
Thu
s
, th
is circu
it is called
an
ev
en-odd
sortin
g
m
o
du
le. This p
r
o
cess will co
m
p
lete in
2
clo
c
k
cycles (2
T
). I
n
or
der
t
o
o
p
t
i
m
ize t
h
e l
ogi
c
de
si
gn
, t
h
e
o
u
t
p
u
t
resul
t
fr
om
t
h
e eve
n
-
o
dd
s
o
r
t
i
ng m
o
d
u
l
e
ca
n
be
fed
bac
k
t
o
t
h
e
in
pu
t to
rep
eat th
e ev
en
-o
dd
so
rting
pro
cess. As a resu
lt, the d
e
sign
of PB
S is fu
lly o
p
t
i
m
ized
. Fo
r M
M
C with
n
un
its of
PEBB, o
n
l
y (
n
1) un
its o
f
m
o
du
lar b
l
o
c
k
will b
e
req
u
i
red
t
o
d
e
v
e
lop
a
basic ev
en-odd
so
rting
m
odule. T
h
e total processing t
i
m
e
to accom
p
lish PBS
for
n
dat
a
,
t
PBS
can
b
e
de
ri
ve
d as
f
o
l
l
o
ws:
T
n
t
eos
PBS
2
(
1
6
)
By su
bstitu
tin
g (1
5) i
n
to
(16), th
is co
n
t
ro
ller m
a
n
a
g
e
s to sort ou
t
n
P
E
B
B
s
pe
r a
r
m
i
n
ap
pr
o
x
i
m
at
el
y
n
cloc
k
cy
cl
es.
W
h
e
n
PEB
B
s
are ar
r
a
nge
d i
n
asce
n
d
i
n
g o
r
de
r, a si
m
p
l
e
l
ook
-
u
p
-
t
a
bl
e (L
UT) ca
n be
use
d
t
o
di
st
ri
but
e
th
e switch
i
ng
co
mman
d
s
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
94
–
1
06
10
3
Dout
_mi
n
Dout_
m
a
x
cl
k
lo
a
d
d
1
q
1
Reg
i
s
t
ers
re
g_e
n
cl
k
d
2
q
2
0
1
0
1
reg
_
ld
Di
n_0
D
i
n_1
<
a
b
a <
b
sor
t
_two_d
ata
(a)
(
b
)
Fi
gu
re
9.
(a
)
2-
dat
a
s
o
rt
i
n
g m
o
d
u
l
e
(m
odul
ar
bl
oc
k
)
,
(b
) E
v
en-
o
dd
so
rt
i
n
g
m
odul
e exam
pl
e fo
r
fo
ur
i
n
pu
t
dat
a
Figu
re 1
0
s
h
o
w
s an
LUT e
x
am
ple for M
M
C. Ass
u
m
e
tw
o PEBBs are a
v
ailable on eac
h arm
.
Input
dat
a
fo
r t
h
i
s
L
U
T i
n
cl
u
d
es ar
m
current
di
re
ct
i
on, t
h
e
posi
t
i
on o
f
t
h
e m
odul
at
i
ng wa
ve
,
v
mod
trajectory and the
sort
e
d
PEB
B
s
’
ID
. Si
nce
onl
y
2
PEB
B
s
are
use
d
,
we
di
vi
d
e
t
h
e s
o
rt
e
d
PE
B
B
s
’ I
D
i
n
p
u
t
i
n
t
o
“L
o
w
er
V
c
” and
“Higher
V
c
”.
A
r
m
curre
nt
di
r
e
ct
i
on i
s
cl
ea
rl
y
defi
ned
i
n
Fig
u
re 1
(c). Th
e cap
acitor on
th
e PEBB will b
e
ch
arg
e
d
up
b
y
po
sitiv
e arm cu
rren
t
and d
i
sch
a
rg
ed
by
ne
gat
i
v
e a
r
m
current
.
The
m
odul
at
i
ng
w
a
ve a
n
d
l
e
vel
s
h
i
f
t
i
n
g
ban
d
s
f
o
r t
h
i
s
e
x
am
ple are
gi
ve
n
by
Fi
gu
re
5 (a
).
If t
h
e m
odul
at
i
n
g
wave
t
r
aject
o
r
y
i
s
de
t
ect
ed t
o
s
w
i
n
g
bet
w
ee
n
3FF
F
and
7
FFF
, t
h
e
PEB
B
so
rt
ed i
n
t
h
e
“Lower
V
c
”
colum
n
m
u
st be allocated with
sw
_cm
d
_B
an
d
1
. Th
is
will enab
le th
e cap
aci
to
r to b
e
ch
arged
for
th
e
en
tire
swit
ch
ing
p
e
riod
(1
00
% du
ty
cycle).
Th
u
s
,
th
e
cap
acito
r
vo
ltage lev
e
l will rise du
e to
t
h
is ch
arg
i
ng
activ
ity. An
o
t
h
e
r PEBB which
is so
rted
in
th
e “Hi
g
h
e
r
V
c
” co
lu
m
n
will carry o
u
t
th
e PW
M switch
i
ng
co
mman
d
(
sw
_cm
d
_PWM
).
Inv
e
rsely, if the n
e
g
a
tiv
e arm cu
rren
t
is sa
m
p
led
,
th
e PEBB with
a h
i
g
h
e
r
V
c
v
a
lu
e shou
ld
be
fu
lly
tu
rn
ed
on
for d
i
sch
a
rg
i
n
g, wh
ile
an
o
t
h
e
r PEBB shou
ld
carry
ou
t the PW
M
du
ty cycle.
Fi
gu
re
1
0
. C
a
p
aci
t
o
r
vol
t
a
ge
bal
a
nci
n
g
co
nt
rol
L
U
T
exam
pl
e re
fer
r
i
n
g t
o
LSP
W
M
i
n
Fi
gu
re
5.
Th
e LUT
o
u
t
pu
t d
a
ta are d
i
st
ribu
ted
v
i
a a set o
f
d
e
-m
u
ltip
lex
e
rs. Th
e so
rt
ed
PEBB’s ID
will b
e
u
s
ed
as t
h
e dem
ux sel
ect
si
gnal
.
Fi
gu
re 1
1
sh
o
w
s t
h
e dem
ux ci
rcui
t
fo
r exa
m
pl
e i
n
Fi
gure
10. Last
l
y
, so
m
e
OR
gat
e
s are
u
s
ed
t
o
wra
p
u
p
eac
h
i
ndi
vi
d
u
al
PE
B
B
m
ux sel
ect
si
gnal
:
cn
DO
i
c
DO
i
c
DO
i
muxsel
i
PEBB
PEBB
PEBB
PEBB
_
_
1
_
_
0
_
_
_
...
(
1
7
)
whe
r
e
i
=
1,
2,
… ,
n
.
Fi
gu
re
1
1
.
2
u
n
i
t
s
of
de
-m
ul
t
i
pl
exe
r
are
re
q
u
i
red
fo
r e
x
am
pl
e gi
ve
n i
n
Fi
g
u
re
1
0
.
t
o
di
st
ri
but
e t
h
e L
U
T
o
u
t
p
ut
dat
a
f
o
r
eac
h i
ndi
vi
d
u
al
PEB
B
Evaluation Warning : The document was created with Spire.PDF for Python.