Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l.
7, N
o
. 1
,
Mar
c
h
20
16
,
pp
. 19
3
~
20
1
I
S
SN
: 208
8-8
6
9
4
1
93
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Novel
Single Ph
ase Full B
r
idge In
vert
er F
o
rm
ed b
y
Fl
oating
Capacit
o
rs
B.
P
r
at
ha
p R
e
d
d
y
*
,
K
.
S
reek
a
nt
h
R
e
dd
y**
,
B.
Sa
mba
Siv
a
R
e
dd
y**
*
* Depart
em
ent o
f
El
ectr
i
c
a
l
Engi
neering
,
Lovely
Professiona
l
Unive
r
si
ty
, India
** School of
Electronics and
Elec
trical Eng
i
neer
ing, Lov
e
ly
Prof
essional University
, India
***
Depart
em
en
t of
El
ectr
i
ca
l
En
gineer
ing,
Lovely
Prof
essional U
n
iversity
, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Oct 22, 2015
Rev
i
sed
D
ec 21
, 20
15
Accepte
d
Ja
n 14, 2016
In this paper, a new single-phase bri
dge inverter is described which can
generate a more steps of voltage leve
ls with reduced number of switches,
gate driv
er c
i
rc
uits and diodes
as com
p
are to
norm
a
l m
u
ltile
vel inve
rter
.
Another featur
e
of this inverter i
s
its abilit
y to pr
odeuce th
e volt
a
ges from
a
single dc-
link
power supply
which en
ab
les
back-to-b
ack o
p
eration o
f
converter.
The
proposed method with mo
re number of levels
can improve
powe
r
qua
l
ity
,
l
o
we
r swi
t
c
hi
ng l
o
sse
s a
nd produc
e
hi
gh qua
lity
vol
ta
ge
waveforms. Moreover
at
all load
power
factors the proposed method can
b
e
operated.The res
earch of the model is
done b
y
means of computer simulation
with the softw
a
re MATLAB/SIMULINK. This topolog
y
h
a
s ver
y
low
common
mode
voltag
e
variatio
n and dv/dt
stress. Also this inverter is help
full for
re
act
ive
power com
p
ens
a
tion.
Keyword:
Flo
a
tin
g Cap
a
cito
r
Fu
ll bridg
e
i
n
verter
MATLAB
SP
W
M
i
n
verte
r
THD
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
B. Pr
at
h
a
p Redd
y,
Depa
rtem
ent of Elect
ri
cal
E
n
gi
nee
r
i
n
g,
Lo
vel
y
Pr
ofes
s
i
onal
Uni
v
ersi
t
y
,
G
T Ro
ad
,
Ph
ag
w
a
r
a
, 144
411, Pu
nj
ab
,
In
d
i
a.
Em
a
il: Prath
a
p.bh
imired
d
y
@g
m
a
i
l
.co
m
1.
INTRODUCTION
Mu
ltilev
e
l in
verters are
p
o
wer electron
i
c syste
m
s wh
ich p
r
od
u
c
e a suitab
l
e AC
o
u
t
p
u
t
vo
ltag
e
wav
e
fo
rm
from
m
a
n
y
d
c
v
o
ltag
e
s as in
pu
ts
[1
]. Mu
ltilev
e
l
in
v
e
rters h
a
v
e
sev
e
ral feat
u
r
es in
co
m
p
arison
with
th
e trad
itio
n
a
l
two
-
lev
e
l v
o
l
tag
e
in
v
e
rters su
ch
as
sm
a
ller o
u
t
pu
t voltag
e
lev
e
l, better electro
mag
n
e
tic
com
p
atibility, lowe
r ha
rm
onic com
pone
nts
and l
o
we
r s
w
itc
hing losse
s [2], [3]. T
h
e conventional full bri
dge
i
nve
rt
er o
u
t
p
ut
vol
t
a
ge o
r
cu
r
r
ent
s
are
of 0
o
r
V
dc
vol
t
a
ge
.
They are nam
e
d as two-level inve
rter. In order to
obtain a qualitative output voltage and curre
nt with
redu
ce
d am
ount
of
ripple c
o
ntent, t
h
ere is a
neces
sity of
hi
g
h
ca
rri
er
f
r
e
que
ncy
al
on
g
wi
t
h
di
f
f
e
r
ent
p
u
l
s
e-
wi
dt
h
m
odul
at
i
on
(P
WM
) t
e
c
h
ni
q
u
e
s.
Ho
we
ver
I
n
hi
g
h
-
po
we
r a
ppl
i
cat
i
ons
t
h
ese
co
n
v
ent
i
o
nal
s
q
ua
re
wave
i
n
ve
rt
ers
have
certai
n
c
o
nfines
like
conducting l
o
s
s
es and
d
e
v
i
ce
ratin
gs. In
m
o
d
r
en
years, Mu
ltilev
e
l in
v
e
rters
h
a
v
e
b
e
en
u
t
i
lized
in
m
e
d
i
u
m
an
d
h
i
gh p
o
wer
applications s
u
ch as
flexi
b
le AC t
r
ansm
is
sion system
(FACTS
)
[4]
,
ind
u
strial m
o
to
r
dri
v
es
[5]
,
tractio
n
electric vehicle
applications, driv
e system
s [6], [7] a
n
d s
o
on.
The
o
u
t
p
ut
vol
t
a
ge
wave
fo
rm
i
s
al
m
o
st
a si
newa
ve
wi
t
h
m
i
nim
u
m
har
m
oni
c val
u
e,
i
m
provi
n
g
t
h
e
perform
a
nce of the
drive
p
r
esent
e
d i
n
[
8
]
and
[
9
]
as t
h
e num
ber
of
vol
t
a
ge l
e
vel
s
i
n
creases
. Th
e wo
r
k
descri
bed i
n
[
1
0]
pr
o
duces
di
f
f
ere
n
t
v
o
l
t
a
ge l
e
vel
s
by
swi
t
c
hi
n
g
th
e lo
ad
cu
rren
t throug
h
cap
acito
rs. Here, b
y
t
a
ki
ng t
h
e re
d
u
nda
nt
st
at
es f
o
r t
h
e sam
e
pol
e vol
t
a
ge, t
h
e
di
rect
i
o
n o
f
l
o
ad cu
rre
nt
t
h
ro
ug
h t
h
e
capaci
t
o
r ca
n
be cha
nge
d. I
n
t
h
i
s
pape
r,
a no
vel
st
ruct
ure f
o
r si
n
g
l
e
pha
se ful
l
bri
d
ge i
nve
rt
er i
s
prese
n
t
e
d
whi
c
h can
pr
o
duce
m
o
re num
ber
of
l
e
ve
l
s
wi
t
h
m
i
nim
u
m
requi
rem
e
nt
of
I
G
B
T
s,
gat
e
fi
ri
n
g
ci
rcui
t
s
and
di
ode
s.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
: 1
9
3
–
20
1
19
4
2.
THE
STRU
CTU
R
E
OF CONV
EN
TIO
NAL
SI
NGLE
PH
ASE I
N
V
E
RTER
The
st
ruct
ure
o
f
c
o
n
v
e
n
t
i
onal
squ
a
re
wa
ve i
n
vert
er
i
s
as fo
llo
ws lik
e figure 1. In th
is
stru
ctu
r
e, each
swi
t
c
h co
nsi
s
t
s
of an
IGB
T
and
one
di
o
d
e
(or a
n
t
i
-
pa
ral
l
e
l
di
ode
). T
h
e
out
p
u
t
wa
ve f
o
rm
of co
nve
n
t
i
onal
syste
m
is shown in Figure
2.
Fi
gu
re
1.
The
a
rra
ngem
e
nt
o
f
con
v
e
n
t
i
onal
i
nvet
e
r
Fi
gu
re
2.
O
u
t
p
ut
wa
ve
f
o
rm
of C
o
n
v
ent
i
o
nal
sy
st
em
B
y
cl
osi
ng a
n
d
ope
ni
n
g
t
h
e s
w
i
t
c
hes i
n
a
n
a
p
p
r
op
ri
at
e seq
u
ence
we ca
n
get
an ac
o
u
t
p
ut
wa
vef
o
rm
i
s
sy
nt
hesi
ze
d
fr
om
a dc i
n
pu
t
.
The
r
e a
r
e
fo
ur
di
f
f
ere
n
t
m
ode
s
depe
n
d
i
n
g
on
w
h
i
c
h
s
w
i
t
c
hes are
cl
os
ed.
The
equi
val
e
nt
ci
rc
ui
t
s
o
f
al
l
f
o
ur
m
odes are s
h
o
w
n
i
n
Fi
g
u
re
3
.
The
o
u
t
p
ut
c
u
r
r
ent
de
pen
d
s
o
n
l
o
a
d
l
i
k
e
R
o
r
R
L
.
Mo
d
e
1
:
During
th
is in
terv
al
th
e switch
e
s S
1
and
S
3
are cl
o
s
ed
. Th
e
o
u
t
pu
t lo
ad
vo
ltag
e
is zero
i.e. load
is
sh
ort circu
ited
.
V
o
=
0
(
1
)
Mo
d
e
2
:
During
th
is in
terv
al th
e switch
e
s S
1
and S
2
are clo
s
ed
. Th
e ou
tpu
t
lo
ad
v
o
ltag
e
is eq
u
a
ls to
th
e i
n
pu
t
vol
t
a
ge (V
dc
) i.e. load is connected across source
dir
ectly. And
th
e lo
ad
cu
rren
t fl
o
w
s t
h
roug
h
V
dc
- S
1
- Lo
ad
-
S
2
and
V
dc
.
V
o
= V
dc
(
2
)
Fi
gu
re
3(a
)
.
M
ode
1
Fi
gu
re
3(
b
)
. M
ode
2
In a sim
i
lar m
a
n
n
e
r t
h
e
o
u
t
p
u
t
vo
ltag
e
will hav
e
a
n
e
g
a
tiv
e
o
f
inp
u
t
vo
ltage
state and
zero
v
o
ltag
e
state.
V
o
= -V
dc
(
3
)
And
t
h
is cycle
will rep
eats
con
tin
uou
sly.
The
rm
s out
p
u
t
v
o
l
t
a
ge i
s
,
V
o
=
(
Vdc
/
)
1/2
=
V
dc
(
4
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
N
o
vel
Si
ngl
e
P
has
e F
u
l
l
Bri
d
ge
Inver
ter Form
ed by Floa
tin
g Capa
cito
rs
(
B
. Prat
ha
p
Re
ddy)
19
5
The Ta
bl
e
1 S
h
o
w
s t
h
e
di
f
f
e
r
ent
s
w
i
c
hi
ng
st
at
es of
co
n
v
e
n
t
i
onal
f
u
l
l
b
r
i
dge
i
n
vert
er
.
Switch
e
s S1
and
S4
or
(S2
and
S3) s
h
oul
d
not be t
u
rne
d
on sim
u
ltaneously.
Othe
rwi
s
e, a dea
d
zone interval take
s place
acros
s the
dc
s
o
urce.
Tabl
e 1. Swi
t
c
h
st
at
es of
S
q
u
a
re wave
i
n
ver
t
er
Mode
On Position
Vo
1
S1 & S3
0
2
S1 & S2
+ Vdc
3
S2 & S4
0
4
S3 & S4
- Vdc
3.
PROP
OSE
D
I
NVE
RTER
The propose
d
structure of full
brid
ge inverter is shown i
n
Figure 4.
In this struct
ure
,
each s
w
itch
cont
ai
n
s
of
an
I
G
B
T
a
n
d
o
n
e
di
o
d
e
(
o
r
an
t
i
-
paral
l
e
l
di
ode) also one
ca
pacitor an
d
one sm
all resistor are
co
nn
ected acro
ss each
switch
.
Th
e
p
r
op
o
s
ed
inv
e
rter
g
i
v
e
s a
q
u
a
litativ
e ou
t
p
u
t
v
o
l
t
a
g
e
an
d
curren
t
wit
h
red
u
ce
d am
oun
t
of
ri
p
p
l
e
c
o
nt
ent
.
Al
so
t
h
i
s
i
nve
rter is h
e
l
p
fu
ll in reactiv
e
p
o
wer co
m
p
en
satio
n
.
By in
creasing
th
e no
o
f
levels in
th
is inv
e
rt
er,
th
e
po
wer ratin
g
of inv
e
rter can
b
e
increased
with
out
requirem
ent of high ratings
devices
. T
h
e
uni
que
structur
es of this
propos
ed i
nve
rter allow
reachi
n
g hi
gh
vol
t
a
ge
wi
t
h
m
i
nim
u
m
harm
oni
c cont
ent
wi
t
h
o
u
t
t
h
e
us
age of tra
n
s
f
ormers or
ca
scade connecte
d
s
w
itching
devi
ces
.
As t
h
e
num
ber
of
o
u
t
p
ut
l
e
vel
s
i
n
crea
ses, t
h
e
out
put
v
o
l
t
age ha
rm
oni
c co
nt
ent
decr
eases
si
gni
fi
ca
nt
l
y
. T
h
e
out
put
vol
t
a
ge
wave
f
o
rm
of
p
r
o
p
o
se
d sy
st
em
i
s
as fol
l
o
ws l
i
k
e
Fi
g
u
re
5.
Fi
gu
re 4.
The
Ar
ran
g
em
ent
o
f
pr
op
ose
d
i
n
v
e
rt
er
Fi
gu
re
5.
O
u
t
p
ut
wa
ve
f
o
rm
of C
o
n
v
ent
i
o
nal
sy
st
em
There a
r
e al
so
ei
ght
di
f
f
ere
n
t
m
odes de
pe
ndi
ng
o
n
w
h
i
c
h swi
t
c
h
e
s ar
e cl
osed
. The
equi
val
e
nt
ci
rcui
t
s
o
f
al
l
e
i
ght
m
odes a
r
e
fol
l
o
ws l
i
k
e
i
n
Fi
gu
re
6.
The
out
put
c
u
rre
nt
depe
n
d
s
o
n
l
o
a
d
l
i
k
e R
o
r
R
L
.
Mo
d
e
1
:
During
th
is p
e
riod
the switch
e
s S
1
and S
3
are clo
s
ed
. Th
e ou
tpu
t
lo
ad
v
o
ltag
e
is zero
i.e. lo
ad
is sh
ort
circu
ited
.
V
o
=
0
(
5
)
M
ode 2:
Du
ri
ng
t
h
i
s
peri
od t
h
e
swi
t
c
h
S
1
i
s
close
d
. T
h
e
out
put l
o
ad voltage is equals
to the
differe
n
ce
of
in
pu
t v
o
ltag
e
(V
dc
) a
n
d ca
pac
i
t
o
r
vol
t
a
ge
(
V
c
)
.
A
nd th
e
lo
ad
cu
rr
en
t f
l
ow
s th
rou
g
h
V
dc
- S
1
- L
o
a
d
– ca
pacitor
and V
dc
.
V
o
= V
dc
- V
c
= V
dc
/
2
(
6
)
Here con
s
id
er t
h
e
v
o
ltag
e
across th
e
resistor i
s
n
e
g
lig
ib
le and
V
c
V
dc
/2.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
: 1
9
3
–
20
1
19
6
Fi
gu
re
6(a
)
.
M
ode
1
Fi
gu
re
6(
b
)
. M
ode
2
M
ode 3:
D
u
ri
n
g
t
h
i
s
peri
od t
h
e swi
t
c
hes S
1
and S
2
are cl
o
s
ed. T
h
e o
u
t
p
u
t
l
o
ad vol
t
a
ge i
s
equal
s
t
o
t
h
e
i
nput
vol
t
a
ge (V
dc
) i.e. load is connected across source
dir
ectly. And
th
e lo
ad
cu
rren
t fl
o
w
s t
h
roug
h
V
dc
- S
1
- Lo
ad
-
S
2
and
V
dc
.
V
o
= V
dc
(
7
)
M
ode
4:
M
o
de
2 an
d
peri
od
4
are sam
e
onl
y
t
h
e swi
t
c
hi
n
g
s
e
que
nce i
s
di
ff
erent
.
D
u
ri
n
g
t
h
i
s
pe
ri
o
d
t
h
e s
w
i
t
c
h
S
2
is clo
s
ed
. Th
e ou
tpu
t
lo
ad v
o
ltag
e
is equals to
th
e d
i
fferen
ce
o
f
inp
u
t
v
o
ltag
e
(V
dc
) an
d
cap
acito
r
vo
ltag
e
(V
c
). And
th
e lo
ad
cu
rren
t fl
ows th
rou
g
h
V
dc
– capacitor
- Loa
d
- S
2
a
nd V
dc
. The
out
pu
t
vol
t
a
ge i
s
fol
l
ows as
equat
i
o
n (
6
).
Fi
gu
re
6(c
)
.
M
ode
3
Fi
gu
re
6(
d
)
. M
ode
4
Mo
d
e
5
:
During
th
is p
e
riod
the switch
e
s S
2
and S
4
are clo
s
ed
. Th
e ou
tpu
t
lo
ad
v
o
ltag
e
is zero
i.e. lo
ad
is sh
ort
ci
rcui
t
e
d.
T
h
e
out
put
v
o
l
t
a
ge
i
s
fol
l
o
ws
as e
quat
i
o
n
(
5
)
M
ode 6:
Du
ri
ng
t
h
i
s
peri
od t
h
e
swi
t
c
h
S
4
i
s
close
d
. T
h
e
out
put l
o
ad voltage is equals
to the
differe
n
ce
of
in
pu
t vo
ltag
e
(V
dc
) and
cap
a
cito
r vo
ltag
e
(V
c
). A
n
d the loa
d
cu
rre
nt flo
w
s
thro
u
gh
V
dc
-
capacitor
- Lo
a
d
– S
1
and V
dc
.
V
o
= - (V
dc
- V
c)
= -
V
dc
/
2
(
8
)
Fi
gu
re
6(e
)
.
M
ode
5
Fi
gu
re
6(
f)
. M
ode
6
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
N
o
vel
Si
ngl
e
P
has
e F
u
l
l
Bri
d
ge
Inver
ter Form
ed by Floa
tin
g Capa
cito
rs
(
B
. Prat
ha
p
Re
ddy)
19
7
M
ode
7:
D
u
ri
ng t
h
i
s
pe
ri
o
d
t
h
e swi
t
c
hes
S
3
and
S
4
are
clo
s
ed. Th
e
ou
tpu
t
lo
ad
vo
ltag
e
is eq
uals to
th
e
negat
i
v
e o
f
i
n
put
vol
t
a
ge (
V
dc
) i.e. loa
d
is connected a
c
ross
source
directly. And
th
e lo
ad
current flo
w
s
th
ro
ugh
V
dc
–
S
3
- L
o
a
d
-
S
4
and V
dc
.
V
o
= -V
dc
(
9
)
M
ode
8:
D
u
ri
ng
t
h
i
s
peri
od
de t
h
e s
w
i
t
c
h
S
2
is closed.
Th
e
ou
tpu
t
lo
ad
v
o
ltag
e
is eq
u
a
ls to
t
h
e
neg
a
tiv
e
d
i
fferen
ce of in
pu
t vo
ltag
e
(V
dc
) and
cap
a
cito
r vo
ltag
e
(V
c
). An
d
th
e lo
ad
cu
rr
en
t f
l
o
w
s t
h
ro
ugh
V
dc
–
capacitor - L
o
ad - S
2
and V
dc
. Th
e
ou
tpu
t
vo
ltag
e
is fo
l
l
o
w
s as equ
a
ti
o
n
(8
) and
th
i
s
cycle will rep
eats
co
n
tinuo
usly.
Fi
gu
re
6(e
)
.
M
ode
7
Fi
gu
re
6(
f)
. M
ode
8
The Ta
bl
e
2.
S
h
o
w
s t
h
e
di
f
f
er
ent
s
w
i
c
hi
n
g
st
at
es of
p
r
op
ose
d
ful
l
bri
d
ge i
n
vert
er
.
Tabl
e 2.
s
w
i
t
c
h
st
at
es
o
f
pr
op
o
s
ed ful
l
bri
dge
i
nve
rt
er
State
Switches Closed
Vo
1
S1 & S3
0
2
S1
+ V
dc
/2
3
S1 & S2
+ V
dc
4
S2
+ V
dc
/2
5
S2 or S4
0
6
S4
- V
dc
/2
7
S3 & S4
- V
dc
8
S3
- V
dc
/2
4.
CO
MP
ARI
S
O
N
OF P
R
O
P
OSED
STR
U
C
TU
RE WIT
H
C
O
N
V
ENT
I
ON
AL ST
R
UCT
URE
The co
nve
nt
i
o
nal
ful
l
bri
dge
i
nvert
er
out
pu
t
vol
t
a
ge or c
u
rre
nt
coul
d be
ei
t
h
er 0 or
V
dc
. Thes
e
in
v
e
rters are also
n
a
m
e
d
as
two
lev
e
l inv
e
rter.
To
g
e
t a qu
alitativ
e voltag
e
wav
e
form
an
d
curren
t
with
red
u
ce
d am
ount
of
ri
p
p
l
e
cont
e
n
t
,
t
h
ese i
nve
rt
ers
req
u
i
r
e hi
g
h
er f
r
e
q
u
e
ncy
of ca
rri
e
r
si
g
n
al
al
on
g
wi
t
h
di
ffe
re
nt
p
u
l
s
e
-
wi
dt
h m
o
d
u
l
a
t
i
on
(P
W
M
) t
e
chni
que
s.
H
o
w
e
ver
i
n
hi
g
h
-
p
owe
r
a
p
pl
i
cat
ions
, t
h
ese t
w
o
l
e
vel
i
nve
rt
ers
hav
e
cert
a
i
n
c
o
n
f
i
n
es l
i
k
e c
o
nd
uct
i
o
n
l
o
sses
and
de
vi
ce rat
i
ngs
. Ta
bl
e 3
gi
ves t
h
e c
o
m
p
ai
si
o
n
b
e
tween
co
nv
en
tio
n
a
l t
w
o level in
v
e
rter and
th
e
pro
p
o
s
ed
fiv
e
lev
e
l (lin
e vo
ltag
e
)
inv
e
rter.
Tabl
e
3. C
o
m
p
ari
s
o
n
bet
w
ee
n
co
nve
nt
i
o
nal
a
n
d
p
r
op
ose
d
st
ruct
ures
Para
m
e
ter
Conventio
nal Full br
idge inver
t
er
Pr
oposed inver
t
er
No of outp
u
t volta
ge levels
2(line voltage)
5(line voltage)
T
o
tal har
m
onic distor
tion
48%
19.
60%
Voltage stresses ac
ross switches
high
Lo
w
Output power
low
High
Electro
m
a
gnetic in
terf
erence
high
Lo
w
dv/dt r
a
tio
high
Lo
w
Output voltage wave shape
Squar
e
wave
Appr
oxim
a
te sine
wave
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
: 1
9
3
–
20
1
19
8
Th
e
p
r
op
o
s
ed
i
n
v
e
rter
g
i
v
e
s a qu
alitativ
e v
o
l
tag
e
and
cu
rren
t wav
e
form
with
redu
ced
ripp
le con
t
en
t.
Also
t
h
is inv
e
rter is h
e
l
p
fu
ll
in
reactiv
e power co
m
p
en
sat
i
o
n
.
W
ith th
is
p
r
op
o
s
ed
st
ru
ctu
r
e it m
a
y eas
ier t
o
pr
o
duce a
hi
g
h
po
wer
,
hi
gh
v
o
l
t
a
ge i
n
vert
er
due t
o
t
h
e v
o
l
t
age st
resses a
c
ross eac
h s
w
i
t
ch i
s
cont
rol
l
e
d. T
h
e
l
i
m
i
t
a
t
i
ons of
con
v
e
n
t
i
onal
t
w
o l
e
vel
i
n
vert
er a
r
e
ove
rcom
e by
pr
o
pos
ed i
nve
rt
er
. Tabl
e
4 gi
v
e
s t
h
e
co
m
p
aisio
n
b
e
tween three level
m
u
ltilev
e
l in
v
e
rter and
t
h
e
p
r
op
o
s
ed
fiv
e
lev
e
l (lin
e vo
ltag
e
) inv
e
rter.
Tab
l
e
4
.
C
o
m
p
arison
b
e
tween th
ree lev
e
l m
u
ltilev
e
l in
v
e
rter and
p
r
op
o
s
ed
i
n
v
e
rter
Para
m
e
ter
Three
level
m
u
lti l
e
vel
inverter
Pr
oposed inver
t
er
No of outp
u
t volta
ge levels
5(line voltage)
5(line voltage)
Voltage stresses ac
ross switches
me
d
i
u
m
Lo
w
No of switches
high
low
Electro
m
a
gnetic in
terf
erence
Med
i
u
m
Lo
w
5.
SIMULATION RESULTS
In
th
is section, th
e MATLAB so
ftware is u
tili
zed
for sim
u
la
tio
n
.
Figure 7
shows resu
lts o
f
th
e
no
rm
al
si
ngl
e pha
se i
nve
rt
er
i
.
e. out
put
v
o
l
t
a
ge o
u
t
p
ut
cur
r
ent
an
d t
h
ei
r
harm
oni
c spect
rum
s
. The i
nve
rt
er i
s
havi
ng
o
n
e su
p
p
l
y
sou
r
ce as
DC
wi
t
h
a m
a
gni
t
u
de
of
10
V
.
A l
o
a
d
w
h
i
c
h
have
bee
n
t
a
k
e
n as t
h
e R
-
L l
o
ad
(R
= 1
Ω
an
d L
=
1
00m
H)
fo
r s
i
m
u
l
a
t
i
on p
u
r
p
ose.T
h
e
swi
t
c
hes a
r
e
IGB
T
’
s
wi
t
h
i
n
t
e
r
n
al
di
o
d
es
an
d
h
a
vi
n
g
internal resista
n
ce of
1m
Ω
.
The t
o
t
a
l
harm
oni
c
di
st
o
r
t
i
o
n
(TH
D
)
i
s
a
po
pul
a
r
pe
rf
o
r
m
a
nce i
n
de
x w
h
i
c
h est
i
m
at
es t
h
e am
ount
o
f
harm
oni
c c
ont
ent
i
s
pre
s
ent
e
d i
n
t
h
e
out
put
wa
vef
o
rm
f
o
r
t
h
e
p
o
w
e
r
c
o
n
v
e
r
t
e
rs.
Di
ffe
re
nt
m
odul
at
i
o
n
m
e
t
hods
ha
ve
been
i
n
t
r
o
duce
d
fo
r i
nve
rt
ers
nam
e
l
y
t
r
apezoi
d
al
m
o
d
u
l
a
t
i
on,
st
ep
pe
d
m
odul
at
i
on,
S
P
W
M
,
space
vector PWM a
n
d m
odified
refe
re
nce
with m
u
lti carrier wa
veform
s.
(a)
(b
)
Fi
gu
re
7.
Si
m
u
l
a
t
i
on res
u
l
t
s
f
o
r
co
n
v
ent
i
o
na
l
sy
st
em
(a) ha
rm
oni
c spect
r
u
m
of o
u
t
p
ut
v
o
l
t
a
ge
(TH
D
=
4
8
.
3
4
%
)
;
(
b
)
Ha
rm
oni
c spect
r
u
m
of
out
put
c
u
rre
nt
(TH
D
=
1
2
.
1
2
%
)
In t
h
i
s
pape
r, t
h
e Si
n
u
s
o
i
d
al
P
W
M
has
bee
n
us
e
d
. T
h
e Si
nus
oi
dal PW
M
technique can
eliminate the
lo
wer ord
e
r h
a
rm
o
n
i
cs alo
ng with
th
e con
t
ro
l of inv
e
rter o
u
p
u
t
v
o
ltag
e
. Th
e requ
iremen
t o
f
filter will b
e
m
i
nim
i
zed as t
h
e
hi
g
h
er
o
r
de
r
ha
rm
oni
cs
can be elim
inated easily with SPWM.
Fi
gu
re
8 s
h
o
w
s t
h
e p
r
op
ose
d
si
ngl
e
pha
se
i
nve
rt
er si
m
u
lat
i
on ci
rc
ui
t
al
on
g
wi
t
h
i
t
s
v
o
l
t
a
ge a
n
d
current
wa
veform
s. The inve
rter is
ha
vi
n
g
o
n
e s
u
p
p
l
y
so
ur
ce as DC
wi
t
h
a
m
a
gni
t
u
de o
f
10
V.
A l
o
ad
whi
c
h
have
bee
n
t
a
ke
n as
t
h
e R
-
L l
o
ad
(R
=
1
Ω
a
n
d
L =
1
0
0
m
H
) f
o
r si
m
u
l
a
t
i
on
pu
r
pose
.
T
h
e
swi
t
c
hes a
r
e
I
G
B
T
’s
wi
t
h
i
n
t
e
rnal
d
i
odes
an
d
ha
vi
ng
i
n
t
e
r
n
al
res
i
st
ance o
f
1m
Ω
al
so
ha
vi
n
g
paral
l
e
l
ca
paci
t
o
rs.
Fi
g
u
r
e
9
sho
w
s
t
h
e harm
oni
c spect
r
u
m
of out
p
u
t
vol
t
a
ge (TH
D
=
1
9
.
6
0
%
)
, ha
rm
oni
c spect
r
u
m
of ou
t
put
cu
rre
nt
(
T
HD
=
3.
09
%) o
f
pr
op
ose
d
i
n
vert
e
r
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
N
o
vel
Si
ngl
e
P
has
e F
u
l
l
Bri
d
ge
Inver
ter Form
ed by Floa
tin
g Capa
cito
rs
(
B
. Prat
ha
p
Re
ddy)
19
9
(a)
(b
)
(c)
(
d
)
Fi
gu
re
8.
Si
m
u
l
a
t
i
on res
u
l
t
s
o
f
pr
op
ose
d
i
n
v
e
rt
er
(a) C
i
r
c
ui
t
di
ag
ram
;
(b)
SP
W
M
seq
u
e
n
ce f
o
r
swi
t
c
hes
(s
ub
-
circu
it); (c)
Outp
u
t
v
o
ltage; (d) Ou
t
p
u
t
cu
rren
t
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
: 1
9
3
–
20
1
20
0
Fig
u
re
9
.
Sim
u
latio
n
resu
lts
fo
r conv
en
tion
a
l syste
m
(a) Si
m
u
la
tio
n
ou
t
p
ut v
o
ltag
e
an
d harm
o
n
i
c sp
ectru
m
(TH
D
=
1
9
.
6
0
%
)
;
(
d
)
Si
m
u
l
a
t
i
on
o
u
t
p
ut
c
u
r
r
e
n
t
an
d
ha
rm
oni
c spect
r
u
m
(THD=
3
.
0
9
%
)
6.
CO
NCL
USI
O
N
In th
is
p
a
p
e
r, a
n
e
w m
u
ltil
ev
el
v
o
ltag
e
so
urce i
n
v
e
rter h
a
s
b
een prop
o
s
ed. Fo
r the propo
sed
structure, each
switch c
o
nsists of a
n
IGBT a
n
d one a
n
ti-
parallel diode
also one ca
p
acitor
and one
resistor are
co
nn
ected
across th
e switch.
Th
e
p
r
o
p
o
s
ed
i
n
v
e
rter
g
i
v
e
s a q
u
a
litativ
e ou
t
p
u
t
v
o
ltag
e
and
curren
t
wav
e
for
m
with
reduce
d a
m
ount of
ripple content.
Als
o
t
h
is inve
rte
r
is help full in
reac
tive
powe
r com
p
ensation. T
h
e
sim
u
l
a
t
i
on res
u
l
t
s
ha
ve bee
n
prese
n
t
e
d
f
o
r t
h
e p
r
op
ose
d
i
n
vert
er
usi
ng t
h
e SP
W
M
t
e
c
h
n
i
que.
Fr
om
t
h
e resul
t
s
of t
h
e
pr
o
pose
d
sy
st
em
THD
val
u
e
i
s
re
duc
ed
whe
n
c
o
m
p
are t
o
c
o
nve
nt
i
onal
sy
st
em
. The
pr
op
ose
d
i
n
vert
er
use
d
in
F
A
CT
S,
UPS
,
AS
Ds,
an
d
Var
com
p
ensato
rs.
ACKNOWLE
DGE
M
ENTS
I m
a
ni
fest
m
y
heart
i
e
r t
h
a
n
kf
ul
nes
s
pert
ai
ni
n
g
t
o
o
u
r c
ont
e
n
t
m
ent
over. M
r
K S
r
e
e
kant
h R
e
d
d
y
,
Assistant profe
ssor,
Sc
ho
ol
of
Electronics & Electrical Engi
neeri
n
g,
Lo
ve
l
y
Profe
ssi
o
n
al
Uni
v
ersi
t
y
, P
u
nja
b
fo
r
hi
s preci
ou
s sug
g
est
i
o
ns apa
r
t
fr
om
general
gui
da
nce, co
nst
a
nt
enc
o
ura
g
em
ent
t
h
rou
g
h
o
u
t
m
y
wor
k
, wi
t
h
o
u
t
wh
ich
it wou
l
d prob
ab
ly no
t po
ssib
l
e
fo
r m
e
to
b
r
i
n
g ou
t the wo
rk
i
n
th
is
fo
rm
.
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NC
ES
[1]
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Sys. Tech
.,
2003; 11(3): 345-
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[2]
JH Kim
,
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e
t
i
. A
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ased PWM m
e
t
hod with
optim
al swit
chin
g sequence for
a m
u
ltil
evel
four-
leg vo
ltag
e
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ce
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a
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Z
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e
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til
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[7]
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W
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e
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e
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e
e –
s
tage h
y
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u
ltilevel cascaded-t
y
p
e d
y
n
a
m
i
c
voltag
e
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emplo
y
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n
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u
, S. Ale
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i
nowski, P. Cortes, and J.R.
Rodriguez
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M
ultile
vel dire
ct powe
r
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e
ralized approach f
o
r grid-
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e
l conver
t
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PED
S
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S
SN
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8-8
6
9
4
N
o
vel
Si
ngl
e
P
has
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u
l
l
Bri
d
ge
Inver
ter Form
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rs
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. Prat
ha
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ddy)
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1
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ard
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e
vel conv
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e
-source i
nverters”,
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r Electron.
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BIOGRAP
HI
ES OF
AUTH
ORS
B. Prath
a
p Redd
y
was born
in A
n
antapur
, Andhr
a Prad
esh, in 19
93. He r
e
ceived
the B
.
E. degr
ee
in electrical and
electron
i
cs
engineering
from JNTU, Ananta
pur,
India, in 2014
.
He is curr
ently
working toward
the M
.
T
ech d
e
gree
in P
o
wer ele
c
troni
cs
an
d drives
, Lov
e
l
y
P
r
ofes
s
i
onal
Univers
i
t
y
P
unj
ab. His
curr
ent
res
ear
ch int
e
re
s
t
s
include
rene
wable En
erg
y
s
y
s
t
em
s
,
pwm
converters, moto
r drives, an
d
electromechan
ic s
y
stems.
K. Sreekanth Redd
y
was born in Kadapa, Andhra Pr
adesh, in 1987. He received the B.E. d
e
gree
in el
ec
tric
al
and
el
ectron
i
cs
eng
i
neer
ing from
J
N
TU, H
y
d
e
rab
a
d, Indi
a,
in 200
8. He r
e
c
e
ived
M.Tech
degree
in Power electr
onics and driv
es, from VIT University
in 201
0. From 2010
onwards he is working as an Assistant profe
ssor in Lovely
Professional Univrsity
and his
research
ar
ea
of
inter
e
sts ar
e Mul
tilev
e
l
inver
t
ers,
power qual
i
t
y
an
d drives.
B. Samba Siva
Redd
y
was born in Anantapu
r,
Andhra Pradesh, in 1992.
He receiv
e
d th
e B.E.
degree in electrical a
nd electron
ics engineering from JNTU,
An
antapur
, India, in 2014. He is
current
l
y
worki
ng toward the
M
.
Tech degr
e
e
in P
o
wer el
ectron
i
cs
and
drives
, Lov
e
l
y
P
r
ofes
s
i
onal Univers
i
t
y
, P
unj
ab.
His
current res
earch in
ter
e
s
t
s
include power e
l
ectron
i
cs
, and
power quality
, r
e
newabl
e
en
erg
y
s
y
s
t
em
s
.
Evaluation Warning : The document was created with Spire.PDF for Python.