Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
Vol
.
6
,
No
. 2,
J
une
2
0
1
5
,
pp
. 25
3~
25
9
I
S
SN
: 208
8-8
6
9
4
2
53
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Clos
ed L
oop Analysis of
B
r
id
geless SEPIC Con
verter for Drive
Application
Gopin
a
th M*,
G. Gopu
**
*Dr.N.G.P. Institute of
Techno
lo
g
y
,
Coim
bator
e
,
Tam
ilnadu
,
Ind
i
a
**Sri Ramakrish
n
a Engg
College, Coimbator
e
, In
dia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Dec 23, 2014
Rev
i
sed
Feb
21
, 20
15
Accepted
Mar 20, 2015
In this paper clo
s
ed loop analy
s
is
of
Single phase AC-DC Bridg
e
less Single
Ended Primar
y
Inductan
ce Con
v
erter (S
EPIC) f
o
r Power Factor
Correction
(PFC) rectifier
is analy
zed
. In this
topolog
y
the absence of an input diode
bridge
and th
e d
u
e to pr
esence o
f
two
semicondu
ctor switches in
the
current
flowing path d
u
ring each swi
t
ching c
y
c
l
e w
h
ich will resul
t
s
in lesser
conduction losses and improv
ed therma
l management compared to th
e
conventional co
nverters. In
this
pape
r th
e oper
a
tional p
r
inciples
, Frequen
c
y
analy
s
is,
and design equations
of the
proposed
converter ar
e described
in
detail. Performance of the propo
sed SEPI
C PFC
rect
ifier
is carri
e
d
out using
Matlab
Sim
u
link
software
and
res
u
lts ar
e pr
esente
d.
Keyword:
Brid
g
e
less rect
ifier
Low co
ndu
ction
losses
Power factor
c
o
rrection
Rectifier
Si
ngl
e e
n
ded
p
r
i
m
ary
-
i
nduct
o
r
con
v
e
r
ter (SEP
IC)
c
o
nve
rter
Tot
a
l
ha
rm
oni
c di
st
o
r
t
i
o
n
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
M
.
G
opi
nat
h
Dr. N.G.P. In
st
itu
te o
f
Tech
nolo
g
y
,
Co
im
b
a
to
re-48, Ind
i
a
Em
ail: gopiavi
1
1@outlook.c
om
1.
INTRODUCTION
Due t
o
the inc
r
ease on
high e
fficiency and l
o
w
h
a
rm
o
n
i
c po
llu
tio
n, th
e PFC circu
its are co
mm
o
n
l
y
em
pl
oy
ed i
n
a
c
–dc c
o
nve
rt
e
r
s an
d al
so i
n
swi
t
c
hed
-
m
ode p
o
w
er s
u
p
p
l
i
e
s. Ge
neral
l
y
,
i
n
t
h
ese ki
nds
o
f
co
nv
erters i
n
clu
d
e
a
fu
ll-b
r
i
d
g
e
d
i
od
e
rectifier on
an
i
n
put cu
rren
t
p
a
t
h
, so th
at co
nductio
n
l
o
sses
will b
e
worse esp
ecial
ly at
th
e lo
w li
n
e
. To
o
v
e
rcome th
is p
r
o
b
l
em
,
b
r
id
g
e
less co
nv
erters is in
trodu
ced
to
redu
ce o
r
eliminate the full-bri
dge
rec
tifier, and he
nce a c
onduct
i
on losses [1]–[3]. Recently, seve
ral bridgeles
s
t
o
p
o
l
o
gy
ha
ve
been
i
n
t
r
o
duce
d
t
o
i
m
prove
t
h
e
rect
i
f
i
e
r
po
wer
de
nsi
t
y
an
d al
s
o
t
o
re
duc
e n
o
i
s
e em
i
ssions
v
i
a
so
f
t
-
s
w
itch
i
n
g
tech
n
i
qu
es or
co
up
led m
a
g
n
e
tic to
po
log
i
es [4
]–
[6
].
I
n
conven
tio
n
a
l
PFC
Bu
ck conv
er
ter
s
, t
h
e
o
u
t
p
u
t
vo
ltag
e
o
f
th
e co
nv
erter in
[7
] and
[8] is
lo
wer th
an th
e p
eak
v
a
lue o
f
th
e inp
u
t
v
o
ltag
e
. In
[9
]–
[13
]
,
sev
e
r
a
l
br
idg
e
less sing
le-
e
nd
ed pr
im
ar
y i
n
du
ctor
con
v
e
r
t
er
s
(
S
EPI
C
s) w
e
r
e
p
r
op
o
s
ed
,
ho
w
e
v
e
r
i
n
th
is
co
nv
erter, an
in
pu
t ind
u
c
t
o
r
with
large in
du
ctan
ce sho
u
l
d
b
e
u
s
ed
in
o
r
der to
redu
ce the in
pu
t cu
rren
t rip
p
l
e.
Th
e
abo
v
e
literatu
re
rev
i
ew d
o
e
s n
o
t
d
eal with
,
a b
r
idg
e
l
e
ss SEPIC conv
erter wit
h
ri
pp
le-free i
n
pu
t
cu
rren
t,
clo
s
ed loo
p
analysis an
d
Fr
equ
e
n
c
y
r
e
sp
on
se an
alysis of
t
h
e Br
idg
e
less SEPI
C PFC conver
t
er
f
e
d D
C
driv
e.
2.
BRID
GELESS SEPI
C
CO
NVE
RTER
2.1. Circuit
Operation
The p
r
o
p
o
se
d bri
dgel
e
ss SE
P
I
C
con
v
ert
e
r i
s
sho
w
n i
n
Fi
g
u
re 1
,
w
h
i
c
h i
s
cont
ract
e
d
by
con
n
ect
i
n
g
two
d
c
-d
c conv
erters. During th
e po
sitiv
e half-lin
e cycle,
th
e first
p
a
rt
o
f
circu
it L1- Q1 –
L3
–
Do
is
activ
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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:
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Vo
l. 6,
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.
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Ju
ne 20
15
:
253
–
2
59
25
4
th
ro
ugh
d
i
od
e
Dp, wh
ich
is co
nn
ecting
th
e i
n
pu
t ac sour
ce
to
th
e ou
tpu
t
groun
d. Du
ri
n
g
th
e n
e
g
a
tiv
e h
a
lf-lin
e
cycle, th
e secon
d
p
a
r
t
o
f
cir
c
u
it, L2-
Q2
-
C
2
-
L3
-
Do
, is
activ
e th
ro
ugh d
i
od
e Dn
,
w
h
ich
is co
nn
ecti
n
g
t
h
e
in
pu
t ac sou
r
ce to
th
e o
u
t
pu
t g
r
o
und
. Gen
e
rally i
t
is su
fficien
t to
an
alyze th
e circu
it o
n
l
y d
u
r
i
n
g
the po
sitiv
e
h
a
lf
o
f
t
h
e inpu
t vo
ltag
e
.
Apart fro
m
th
at, th
e
o
p
e
ratio
n of
th
e pro
p
o
s
ed
rectifiers will be b
r
iefly d
e
scri
b
e
d b
y
assum
i
ng that the three i
n
duc
t
ors are
operat
ing in
DCM.
Because of thi
s
several a
dva
ntages ca
n be gaine
d
.
These a
dva
nta
g
es include the
following
: th
ere is ap
pro
x
i
mate n
ear-un
ity
powe
r factor, t
h
e power s
w
itches are
t
u
r
n
ed
on at
zero cu
rr
ent
,
a
n
d t
h
e o
u
t
p
ut
di
ode
Do i
s
turned off at zero
current.
Thu
s
,
th
e lo
sses du
e to
th
e
tu
rn
-o
n
switch
i
n
g
an
d
the reverse reco
v
e
ry o
f
th
e
o
u
t
p
u
t
dio
d
e
are co
nsiderab
ly red
u
c
ed. Du
e to
filter circu
i
t
acros
s t
h
e out
p
u
t
DC
i
s
ri
ppl
e
free. C
o
upl
e
d
inductors are also use
d
to reduce
th
e ripp
le co
n
t
en
t in
th
e circu
it.
Si
m
ilar
l
y th
e Ef
f
i
cien
cy
o
f
th
e pr
opo
sed conver
t
er
can
b
e
imp
r
ov
ed.
Figure
1.
Propose
d SE
PIC C
o
nve
r
ter
2.
2. E
ffi
ci
enc
y
Impr
ove
ment
The effi
ci
e
n
cy
of t
h
e pr
o
pose
d
co
nve
rt
er ca
n be im
pro
v
e
d
by
i
)
. The vol
t
a
ge dr
op
of a M
O
SFET i
s
i
g
n
o
re
d,
i
i
)
. T
h
e
po
we
r di
ssi
pat
i
o
n
o
f
t
h
e r
e
duce
d
c
o
m
p
o
n
en
ts is th
eo
retically calcu
lat
e
d
.
Th
is is
do
ne wit
h
the ass
u
m
ption that t
h
e
forward volta
ge dr
o
p
s of
al
l
di
o
d
es
are 0.
5 V.
1
2
(1
)
∆
/
(2
)
In t
h
is case
when the
propos
ed
ga
te sign
als are ap
p
lied
to th
e co
nv
erte
r,
one diode of a
rectifier,
i
n
cl
udi
ng
t
h
e i
n
t
r
i
n
si
c
b
ody
di
o
d
e, i
s
om
i
tted i
n
a s
w
i
t
c
hi
ng
pe
ri
o
d
.
So
,
t
h
e ef
fi
ciency
im
provem
ent of t
h
e
p
r
op
o
s
ed
con
v
erter is
ob
tain
ed
.
2.
3. Freque
nc
y Resp
onse
A
n
al
ysi
s
Th
e
p
o
wer stag
e sp
ecification
s
of th
e
b
r
i
d
geless
SEPIC
P
F
C
con
v
e
r
t
e
r a
r
e desi
gne
d
wi
t
h
fol
l
owi
n
g
po
we
r st
age
p
a
ram
e
t
e
rs l
i
k
e In
put
vol
t
a
ge
, O
u
t
p
ut
v
o
l
t
a
ge,
Out
put
po
wer
,
Swi
t
c
hi
n
g
f
r
eq
ue
ncy
,
Po
wer
Factor.
According t
o
t
h
e
desi
gn s
p
eci
fication
param
e
ters, t
h
e state
vectors
fo
r bo
th switch
i
ng
i
n
terv
als (in th
e
equat
i
o
n
3 &
4) a
n
d a q
u
asi
-
st
at
e assum
p
t
i
on
, f
o
l
l
o
wi
n
g
t
h
e n
u
m
e
ri
cal
exp
r
essi
on
of t
h
e cont
rol
-
t
o
-i
n
duct
o
r
cu
rren
t t
r
an
sfer fu
n
c
tion
is
ob
tain
ed
assu
m
i
n
g
an
inpu
t vo
lt
ag
e.
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
/0
(3
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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S
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:
208
8-8
6
9
4
C
l
osed Lo
o
p
A
nal
ysi
s
of
Bri
d
g
el
ess SEP
I
C
C
onvert
e
r
f
o
r Dri
ve
A
ppl
i
c
at
i
o
n
(
M
. G
opi
na
t
h
)
25
5
B1
0
0
(4
)
3
2
3.96
4
3
2
1
3.49
(5
)
1
/
1
1
(6
)
Fi
gu
re
2 s
h
ow
s t
h
e
fre
q
u
enc
y
resp
o
n
se
of
t
h
e de
ri
ve
d c
o
nt
r
o
l
-
t
o
-i
n
duct
o
r
m
odel
.
As
t
h
ere a
r
e
2
reso
na
nce l
o
ca
t
i
ons, a
n
d o
n
e
am
ong
t
h
em
has very
hi
g
h
Q
-fact
o
r
.
I
n
ad
di
t
i
on,
fr
om
t
h
e st
at
e-
m
a
t
r
i
x
an
d t
h
e
trans
f
er function with
the
c
h
aracteriz
ed
param
e
ters, th
e lo
catio
n
s
o
f
reson
a
n
ce po
i
n
ts are
d
e
termin
ed
as
sho
w
n i
n
e
qua
t
i
on-
6.
T
hose
l
o
cat
i
o
n
s
a
r
e re
l
a
t
e
d t
o
t
h
e m
a
i
n
pa
ssi
ve
co
m
ponent
s a
n
d
t
h
e d
u
t
y
cy
cl
e t
h
a
t
p
r
esen
ts t
h
e rel
a
tio
n
b
e
tween
t
h
e inpu
t vo
ltage and
th
e ou
t
p
ut v
o
ltag
e
.
Fig
u
r
e
2
.
Fr
equ
e
n
c
y
r
e
sp
on
se of
inpu
t vo
ltage
3.
SIMULATION ANALYSIS
The pe
rf
o
r
m
a
nce of t
h
e
pr
op
ose
d
m
odel
e
d i
s
eval
uat
e
d
U
s
i
ng M
a
t
l
a
b-
Si
m
u
li
nk en
vi
r
o
nm
ent
,
and i
t
is ex
ten
d
e
d
to
d
r
i
v
e app
licatio
n
s
. Th
e sim
u
latio
n
of br
idg
e
less SEPIC con
v
e
rter is shown
in
Figu
re
3, wh
ich
gi
ves a l
o
w c
o
nd
uct
i
o
n l
o
ss a
nd s
w
i
t
c
hi
n
g
l
o
ss
du
ri
n
g
swi
t
ch t
u
r
n
o
n
a
n
d t
u
r
n
of
f co
n
d
i
t
i
on. Fi
g
u
r
e
4
sho
w
s
t
h
e i
n
put
vol
t
a
ge a
nd c
u
rre
nt
wave
f
o
rm
. Thi
s
ci
rcui
t
al
so
u
s
ed t
o
i
m
prove
p
o
we
r fact
or
du
ri
n
g
c
o
n
v
e
r
s
i
on
o
f
ac-dc
. Here t
h
ree i
d
ent
i
cal
i
nduct
o
rs ar
e us
ed t
o
red
u
ce t
h
e ri
p
p
l
e
cur
r
e
n
t
.
The o
u
t
p
ut
vol
t
a
ge m
easures
5
9
vol
t
s
a
n
d c
u
r
r
e
n
t
m
easures
1.
4 am
ps f
r
om
t
h
e Fi
g
u
re
5
Evaluation Warning : The document was created with Spire.PDF for Python.
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:
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S
Vo
l. 6,
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.
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ne 20
15
:
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–
2
59
25
6
Fi
gu
re
3.
Si
m
u
l
a
t
i
on o
f
Pr
op
o
s
ed C
i
rc
ui
t
Figure
4. Meas
ure
d
Input Vol
t
age and C
u
rre
n
t
Fi
gu
re 5.
O/
P
Vol
t
a
ge=
5
9
v,
C
u
r
r
e
n
t
=
1.
4 A
Fi
gu
re
6 de
pi
c
t
s t
h
e cl
ose
d
l
o
o
p
si
m
u
l
a
t
i
on ci
rc
ui
t
usi
n
g
PI c
ont
rol
l
e
r,
whe
r
e i
n
p
u
t
si
de v
o
l
t
a
g
e
disturba
nces a
r
e c
r
eated at
a
speci
fi
ed
time. Dur
i
ng
o
p
e
n
loop
system ou
tpu
t
v
o
ltage of
o
p
e
n loop
w
i
t
h
d
i
stu
r
b
a
n
ce
remain
s con
s
tan
t
till th
e ti
m
e
o
f
d
i
sturb
a
n
ce
g
i
v
e
n b
y
PI con
t
ro
ller.
Fig
u
r
e
6
.
Clo
s
ed
loop
A
n
alysi
s
of
Pr
opo
sed
Co
nv
er
ter
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8-8
6
9
4
C
l
osed Lo
o
p
A
nal
ysi
s
of
Bri
d
g
el
ess SEP
I
C
C
onvert
e
r
f
o
r Dri
ve
A
ppl
i
c
at
i
o
n
(
M
. G
opi
na
t
h
)
25
7
The i
n
put
v
o
l
t
a
ge di
st
u
r
ba
nc
e i
s
done
usi
n
g PI co
nt
r
o
l
l
e
r
and i
t
get
s
ref
l
ect
ed i
n
t
h
e o
u
t
p
ut
si
de, l
eadi
n
g t
o
redu
ction
in
the o
u
t
p
u
t
vo
ltag
e
.
During
th
i
s
ti
m
e
th
e clo
s
ed
loo
p
PI ci
rcu
it with
PWM co
n
t
ro
ller
help
s in
reducing t
h
e
overs
h
oot ca
use
d
due
t
o
o
p
en
l
o
o
p
.
The
out
put
vol
t
a
ge i
s
co
nt
i
n
u
ousl
y
c
o
m
p
ared wi
t
h
a re
fere
nce v
o
l
t
a
ge
usi
ng a
di
f
f
ere
n
t
i
al
am
pl
i
f
i
e
r.
The di
ffe
rent
i
a
l
si
gnal
i
s
am
pli
f
i
e
d an
d f
e
d t
o
com
p
ara
t
or. T
h
e com
p
arat
or
o
u
t
p
ut
i
s
fed t
o
o
n
e of t
h
e
M
O
SFET s
w
i
t
c
hes. A
n
ot
he
r t
r
i
a
ng
ul
ar wa
v
e
i
s
phase shi
f
t
e
d
b
y
18
0º is co
m
p
ared
with
th
e sam
e
d
i
fferen
tial
am
pl
i
f
i
e
r o
u
t
p
ut
an
d t
h
e o
u
t
put
of
t
h
e sec
o
nd
com
p
arat
o
r
i
s
fed
t
o
t
h
e
o
t
her M
O
SFE
T.
Th
us c
h
a
nges
i
n
t
h
e
o
u
t
p
u
t
vo
ltag
e
are reflected
i
n
th
e
d
i
fferen
tial a
m
p
lifier ou
t
put
a
n
d i
n
t
u
rn
i
n
t
h
e
com
p
ar
at
or
o
u
t
p
ut
. Fi
gu
re
7
gi
ves t
h
e
o
u
t
p
ut
DC
v
o
l
t
a
ge
of t
h
e cl
osed l
o
o
p
ci
rc
ui
t
.
Fi
gu
re 8 s
h
ows t
h
e st
ep c
h
an
ge
i
n
t
h
e t
o
r
que
at
1 sec
and from
Figure 9, the
spee
d a
ttains its steady state in
stantly after the
step cha
nge
in t
h
e l
o
ad torque.
Fr
o
m
Fig
u
r
e
10
, th
e
THD
main
s cur
r
e
n
t
of th
e pr
opo
sed
PFC SEPI
C co
nv
er
ter
f
e
d
DC d
r
iv
e is
o
b
s
erv
e
d und
er 5
%
, wh
ich
is t
h
e
requ
irem
en
t of
p
o
wer qu
ality.
Fi
gu
re 7.
DC
Out
put
V
o
l
t
a
g
e
Fi
gu
re
8.
C
h
a
n
ge i
n
l
o
a
d
t
o
r
q
ue at
t
i
m
e t
=
1 sec
Fi
gu
re
9.
S
p
ee
d
resp
o
n
se
of
c
l
ose l
o
o
p
sy
st
e
m
Fi
gu
re 1
0
.
T
H
D Val
u
e o
f
P
r
o
pos
ed
C
o
nve
rt
er
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94
I
J
PED
S
Vo
l. 6,
No
.
2,
Ju
ne 20
15
:
253
–
2
59
25
8
4.
E
X
PERI
MEN
T
AL A
N
A
LY
SIS O
F
SEPI
C
CO
NVE
RT
ER
Fi
gu
re 1
1
sh
o
w
s t
h
e ha
rd
wa
re b
o
ar
d wi
t
h
t
op si
de fo
r m
a
in swi
t
c
hes a
n
d
bot
t
o
m
si
de fo
r co
nt
rol
l
e
r
.
Th
e
o
u
t
p
u
t
v
o
l
tag
e
is regu
lat
e
d
and
th
e i
n
pu
t curren
t
track
s
th
e i
n
pu
t voltag
e
. Un
d
e
r full-lo
ad
co
nd
itio
n, th
e
po
we
r fact
o
r
a
nd t
h
e ha
rm
oni
c di
st
ort
i
o
n re
sul
t
can be a
n
a
l
y
zed fr
om
Fi
gure
12
. Ha
rm
oni
c com
pone
nt
s are
sho
w
n i
n
Ta
bl
e 1. T
h
e m
a
jor
ob
ject
i
v
e
of the analysis is to com
p
ensate
t
h
e po
wer
st
age
wi
t
h
p
r
o
p
e
r
da
m
p
i
ng
and
to ens
u
re the
stable
op
eratio
n
o
f
conv
erter. B
r
idg
e
less SEPI
C PFC
to
po
log
i
es can fu
rth
e
r im
p
r
ov
e th
e
conve
r
sion efficiency. To
main
tain
sam
e
efficien
cy, th
e im
p
r
o
v
e
d
circuits could operate
with highe
r
sw
itch
i
ng
f
r
e
qu
en
cy.
Fig
u
r
e
11
. H
a
rd
w
a
r
e
o
f
Pr
opo
sed
Conv
er
ter
Fig
u
r
e
12
.
I
npu
t A
C
and
ou
tpu
t
D
C
sign
als
o
f
pr
o
pose
d
c
o
nv
ert
e
r
Tabl
e 1. Harm
oni
c
c
o
m
pon
en
t
s
Fundam
e
ntal
3 5
7 9
1.
448A
0.
067A
0.
097A
0.
044A
0.
009A
5.
CO
NCL
USI
O
N
In order to
improve the efficiency
, bridg
e
less SEPIC
converter
has been proposed. Performance of
the proposed
SEPIC PFC rectifier is carr
i
ed o
u
t using Matlab
Simulink so
ftware. Th
e frequen
c
y
r
e
sponse of the derived con
t
r
o
l-to-
inductor model is analy
zed for
th
e proposed
conv
erter
.
In our analy
s
is Bridgeless
SEPIC PFC rectifier suffers a step input
voltag
e
ch
ange
and th
ereb
y
it
at
tains
th
e s
t
ead
y
s
t
ate
.
Bes
i
d
e
s
in
im
proving th
e
c
i
rcuit
topo
log
y
t
h
e perform
an
ce
can b
e
further r
e
duc
e in
rec
tifi
e
r s
i
ze
co
uld be
re
ali
zed b
y
int
e
grat
ing th
e
thre
e indu
ctors
.
The s
i
m
u
la
tion r
e
s
u
lts
ar
e pr
es
en
ted
to
verif
y
the
contr
o
ller design
. Th
e experiment
r
e
sults indic
a
te th
at
the harm
onic c
ontents are we
ll
below the lim
it
s. It is
verified that a well-d
e
signed damping circ
uit reduces the high risk of
sy
stem inst
abili
t
y
. Sim
u
lati
on and hardware
results
show high perfo
rmance in
terms of high pow
er f
a
ctor
and
efficien
cy
.
REFERE
NC
ES
[1]
G
a
rcia
, O
., Cob
o
s
,
J
.
A
.
,
P
r
ie
to
R., A
l
ou
P
.
, U
c
e
d
a,
J
.
,
“
S
ingle P
h
as
e P
o
wer F
a
ct
or Correc
tion
:
A S
u
rve
y
”,
IE
EE
Transactions on
Power Electronics
, vol. 18
, no
. 3
,
pp
. 749-755
, M
a
y
2003.
[2]
Lazaro A., B
a
rr
ado A., Sanz
M., Sa
las V.,
Olias E., “New Power Factor
Correction AC-
D
C Converter
with
Reduced S
t
orag
e
Capaci
tor Volta
ge”,
I
EEE Transactions on Industrial Ele
c
troni
cs
, vol. 54, no. 1, p
p
.384-397, Feb.
2007.
[3]
Liang T.J., Yang
L.S., Ch
en J.F.,
“A
naly
sis and d
e
sign of a si
ngle-phase AC/DC step-down conver
t
er for univers
al
input voltag
e
”,
I
E
T Electric
Pow
e
r Applications
,
vol. 1
,
no
. 5
,
pp
.
778-784, Sept. 2
007.
[4]
B. Su and Z. Lu, “An interleaved totem-pole boost bridgele
ss rectifier with redu
ced reverse-r
eco
ver
y
problems f
o
r
power fa
ctor
cor
r
ect
ion”,
IE
EE
T
r
ans. Power
Ele
c
tron
., vol. 25
, n
o
. 6
,
pp
. 1406-1
415, Jun. 2010.
[5]
H.
Y.
Tsai,
T.
H.
Hsia,
and D.
Chen,
“A family
of zero-
voltage-transition bridgeless powe
r-factor-correction circu
i
ts
with a
z
e
ro-curr
e
nt-switch
i
ng au
xiliar
y
switch
”
,
IEEE Trans. Ind
.
Electron
., vol. 58, no
. 5
,
pp
.
1848-1855, May
2011.
[6]
J
.
P
.
R. Bal
e
s
t
ero
,
F
.
L. Tofo
li
, R.C. F
e
rnand
e
s
,
G.V. Torrico-
B
as
cope,
and F
.
J
.
M
.
de S
e
ix
as
, “
P
ower factor
correction boost converter b
a
sed
on
the three-state switching cell”,
IEEE Trans. Ind. Electron
., vol. 59, no. 3, pp
.
1565-1577, Mar
.
2012.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
C
l
osed Lo
o
p
A
nal
ysi
s
of
Bri
d
g
el
ess SEP
I
C
C
onvert
e
r
f
o
r Dri
ve
A
ppl
i
c
at
i
o
n
(
M
. G
opi
na
t
h
)
25
9
[7]
L. Huber, Y. J
a
ng, “
P
erform
ance of eval
uation f
o
r bridgeless PFC buck rectif
ier
”
,
IEEE Trans.
Power Electron
.,
vol. 23
, no
. 3
,
pp
. 1381
, May
200
8.
[8]
W. Wei, L. Hon
gpeng, J.
Ahigo
ng, and X. Iang
uo, “
A novel bridgeless buck-bo
ost PFC con
verter
”, in
P
r
oc. I
E
EE
Power Electron
.
Spec. Conf
., 200
8, pp
. 1304-130
8.
[9]
W. Wei, L. Hongpeng, J.
Shigong, and X. Dianguo, “
A novel bridgeless buck-bo
ost PFC converter
”
,
i
n
Proc
.
IE
EE
Power Electron
.
Spec. Conf
., 200
8, pp
. 1304-130
.
[10]
E.H.
Ism
a
il,
“
B
ridgeless SEPIC r
ect
ifier
with
unity
power f
actor
and reduced
cond
uction
loss
[11]
D.S.L. Simonetti, J. Se
b
a
stian
,
and J. Uced
a, “
T
he discon
tinuo
us
conduction
mode Sepic and
Cuk power factor
preregulators: Anal
y
s
is and
design”,
I
E
EE Trans. Ind
.
Electron
.,
vol. 44
, no
. 5
,
pp
. 630-637
, Oct. 1
997.
[12]
D.
M.
Mitc
he
ll, “
AC-DC Converter having
an
improved power
factor
”, U.S. Patent
4,
412,277
, Oct.
25, 1983
.
[13]
Younghoon Cho, “A Low Cost Single-Switch
Br
idgeless Boost PFC Converter”, in
International
Journal of Powe
r
Electronics and
Drive System
. V
o
l. 4
,
No
. 2
,
Jun
e
2014.
[14]
Laxmi Devi Sahu, Saty
a Prakash
Dubey
,
“ANN b
a
sed H
y
brid Active Power Filte
r
for Harmonics
Elimination with
Distorted Mains
”
, in
Internation
a
l Journal of Po
we
r Electronics
and Drive System
, Vol. 2, No. 3, September 2012,
pp. 241~248.
BIBLIOGRAPHIES
OF AUTHO
R
S
GOPINATH M
ANI
has obtained his B.E degree from Bharat
hiar
Universit
y
, Coi
m
batore in the
y
e
ar 2002. He o
b
tain
ed his M-Tech degr
ee from Ve
llore Institute of Technolog
y; Vellore
in th
e
y
e
ar 2004
. He
obtain
e
d is Doctorate from Bharat
h University
, Chennai. He is
working as a
P
r
ofessor/EEE,
at Dr.N.G.P
Inst
itute of
Techno
l
o
g
y
, Coim
batore
, India
.
His Area of inter
e
st is
P
o
wer Electron
i
cs
. He is
profes
s
i
onal m
e
m
b
er
of IEEE, ISTE, IETE, IAENG, an
d IACSIT. He
has
rec
e
iv
ed b
e
s
t
perform
er
awar
d in
the
year
201
0.
G. GO
PU
has o
b
tain
ed his B.E
degree from Annamalai Univ
ersity
,
Ch
i
d
a
m
b
a
ra
m
in the
year
1996. He obtain
e
d his Master d
e
gree
in Biomed
ical
Signal Processing and In
stru
mentation
in
the
y
e
ar 2002 fro
m SASTRA University
, Than
javur
and comp
leted his Ph.D in Biomedical
Engineering at
P.S.G College o
f
Techno
log
y
, C
o
imbatore under
Anna Univ
ersity
, Chennai. At
present h
e
is wo
rking as
a Professor and Head
/Biomedical,
at
Sri Ramakrishna Engg Co
lleg
e
,
Coim
batore, Ind
i
a. His Area of
inter
e
st is Medi
cal Ins
t
rum
e
nt
at
ion, P
o
wer Electronics.
He is
professional member of IEEE, I
S
TE, BMESI
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