Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
Vol
.
5
,
No
. 2, Oct
o
ber
2
0
1
4
,
pp
. 23
7~
24
3
I
S
SN
: 208
8-8
6
9
4
2
37
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Modelling of Variable Frequenc
y Synchronous Buck Converter
Jeya Selvan Renius
A, Vinoth
Kum
a
r
K,
Arn
o
ld Fre
d
derics, Raja
Guru, Sree
Laks
hmi Nair
Departement of
EEE, School of
Electri
cal Sciences, Karun
y
a University
, Co
imbatore – 64111
4, Tamil Nadu
, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
J
u
l 11, 2014
Rev
i
sed
Sep 9, 20
14
Accepted
Sep 25, 2014
In this paper
,
novel small-sig
n
al av
eraged m
odels for dc–d
c conver
t
er
operating at var
i
able switc
hing
frequency
are d
e
rived
.
This is achieved
b
y
separately
considering th
e on-
time and the off-time
of the switching period.
The deriv
a
tion is shown
in detail for a s
y
nchro
nous buck converter
. Th
e
Enhanced Small Signal (ESSA)
Model
is derived for the s
y
nchr
onous buck
converter. The equivalent
se
ries inductance (ESL)
is
al
so consid
ered in th
is
modelling. Th
e buck converter model is
also si
mulated in MATLAB and th
e
result
is also
pre
s
ented.
Keyword:
D
C
-D
C conv
erter
,
En
hance
d
Sm
al
l
Si
gnal
Analy
s
is (ESS
A),
Equivalent Series
Inductance
(ESL
)
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Jey
a
Sel
v
a
n
R
e
ni
us
A,
Depa
rt
em
ent
of EEE
, Sc
h
ool
of Electrical Sciences,
Karun
y
a Un
iv
ersity,
Co
im
b
a
to
r
e
–
6
411
14
, Tam
il
N
a
du
, Ind
i
a.
Em
a
il: ren
i
u
s
28
@g
m
a
il.co
m
1.
INTRODUCTION
In t
h
e co
nt
r
o
l
of
dc
–dc c
o
nv
ert
e
rs, t
w
o c
o
n
t
rol
o
b
j
ectives
are appare
nt: perform
a
nce and efficiency.
On
t
h
e on
e
h
a
n
d
, th
e
research
fo
cu
s in
t
h
e
co
mm
u
n
ity h
a
s b
e
en
pu
t on
th
e op
timizatio
n
of th
e con
v
e
rsion
effi
ci
ency
.
F
o
r
i
n
st
ance
, t
h
e s
w
i
t
c
hi
n
g
fre
q
u
e
ncy
ca
n
be
re
duce
d
at
l
o
w l
o
ad
s,
o
r
t
h
e
c
o
nt
r
o
l
sc
hem
e
coul
d
be
swi
t
c
he
d bet
w
een a co
nst
a
n
t
on
-t
im
e and
a const
a
nt
o
f
f
-
t
i
m
e
cont
r
o
l
schem
e
dependi
ng
o
n
t
h
e
l
o
ad
co
nd
itio
ns.
On
th
e o
t
h
e
r h
a
nd
, a stro
ng
i
n
terest can
b
e
foun
d in
th
e op
tim
iz
atio
n
o
f
th
e
d
y
n
a
m
i
c p
e
rforman
ce.
Wh
en
a v
a
riatio
n
of th
e swi
t
ch
in
g p
e
riod
is to
le
rab
l
e during
co
nv
erter op
eration
,
th
i
s
add
itio
n
a
l
deg
r
ee o
f
fr
ee
dom
offe
rs t
h
e
op
po
rt
u
n
i
t
y
of t
i
ght
(n
ear o
p
t
i
m
u
m
)
vol
t
a
ge re
gul
at
i
o
n.
Neve
rt
hel
e
ss
, t
o
f
u
l
l
y
expl
oit the swi
t
ching
peri
od
m
odulation
in
term
s of dyna
m
i
c transient perf
orm
a
nce and to ens
u
re stability in
all conditions,
accurate m
o
dels, which c
o
ver the
dynam
i
cs of t
h
e
power conversi
on
system
unde
r
varia
b
le
fre
que
ncy ope
r
ation, are
ne
eded. A
fre
quency
-selectiv
e av
erag
ing
is ap
p
lied
su
ch
th
at th
e switch
i
n
g
fre
que
ncy appears in the
dynam
i
c s
y
ste
m
m
odel. The de
rivations gi
ve an accurate
model
of the c
o
nve
rte
r
d
y
n
a
m
i
cs also
for situatio
n
s
wh
en th
e t
r
ad
itio
n
a
l sm
all-ripp
le cond
itio
n
s
are
n
o
t
sat
i
sfied
,
bu
t yield
a
no
nl
i
n
ea
r t
i
m
e
-va
r
y
i
ng sy
st
e
m
form
ul
at
i
on. As p
r
e
v
i
o
us
cl
assi
c cont
r
o
l
t
h
eo
ri
es l
a
rgel
y
de
pen
d
on
a
linearized representation of
t
h
e
system
u
n
d
er ex
am
, th
e resu
ltin
g
m
o
d
e
l is o
f
lim
i
t
ed
in
terest fo
r th
e targ
eted
d
e
sign
ob
j
ective.
In
th
is p
a
p
e
r, an
altern
ativ
e
form
u
l
atio
n
o
f
th
e SSA m
o
d
e
l is p
r
esen
ted, wh
ich
yield
s
a lin
earized
sm
a
ll-sig
n
a
l rep
r
esen
tatio
n of th
e
p
o
wer conv
ersi
o
n
circu
it, where t
h
e
on-tim
e, as well as the
off-tim
e
of t
h
e
pul
se
-wi
d
t
h
m
o
d
u
l
a
t
i
on
(P
W
M
) si
gnal
a
r
e t
r
eat
ed as
di
st
i
n
ct
cont
r
o
l
i
n
put
s. I
n
t
h
i
s
m
a
nn
er,
one ca
n st
u
d
y
t
h
e
dynam
i
cs
under variable
s
w
itching fre
quency operat
io
n.
Th
e
co
rr
ec
tn
e
s
s
o
f
th
e e
n
h
a
n
c
ed
con
v
e
r
t
e
r
rep
r
ese
n
t
a
t
i
on
i
s
al
so
di
scus
se
d i
n
t
h
i
s
pa
per.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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-86
94
I
J
PED
S
Vo
l.
5
,
No
.
2
,
O
c
t
o
b
e
r 201
4 :
2
37 –
24
3
23
8
2.
CONVE
RTER MODELLING
In
t
h
is sectio
n, a sm
a
ll-sig
n
a
l
av
erag
ed
and
lin
ear
ized
m
o
del will b
e
d
e
riv
e
d, in
wh
ich
th
e on
-tim
e
ˆ
t
on
an
d th
e of
f-
ti
m
e
ˆ
t
o
f
f
of
th
e PW
M si
g
n
a
l
dr
iv
ing th
e
po
w
e
r
stage
o
f
th
e
d
c
–d
c
co
nv
er
ter
appear
as
ad
d
ition
a
l in
puts to
th
e system
. Th
is is
in
co
n
t
rast to
th
e
co
nv
en
tio
n
a
l SSA m
o
d
e
l, where th
e sm
al
l-sig
n
a
l
dut
y
cy
cl
e dˆ i
s
t
h
e o
n
l
y
co
nt
rol
vari
abl
e
. T
h
e o
n
-
t
i
m
e
i
s
defi
ne
d as t
h
e t
i
m
e peri
o
d
d
u
ri
ng
w
h
i
c
h t
h
e
b
i
nary
P
W
M
si
gnal
i
s
“H”, a
n
d t
h
e
of
f-t
i
m
e i
s
defi
ned
as t
h
e
pe
ri
od
o
f
t
i
m
e dur
i
ng
w
h
i
c
h t
h
e
P
W
M
si
gnal
i
s
“L”.
Acco
r
d
i
n
gl
y
,
for a sy
nc
hr
o
n
o
u
s b
u
c
k
co
nve
rt
er i
n
co
nt
i
n
u
ous c
o
nd
uct
i
o
n m
ode (C
C
M
), d
u
ri
ng t
h
e
o
n
-t
i
m
e
t
h
e hi
g
h
-
si
de s
w
i
t
c
h S
1
i
s
co
nd
uct
i
n
g a
nd t
h
e l
o
w-si
de s
w
i
t
c
h S
2
i
s
o
p
e
n.
Whe
r
eas
d
u
ri
ng t
h
e o
f
f
-
t
i
m
e, t
h
e
hi
g
h
-si
d
e swi
t
c
h S1 i
s
ope
n
and t
h
e l
o
w-si
de swi
t
c
h S
2
i
s
con
duct
i
n
g.
Sim
i
l
a
r consi
d
erat
i
ons are
va
l
i
d
for a
b
o
o
s
t co
nv
erter. Th
e relation b
e
tween
d
u
t
y
cycle, o
n
-ti
m
e, o
f
f-tim
e, an
d
switch
i
ng
p
e
ri
o
d
i
n
equ
ilib
ri
u
m
i
s
gi
ve
n by
:
D =
T_on
/
T_sw
=
T_on
/(
T_on
+ T
_off
)
(1)
D
'
=
(
1
-
D
)
(
2
)
Thus, a
va
riation of the
duty
cycle corre
sponds
to
a v
a
riatio
n of th
e on-time
of the
s
w
itching cycle,
wh
en
th
e switch
i
ng
p
e
riod
Tsw is assu
m
e
d
to
b
e
co
nstan
t: d
(
t) = t
o
n(t) / Tsw .
Wh
en
, add
itio
n
a
lly, a v
a
riatio
n
o
f
th
e switch
i
ng
p
e
ri
o
d
Tsw i
s
allo
wed
,
th
e
fo
llo
wi
n
g
equ
a
t
i
o
n
is read
ily ob
tain
ed
:
d(t
)
=
(
T_on
(t)/
T_sw
(t)) =
(
T_on
(t)/
T_on
(t)+
T_(off
(t
) )
The state-s
p
ac
e m
odels, as c
o
nside
r
ed in t
h
is
study, are
de
fi
ned as:
dx
(t)
)
/dt
=
A
x
(
t
)
+
Bu
(t)
(3
)
y
(
t)
=
C
x
(t
)
+
Du
(t)
(4
)
Thi
s
i
s
t
h
e
basi
c sm
all
si
gnal
equat
i
o
n
f
o
r t
h
e sy
nc
hr
on
o
u
s
buc
k c
o
nve
rt
er
.
3.
ENHA
N
C
ED
SM
ALL
SIG
NAL M
O
DEL
L
ING OF SY
NC
HR
ON
OU
S
BU
CK CO
NVE
RTER
Fi
gu
re
1.
B
u
c
k
co
nve
rt
er m
o
d
e
l
From
the above circuit two mode
s of operati
on a
r
e
possi
ble (i.e)
whe
n
the
switch is ON s
t
ate and the
switch is i
n
OFF state. T
h
e sta
t
e varia
b
les are
give
n a
s
:
X =
The i
n
p
u
t
vari
a
b
l
e
s are
gi
ven
as U.
T
h
ey
are
gi
ve
n
bel
o
w.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
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208
8-8
6
9
4
Modelling
of V
a
riable Fre
q
ue
ncy
Sync
hr
onou
s B
u
ck C
o
nve
r
ter (Jeya
Selvan Re
nius
A)
23
9
U =
The
o
u
t
p
ut
va
r
i
abl
e
i
s
gi
ven
a
s
:
Y =
[
]
3.
1. MO
DE
1
Wh
en
t
h
e switch
S1
is i
n
ON state and
th
e switch
S2
is i
n
OFF state, the
circuit equations acc
ordi
ng
to
Ki
rcho
ff’s
vo
ltag
e
law is
g
i
v
e
n as:
L
=
-
+
(
5
)
C
= -
(
6
)
=
-
-
(
7
)
B
y
appl
y
i
n
g
t
h
e ab
ove
eq
uat
i
ons
t
o
t
h
e sm
all
si
gnal
a
n
al
y
s
i
s
m
odel
eq
uat
i
ons
,
we
get
:
=
00
0
+[
]
(
8
)
Y =
[
]
+ [
o
o
o]
(
9
)
These a
b
ove
e
quat
i
o
ns
are
si
m
i
l
a
r t
o
t
h
e
ba
si
c sm
al
l
si
gna
l
equat
i
o
ns
. T
h
us
fr
om
t
h
e ab
ove
eq
uat
i
o
ns,
=
00
0
= [
]
= [
]
= [o
o
o]
Th
us t
h
e
f
o
ur
m
a
t
r
i
ces are de
ri
ve
d f
r
o
m
m
o
de
1.
Si
m
i
l
a
r cal
cul
a
t
i
ons a
r
e
m
a
de i
n
m
ode
2 al
s
o
.
3.
2. MO
DE
2
Wh
en
t
h
e switch
S2
is i
n
ON state and
th
e switch
S1
is i
n
OFF state, the
circuit equations acc
ordi
ng
to
Ki
rcho
ff’s
vo
ltag
e
law is
g
i
v
e
n as:
L
=
-
(
1
0
)
C
= -
(
1
1
)
=
-
-
(
1
2
)
Sim
i
l
a
r t
o
ab
o
v
e m
ode, i
n
t
h
i
s
m
ode al
so
we
f
o
rm
t
h
e m
a
t
r
ix e
quat
i
o
n a
s
g
i
ven
bel
o
w:
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l.
5
,
No
.
2
,
O
c
t
o
b
e
r 201
4 :
2
37 –
24
3
24
0
=
00
0
+[
000
]
(
1
3
)
Y =
[
]
+ [
o
o
o]
(
1
4
)
Thus
from
the above e
q
uations we
can
also
get th
e fo
llowing
m
a
trices,
=
00
0
= [
000
]
= [
0
]
= [0
0
0]
Co
n
s
i
d
eri
n
g
small p
e
rtu
r
b
a
tio
n
s
aro
und
th
e eq
u
ilibriu
m
p
o
i
n
t
, th
e states
x
, inpu
t sign
als
u
, an
d t
h
e c
ont
ro
l
vari
a
b
l
e
s
t
on
and
t
off
are
gi
ven
by
,
x =
X +
x
̂
,u =
U +
û
t
on
=
T
on
+
t
ôn
,
t
off
=
T
off
+
t
̂
off
Acco
r
d
i
n
gl
y
,
t
h
e st
at
e e
quat
i
on
i
s
gi
ve
n
by
,
̂
= ((
-
)
on
ôn
on
o
̂
n
off
̂
off
+
) (
X
+
x
̂
) +
(
(
-
)
on
ôn
on
o
̂
n
off
̂
off
+
) (
U
+
û
)
(1
5)
An
d t
h
e
out
put
eq
uat
i
o
n
i
s
,
Y+
ŷ
= ((
-
)
on
ôn
on
o
̂
n
off
̂
off
+
) (X
+
x
̂
) +
((
-
)
on
ôn
on
o
̂
n
off
̂
off
+
) (U + û
)
(1
6)
Co
llectin
g
th
e
d
i
rect-cu
r
ren
t
(d
c) term
s an
d
acco
rd
ing
t
o
th
e con
d
ition
o
f
the equ
ilib
riu
m
,
0=
A
x
(
t
) + Bu(
t
)
y
(
t
)
= C
x
(
t
) +
D
u
(
t
)
Whe
r
e t
h
e a
v
eraged m
a
trices are
give
n
by,
A =
D
+ D'
B
̃
= D
+ D'
C = D
+ D'
D
̃
=
D
+ D'
After
calcu
latio
n, we g
e
t:
A =
00
0
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I
J
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S
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208
8-8
6
9
4
Modelling
of V
a
riable Fre
q
ue
ncy
Sync
hr
onou
s B
u
ck C
o
nve
r
ter (Jeya
Selvan Re
nius
A)
24
1
B
̃
= [
]
C = [
]
D
̃
=
[o
o
o]
To calc
u
late B
and D,
we
use
t
h
e p
r
oced
ure
as gi
ven
bel
o
w
,
B = [
B
]
D
=
[
D
]
&
and
&
can
be calculated
from
the fo
rm
ula belo
w,
= (
X +
U)
/
(
)
= (
X +
U)
/
(
)
(
1
7
)
An
d,
= (
X +
U
−
Y)
/
(
)
= (
X +
U
−
Y)
/
(
)
(
1
8
)
Th
us a
f
t
e
r cal
c
u
l
a
t
i
ons
we
get
t
h
e
val
u
e
o
f
B
& D
m
a
t
r
i
ces as gi
ven
bel
o
w
,
=
0
D′
0
=
0
D
0
=
=
0
B
=
00
0
D′
D
00
0
D
=
0
By sp
littin
g
th
e switch
i
ng
p
e
riod
of th
e PWM sig
n
a
l in
to
t
h
e on
-tim
e an
d
th
e o
f
f-tim
e o
f
th
e p
e
riod
,
the input
vector size is
m
+
2, com
p
ared t
o
m
+
1
in
case
o
f
t
h
e trad
itio
nal SSA app
r
o
a
ch
(wh
e
re so
lely th
e
dut
y
cy
cl
e i
s
adde
d as co
nt
r
o
l
i
nput
)
.
Ne
ver
t
hel
e
ss, t
h
e i
n
p
u
t
com
pone
nt
s
(
t
on a
nd
t
o
f
f
)
do
not
ind
e
p
e
nd
en
tly
affect the state
v
ector. Th
is is
in
tu
itiv
ely clear an
d reflected
in
th
e
resu
ltin
g m
o
d
e
ls, as:
ran
k
(
B
)
≤
(m
+ 1
)
i.e.,
B
d
o
es not
ha
ve ful
l
ra
n
k
.
4.
SIMULATION MODEL
Th
e
bu
ck conver
t
er
m
o
d
e
l si
m
u
la
ted
in
M
A
TLA
B is
g
i
v
e
n b
e
low
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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088
-86
94
I
J
PED
S
Vo
l.
5
,
No
.
2
,
O
c
t
o
b
e
r 201
4 :
2
37 –
24
3
24
2
Fi
gu
re
2.
Si
m
u
l
a
t
i
on di
a
g
ram
of
b
u
c
k
c
o
n
v
er
t
e
r i
n
M
A
TL
A
B
R
2
0
1
3
A
Thu
s
th
e bu
ck co
nv
erter m
o
d
e
l is si
m
u
late
d
in
MATLAB an
d
th
e
o
u
t
p
u
t
is similar t
o
th
at o
f
t
h
e
id
eal ou
tpu
t
. Th
e sim
u
lated
ou
tpu
t
is
p
r
esen
t
e
d
b
e
low.
5
.
SIMUL
A
TED OUTPUT
The si
m
u
l
a
t
e
d o
u
t
p
ut
s
h
o
w
s
t
h
at
a
2
0
0
0
V
i
n
p
u
t
DC
s
o
u
r
ce has
bee
n
b
u
cke
d
t
o
gi
ve
an
out
put
o
f
15
0
0
V
DC
o
u
t
put
.
T
h
e si
m
u
l
a
t
e
d o
u
t
p
ut
i
s
s
h
o
w
n
bel
o
w.
Fi
gu
re
3.
Si
m
u
l
a
t
e
d o
u
t
p
ut
of
t
h
e b
u
c
k
c
o
n
v
e
r
t
e
r
6.
CO
NCL
U
S
ION
In
th
is p
a
p
e
r, an
altern
ativ
e an
d
no
v
e
l
form
u
l
a
tio
n
of the lin
earized
small-sig
n
a
l
m
o
d
e
ls fo
r
d
c
–d
c
con
v
e
r
t
e
rs
has
bee
n
prese
n
t
e
d. T
h
e
de
ri
v
a
t
i
on
of t
h
e
d
y
n
am
i
c
m
odel
has
bee
n
s
h
ow
n i
n
d
e
t
a
i
l
fo
r a
syn
c
hr
ono
us bu
ck
co
nv
er
ter
.
Thu
s
th
e du
ty cycle is a
l
so adde
d as a co
nt
rol
i
n
put
t
o
t
h
e con
v
ert
e
r t
o
pol
ogy
d
i
scu
s
sed above. Th
u
s
th
e conv
er
ter can also
b
e
co
n
t
r
o
lled by u
s
ing
t
h
e
d
u
t
y cycle v
a
r
i
atio
n
s
.
REFERE
NC
ES
[1]
X Yu, B W
a
ng,
X Li. Com
pute
r-control
l
ed v
a
ri
able s
t
ru
ctur
e s
y
s
t
em
s
:
The s
t
at
e
of the
art
.
IEEE Trans. Ind. In
f.,
2012; 8(2): 197–
205.
[2]
L
Corra
di
ni,
A Cost
a
b
e
b
e
r
,
S Me
mbe
r
,
P Ma
t
t
a
vel
l
i
,
S Me
mb
e
r
,
S Sa
ggi
ni
.
Pa
ra
me
t
e
r-i
nde
pende
nt
t
i
m
e
-
optima
l
digital
control fo
r point-of-
load
converters.
IE
EE
T
r
ans.
Po
wer Electron.,
2009
; 2
4
(10): 2235–224
8
[3]
S Kapat. Improved time optim
al contro
l of
a
buck conver
t
er
based on capacitor curren
t
.
IEEE
Trans.
P
o
we
r
Electron.,
2012; 27(3):
1444–145
4.
[4]
AV Peterchev
,
S Sanders. Quan
tization
resolution and limit cy
c
ling in
digi
tally
controlled PWM conver
t
ers.
IEEE
Trans. Power Electron.,
2003
; 1
8
(1): 301–308.
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I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Modelling
of V
a
riable Fre
q
ue
ncy
Sync
hr
onou
s B
u
ck C
o
nve
r
ter (Jeya
Selvan Re
nius
A)
24
3
[5]
RW Erickson, D Maksimovic.
Fundamentals of
P
o
wer Electronics
, 2nd
ed.
New Y
o
rk, USA: Sprin
g
er-Verlag
,
200
1.
[6]
J Sun, D Mitchell, M Greuel. Averag
ed modeling
of PWM converters opera
ting in
discontinuous conduction mode.
IEEE
T
r
ans. Po
wer El
ectron
.
,
2
001; 16(4): 482–
492.
[7]
S Sanders, J No
worolski, X Liu. Generalized
av
eraging method for power conversion circuits
. IEEE T
r
ans. Power
Electron.,
1991; 6(2):
251–259.
[8]
V Caliskan, O Verghese, A St
an
kovic. Multifreq
u
ency
av
eraging
of dc/dc conv
erters.
IEEE Trans. Power Electron
.,
1999; 14(1): 124
–133.
[9]
Z Shen, N Yan
,
H Min. A m
u
ltim
ode dig
ital
l
y
contro
lle
d
b
oost convert
er
with pid
autotu
ning and
constant
frequency
/
constant off-
time h
y
b
r
id pwmcontrol.
IEEE
T
r
ans. Po
wer El
ectron
.
,
2
011; 26(9)
: 258
8–2598.
[10]
F Kuttner, H Habibovic, T Hartig, M Fu
lde, G
Babin, A Santne
r, P Bogner
,
C
Kropf, H
Riesslegger, U Hodel.
A
digitally controlled dc-dc converter for SoC in 28
nm CMOS.
P
r
oc
. IEEE Int
.
S
o
li
d-S
t
ate Cir
c
uits Conf. Dig. Te
ch
.
Papers, San
Fran
cisco, CA, USA. 2011: 384–385
.
BIOGRAP
HI
ES OF
AUTH
ORS
M
r
.
A.
Jey
a
Selvan Re
nius
received
his B
.
Tech. degr
ee
in
Electronics and
Co
mmunication
Engineering fro
m Anna University
, Tamilnadu
,
Indi
a. P
r
es
ent
l
y
h
e
is
purs
u
ing M
.
Tech in P
o
wer
Ele
c
troni
cs
and Drives
from
Karun
y
a Univ
ers
i
t
y
,
Coim
batore, T
a
m
il Nadu,
India. His present
research in
ter
e
sts are Power converters and i
nverters, Special machines, Solar and wind
Applica
tions.
Prof .K
. V
i
n
o
th
Ku
mar
recei
ved his
B.E. de
gree in El
ectr
i
c
a
l and El
ectron
i
cs
Engineer
ing
from Anna
Uni
v
e
r
si
ty
,
Che
n
na
i,
T
a
mi
l
Na
du,
Indi
a. He obtained
M.Tech in Power Electronics
and Drives from
VIT
Universit
y
, Vellor
e
, T
a
m
il Na
du, India. Presently
h
e
is working as an
Assistant Professor in the Scho
ol of El
ectrical
Science, Karun
y
a Institu
te of
Technolog
y
an
d
S
c
ienc
es
(Karunya Univ
ers
i
t
y
)
,
Coim
batore,
Ta
m
il Nadu, India. He is pursuing PhD degree in
Karun
y
a Univer
sity
, Coimbatore, India. His pres
ent research interests are Condition Monitoring
of Industrial Drives, Neural Networks and Fuzz
y
Logic, Special machines
, Application of Sof
t
Computing Technique. He has published various
papers in intern
ational journals
an
d
conferen
ces
and
also published
four tex
t
books.
He is a member of IEEE (USA), MISTE
and
als
o
in
Int
e
rnat
io
nal
as
s
o
ciat
ion o
f
El
ectr
i
c
a
l
Engi
neers
(IAENG).
Mr. A. Arn
o
l
d
Fred
d
erics
rece
ived his
B.Te
ch. degr
ee i
n
Electr
i
c
a
l an
d Electron
i
cs
Engineering fro
m Anna University
, Tamilnadu
,
Indi
a. P
r
es
ent
l
y
h
e
is
purs
u
ing M
.
Tech in P
o
wer
Ele
c
troni
cs
and Drives
from
Karun
y
a Univ
ers
i
t
y
,
Coim
batore, T
a
m
il Nadu,
India. His present
res
earch
in
teres
t
s
are
P
o
wer con
v
erters
,
S
p
ec
ial
m
achines
,
S
o
lar
Applica
tion.
Mr.
B.
Raja Gu
ru
rec
e
ive
d
his
B.Te
ch.
degr
ee
i
n
El
ectron
i
cs
an
d Com
m
unicatio
n Eng
i
neer
ing
from Anna
Uni
v
e
r
si
ty
,
Ta
mi
l
n
a
d
u,
India. Presently
h
e
is pursui
ng M.Tech in Power Ele
c
tron
ic
s
and Drives from Karuny
a University
, Coimbatore
,
Tam
il Nad
u
, India
.
His
pres
ent res
e
arc
h
inter
e
sts ar
e Res
onant
converters
,
Special mach
in
es,
Solar
Application
.
Ms
.S
ree
lak
s
h
m
y Nair
r
e
c
e
ived
his
B.Tech
. de
gree in E
l
e
c
trical and Electronics Engineering
fromSaintgits co
lleg
e
of engineer
ing,Mahatma Gandhi University
,
K
er
ala, India. Pr
esently
she
is
pursuing M.Tech in Power Electronics and Driv
es from Ka
runy
a
Uni
v
e
r
si
ty
,
Coimba
t
ore
,
T
a
mi
l
Nadu,
and India. Her pr
esent research
inte
re
st
s are dc
-dc c
onve
r
ter
s
and inv
e
rters.
Evaluation Warning : The document was created with Spire.PDF for Python.