Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
V
o
l.
7, N
o
. 1
,
Mar
c
h
20
16
,
pp
. 45
~55
I
S
SN
: 208
8-8
6
9
4
45
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
An Experimental Study of th
e Unbalance Compensation by
Voltage Source Inverter Based STATCOM
An
as Benslim
ane,
Jam
a
l Bouchn
aif,
Mo
ha
med Azizi, Kha
lid Gra
r
i
Laborator
y
of
Electr
i
cal
Engineer
ing and
Ma
inten
a
nce, High
er School of
Technolog
y
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Sep 24, 2015
Rev
i
sed
D
ec 15
, 20
15
Accepte
d Ja
n
6, 2016
This work presents an experim
e
ntal
stud
y
of the unbalan
ce compensation
caused b
y
th
e high speed
railway
substa
tions
in
the h
i
gh-voltage power gr
id
with a shunt voltag
e
source inv
e
rter
bas
e
d STATCOM. Th
is experimental
stud
y
is realized on a r
e
duced
scale pr
ototy
p
e. Th
e Control o
f
inverter is
im
plem
ented
in
a DS
P
card.
The
prac
tic
al r
e
s
u
lts
pres
ent
e
d in
thi
s
paper
are
shown the perfo
rmance of unbalance
compensation b
y
VSI_STATCOM in
s
t
atic
and
d
y
nam
i
c r
e
gim
e
.
Keyword:
DSP
Power System
P
W
M
i
nve
rt
er
STATC
O
M
Unb
a
lan
c
e com
p
en
satio
n
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Anas
Benslim
a
n
e,
Depa
rtem
ent of Electrical a
nd Co
m
p
u
t
er
Engin
eer
ing
,
Lab
o
rat
o
ry
of El
ect
ri
cal
Engi
neeri
n
g
an
d
M
a
i
n
t
e
nan
ce, Hi
ghe
r Sch
o
o
l
o
f
Tech
nol
ogy
EST-Ou
jd
a, Un
iv
ersity o
f
Mo
h
a
mm
ed
I, M
o
ro
cco
.
Em
a
il:an
a
s.b
e
nsli
m
a
n
e
@g
m
a
i
l
.co
m
1.
INTRODUCTION
Th
e
h
i
gh
sp
eed
r
a
ilw
ay sub-statio
n
s
co
nn
ected
b
e
t
w
een
t
w
o ph
ases of
t
h
e
h
i
gh
-vo
ltage po
w
e
r
g
r
i
d
are con
s
id
ered p
o
llu
tion
lo
ad
s, d
i
sr
up
ting p
o
w
e
r
gr
id
s. Th
e
m
a
j
o
r
pr
ob
lem
o
f
th
ese su
b-
statio
ns is th
e
un
bal
a
nce
[
1
]
.
The
com
p
ens
a
t
i
on
of
t
h
i
s
u
nbal
a
nce
by
c
u
r
r
ent
i
n
ject
i
o
n t
ech
ni
que
i
s
t
r
eat
ed i
n
t
h
e
o
ret
i
cal
vi
ew
poi
nt
by
sim
u
l
a
t
i
on [2]
.
Thi
s
w
o
r
k
p
r
es
ent
s
t
h
e ex
peri
m
e
nt
al
val
i
d
at
ion
of co
nt
r
o
l
l
a
ws f
o
r t
h
e u
n
b
al
anc
e
com
p
ensation. A re
duce
d
sc
ale prot
otype
m
odel is pres
ented in this
pape
r, the
n
we proceed t
o
s
i
ze the
n
ecessary ele
m
en
ts in
o
r
d
e
r to realize th
e exp
e
rim
e
n
t
al
test
, and
fi
n
a
lly we will co
m
p
are th
e practical resu
lts
wi
t
h
a
n
d
wi
t
h
out
c
o
m
p
ensat
i
on
by
vol
t
a
ge
so
urce
i
n
vert
y
e
r base
d
ST
ATC
O
M
(
V
SI
_ST
A
TC
OM
)
i
n
st
at
i
c
and
dy
nam
i
c regi
m
e
.
2.
NOTATION
Th
e no
tatio
n
used
t
h
ro
ugh
ou
t
th
e pape
r
is stated
bel
o
w.
Indexe
s:
a, b,
c
:
P
h
ase i
nde
x
p
o
we
r
gri
d
si
de ;
a’,
b
’
,
c’
:
Pha
s
e i
n
de
x i
nve
rt
er
AC
si
d
e
;
+
: Positiv
e
sequ
en
ce ind
e
x ;
- :
Negat
i
v
e
se
que
nce i
nde
x;
d
: d-ax
is co
m
p
on
en
t fo
r curren
t or
vo
ltag
e
(Park
tran
sformatio
n
)
;
q
:
q-axi
s
co
m
ponent
f
o
r c
u
r
r
ent
o
r
v
o
l
t
a
ge (Pa
r
k t
r
a
n
s
f
o
r
m
a
ti
on)
;
α
:
α
-axis co
m
p
o
n
e
n
t fo
r cur
r
ent o
r
v
o
ltag
e
(Clark
tran
sform
a
t
i
o
n
) ;
β
:
β
-a
xi
s c
o
m
ponent
fo
r c
u
rre
nt
o
r
v
o
l
t
a
g
e
(C
l
a
r
k
t
r
a
n
sf
orm
a
t
i
on)
.C
:
Set-poi
nt
of the i
n
jecte
d
current ;
.r
ef
:
Referen
ce
o
f
t
h
e inj
ected
cu
rren
t and
DC voltag
e
;
Co
nst
a
n
t
s &
Qua
n
tities
:
t
:
Tim
e
;
p
: Laplace transform
a
tion operator
;
V
r
: Ph
ase-
gro
und v
o
ltag
e
i
n
th
e pow
er
g
r
i
d
side
(aut
otran
s
f
o
rm
er’s sec
o
n
d
a
r
y
)
;
V
O
: Ph
ase-groun
d
v
o
ltage in
th
e in
v
e
rter AC sid
e
;
I
-
: Neg
a
tiv
e sequ
ence
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
45
–
5
5
46
of t
h
e curre
nt
consum
ed by the single-pha
s
e
load
;
I
inj
: Injecte
d
c
u
r
r
ent
fo
r
unbalance
com
p
ensation
;
I
L
:
Current cons
umed by th
e single
-
phase loa
d
;
ω
r
: Po
wer g
r
id
p
u
l
sation (
ω
r
=2.
π
.f
r
and f
r
= 50Hz
) ;
L
:
Filterin
g
indu
ctan
ce;
r
: Am
p
litu
d
e
ratio
o
f
th
e PW
M con
t
ro
l (
r =
V
réf.m
a
x
/ V
p.m
a
x
) ;
V
p.
ma
x
: A
m
p
litu
d
e
of
PW
M carrier
;
V
réf.m
ax
:
Am
pl
i
t
ude of P
W
M
si
nus
oi
dal
r
e
fere
nce
;
V
DC
: DC bu
s Voltag
e
;
f
d
: Swi
t
ch
ing
fre
que
ncy
;
δ
I
in
j
(%
)
: Ripple rate of t
h
e inje
cted curre
nt
;
a
: Fo
rtescu
e tran
sfo
r
m
a
tio
n
operato
r
a=e
j(2
π
/3)
;
C
:
Clark
transfo
r
matio
n
m
a
trix
;
C’
: Matrix
fo
r
d
e
term
in
in
g th
e in
stan
tan
e
o
u
s
po
wer in
α
-
β
fram
e
;
p(t) an
d
q(t)
: Activ
e an
d
reactiv
e in
stan
tan
e
ou
s
p
o
wer in
t
o
th
e
p
o
we
r g
r
id side
(autot
rans
f
o
r
m
er’s seco
n
d
ar
y
)
;
p
dc
:
Inst
a
n
t
a
ne
ou
s
po
we
r i
n
t
h
e
D
C
si
de
;
p
dc.corrected
: Co
rrected in
stan
tan
e
ou
s
p
o
wer in th
e
DC sid
e
;
K
v
:
Vo
ltag
e
co
n
t
ro
ller g
a
in;
τ
v
:Ti
m
e co
n
s
tan
t
of th
e
v
o
ltag
e
con
t
roller;
P
K
: Park
tran
sfo
r
m
a
tio
n
m
a
trix
;
θ
:
Park
t
r
ans
f
o
r
m
a
ti
on ope
rat
o
r
;
x
:
Mo
du
latin
g sign
al corrected
;
PWM
:
P
ul
se
-
w
i
d
t
h
m
odul
at
i
o
n
si
g
n
al
K
I
:
C
u
rre
nt
c
o
nt
r
o
l
l
e
r gai
n
;
τ
I
: Tim
e
co
n
s
tan
t
of t
h
e cu
rren
t con
t
ro
ller
3.
P
R
E
S
E
N
TA
TI
O
N
O
F
TH
E
EX
P
E
R
I
M
E
NT
A
L
P
R
O
T
OT
Y
P
E
Thi
s
re
duce
d
s
cal
e prot
ot
y
p
e
(Fi
g
ure
1) i
s
r
eal
i
zed
in
o
r
d
e
r to
v
a
lid
ate
the unbalance c
o
m
p
ensation
by
t
h
e c
u
r
r
ent
i
n
ject
i
o
n t
ech
n
i
que,
usi
n
g
t
h
e
v
o
l
t
a
ge s
o
u
r
ce
i
nve
rt
er
base
d
sh
unt
STA
T
C
O
M
.
It
i
s
c
o
m
pos
e
d
of:
A v
a
riab
le sing
le p
h
a
se resistiv
e lo
ad
, connected
b
e
tween two
p
h
a
ses o
f
lo
w v
o
ltage po
wer grid
. Th
is
lo
ad
is equ
i
v
a
l
e
n
t
to
a h
i
gh
speed
railway sub
s
tatio
n to
g
e
nerate a cu
rren
t
u
n
b
a
lan
c
e.
Three
-
phase
a
u
t
o
t
r
a
n
s
f
o
r
m
e
r of a
n
a
u
t
o
n
o
m
ous p
o
st
i
n
el
ect
rot
e
c
h
n
i
cal
l
a
borat
or
y
,
pr
ot
ect
ed
by
d
i
fferen
tial circu
it break
er, t
h
is au
to
tran
sformer su
pplies t
h
e si
ngle
phas
e load bet
w
een two phases
. T
h
e
current
unbalance ca
use
d
by the si
n
g
l
e phase lo
ad
, leads to
a vo
ltag
e
un
b
a
lan
ce, v
i
a th
e
n
e
twork
im
pedances
at
t
h
e l
o
a
d
c
o
n
n
e
c
t
i
on
poi
nt
(a
ut
ot
ra
nsf
o
rm
er’s
seco
nda
ry
).
A voltage s
o
urce inverte
r
(low voltage)
of
Semikr
on m
a
nufact
ure
r
whos
e PW
M control is accessible.
Th
is in
v
e
rter co
n
t
ains a DC cap
acito
r eq
u
i
v
a
len
t
to
an
en
erg
y
sto
r
ag
e
circu
it; th
e in
itial ch
arg
i
ng
by a
DC vo
ltag
e
sou
r
ce is realized b
y
th
e switch
S2
; its
d
i
sch
a
rg
e is
realized
by th
e switch
S1
an
d th
e
resist
o
r
Rd
c.
Th
ree si
n
g
l
e-ph
ase filter in
du
ctan
ce in
o
r
d
e
r to
filte
r th
e curren
t
in
jected
at th
e au
to
tran
sform
e
r’s
seconda
ry.
A sm
al
l
cont
r
o
l
pa
nel
w
h
i
c
h c
ont
ai
ns a
cou
p
l
i
n
g c
o
nt
act
or t
o
t
h
e a
u
t
o
t
r
a
n
s
f
o
r
m
e
r’s sec
o
nda
ry
and
ove
rl
oa
d rel
a
y
fo
r pr
ot
ect
i
n
g
t
h
e
s
h
unt
STA
T
C
O
M
agai
nst
o
v
er
-cu
rre
nt
due
t
o
ove
rl
oa
d.
A D
SP ca
rd
(r
ef : CP 1
1
0
4
)
i
n
o
r
der t
o
en
su
re the c
ont
rol
of t
h
e injected
curren
t, th
e con
t
ro
l o
f
DC
b
u
s
voltage
, a
n
d generating t
h
e PWM signals. T
h
is card is
e
q
uippe
d
by an int
e
rface ci
rcuit
board in order t
o
real
i
ze an i
s
ol
a
t
i
on
bet
w
ee
n c
ont
rol
part
a
n
d
po
we
r sy
st
em
.
Cu
rren
ts sen
s
ors with
g
a
i
n
(b
i
) a
n
d V
o
l
t
a
g
e
s sens
or
s wi
t
h
gai
n
(
b
v
) i
n
o
r
d
e
r t
o
tran
smit th
e v
a
lu
es o
f
th
ese real
qu
antities to
th
e DSP card
.
The di
st
ur
ban
ces exi
s
t
i
ng i
n
t
h
e hi
g
h
-
v
ol
t
a
ge p
o
w
er
gri
d
are
not
c
ons
i
d
ere
d
i
n
t
h
i
s
l
o
w
-
v
o
l
t
a
ge
red
u
ce
d scal
e
pr
ot
ot
y
p
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An Ex
peri
ment
al
St
udy
of
t
h
e
Un
b
a
l
a
nce C
o
mpe
n
s
a
t
i
o
n
by
VSI
B
a
sed
S
T
A
T
C
O
M (
A
nas
Bensl
i
m
ane)
47
Fi
gu
re
1.
R
e
d
u
ced scal
e
pr
ot
o
t
y
p
e o
f
vol
t
a
ge
so
urce
i
n
vert
e
r
based
s
h
u
n
t
S
T
ATC
O
M
4.
TECHNI
C
AL
CH
A
R
A
C
TE
RISTI
C
S OF RED
UCE
D S
CALE
P
R
OTOTYPE
a.
Three-Phase
Vol
t
age
Sourc
e
PW
M Inver
t
er (Figure
2)
The voltage source inverte
r
is im
portant in the st
ruct
ure of
shunt ST
ATC
O
M
because it represe
n
ts a
t
h
ree-
p
h
ase
vo
l
t
a
ge so
urce
w
h
i
c
h i
m
poses a
n
AC
vol
t
a
ge a
t
t
h
e out
put
fr
o
m
a DC
vol
t
a
g
e
. The c
o
nt
rol
of t
h
i
s
v
o
ltag
e
allows to
i
m
p
o
s
e th
e in
j
ected
current by the voltage differe
n
ce (V
O
(t) –
V
r
(t)) acro
ss the filter
in
du
ctor
.
This inverte
r
is
equipped
with a
control interface com
pose
d
by the
dri
v
er
circuits in
orde
r to e
n
s
u
re
th
e IGBT switch
i
ng
,
PD3
rectifier in
o
r
d
e
r t
o
en
su
re
t
h
e
DC voltage s
o
urce, the
capacit
o
r DC link
ba
nk, a
n
d
two
coo
lin
g fan
s
.
V
o
l
t
ag
e so
u
r
c
e
i
n
ver
t
e
r
(
S
em
i
k
r
o
n
)
*
Is
o
l
a
t
i
o
n
tr
a
n
s
f
o
r
m
e
r*
A
ut
o
t
r
a
n
s
f
o
r
m
e
r
*
D
i
f
e
r
e
n
t
i
a
l
c
i
r
c
u
i
t
br
eak
er
*
R
e
s
i
s
tiv
e
lo
a
d
*
L*
Cd
c
*
Rd
c
*
S1*
o
v
er
l
o
ad r
eal
y*
Co
u
p
l
i
ng
Co
n
t
a
c
t
o
r
*
Vd
c
*
DS
P
C
P
1104
Cu
r
r
e
n
t
s
e
n
s
o
r
b
i
=
100m
V
/
A
Vo
lta
g
e S
e
n
s
o
r
bv
=
1
/
1
0
0
Vr
40
0 V
V
a
r
i
ab
l
e
S
e
c
o
n
d
ar
y
40V -
450V
N
DC
Vo
l
t
age
s
o
u
r
c
e
*
S2
PW
M
a
b
c
Ii
n
j
Ir
V
o
l
t
ag
e
S
e
n
s
or
bv
=
1
/
1
0
0
Vo
a'
b
'
c'
I
L
Evaluation Warning : The document was created with Spire.PDF for Python.
I
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I
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S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
45
–
5
5
48
Fi
gu
re
2.
P
o
we
r st
r
u
ct
u
r
e
of
t
h
e i
n
ve
rt
er
b.
Filtering I
ndu
ctor
Th
e i
n
du
ctan
ce, used fo
r filtering
th
e inj
e
cted
cu
rren
t i
n
to
the
p
o
wer
g
r
id
, is a lam
i
n
a
t
e
d
m
a
g
n
e
ti
c
circu
it ind
u
c
t
o
r with
a static resistan
ce R.
c.
A
u
tot
r
ansfo
r
mer of
A
u
t
o
no
mo
us Po
st
It is a
three-phase autotra
n
sform
e
r with
star
co
nn
ection
and
with
g
a
l
v
ani
c
isolation. For reasons
of
security
and sizing optim
i
zat
ion
,
t
h
e
com
pos
ed sec
o
nda
ry
v
o
l
t
a
ge i
s
a
d
ju
st
ed at
√
3.V
r
= 80 V.
d.
Single-P
hase Load
It is a variable single phase re
sistive
load, which cons
um
es
a variable power [
50
VA
;
53
0VA
] with
a
fi
xe
d
vol
t
a
ge
o
f
80
V
. T
h
e load c
r
eates a c
u
rre
nt unbalanc
e
and a
vo
ltag
e
un
b
a
lan
ce in th
e au
to
tran
sformer’s
seco
nda
ry
. T
h
i
s
u
n
b
a
l
a
nce
wi
l
l
be com
p
ensa
t
e
d by
t
h
e
vol
t
a
ge s
o
urce i
n
v
e
rt
er
base
d s
h
u
n
t
ST
ATC
O
M
.
e.
DSP
C
a
rd
(re
f
:
CLP
1
10
4
)
The DSP ca
rd controls the i
n
jecte
d
curre
nt
into
th
e
p
o
wer grid
, and
th
e DC bu
s vo
ltag
e
. Con
t
ro
l
lo
op
s
realized
b
y
Sim
u
lin
k
b
l
o
c
ks will b
e
t
r
an
slated
au
to
m
a
tically
in
C lan
g
u
a
g
e
b
y
th
e
DSP card
so
ft
ware.
Th
is
p
r
o
g
ram will g
e
n
e
rate th
e PWM si
g
n
a
ls con
t
ro
llin
g th
e cu
rren
t and
keep
i
n
g
th
e DC
bu
s
vo
ltag
e
constant.
5.
SIZ
I
NG PROTOTYPE PARAMETERS
5.1. Power Ci
rcuit
5.
1.
1
Injec
t
ed Curr
ent
The curre
nt injected by the inve
rt
er
de
pen
d
s
on t
h
e
ne
gat
i
v
e seq
u
e
n
ce of the current c
o
nsum
ed by
th
e sing
le-p
hase lo
ad acco
r
d
i
ng
to th
e
fo
llo
wi
n
g
co
m
p
lex
equ
a
tio
n (1
) [2
]:
I
I
√
I
e
π
(
1
)
Th
e
rm
s v
a
lu
e
o
f
th
e cu
rren
t in
j
ected
b
y
th
e in
v
e
rter is v
a
riab
le b
e
t
w
een [
0
,
3
6
A
;
3,825
A
].
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
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S
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9
4
An Ex
peri
ment
al
St
udy
of
t
h
e
Un
b
a
l
a
nce C
o
mpe
n
s
a
t
i
o
n
by
VSI
B
a
sed
S
T
A
T
C
O
M (
A
nas
Bensl
i
m
ane)
49
5.
1.
2
DC
Bus V
o
lta
g
e
If we n
e
g
l
ect th
e vo
ltag
e
h
a
rm
o
n
i
cs in
th
e in
v
e
rter AC
sid
e
to
th
e fu
nd
am
en
tal an
d
th
e static
resistance
(R)
of the s
e
lf to t
h
e indu
ctive
re
actance, t
h
e c
o
m
p
lex equation th
at
relates t
h
e injecte
d
c
u
rrent at
th
is vo
ltag
e
is [3
] :
V
L
ω
e
π
.I
V
(
2
)
For a t
h
ree
-
p
h
a
se si
nus
-t
ri
a
n
gl
e P
W
M
i
n
ve
rt
er, t
h
e
DC
b
u
s v
o
l
t
a
ge i
s
d
e
pen
d
i
n
g
on t
h
e po
wer
g
r
i
d
v
o
ltag
e
, an
d the m
a
x
i
m
u
m
v
o
ltag
e
drop
i
n
the filtering
inducto
r:
V
√
max
Lω
e
.I
.
V
(
3
)
5.
1.
3
Ripple Rate of
the
Injec
t
ed Current
Th
e equ
a
tio
n th
at relates the
ripp
le rate
o
f
in
j
ect
ed
cu
rren
t with
t
h
e
v
a
lu
e o
f
th
e
filtering in
du
ctan
ce
is d
e
fi
n
e
d in
t
h
e article [4
]:
L
∗
.é
√
.
.
.
%
.
(
4
)
Acco
r
d
i
n
g t
o
t
h
i
s
e
quat
i
o
n,
w
e
de
duce
t
h
e
e
x
p
r
essi
on
o
f
c
u
rre
nt
ri
ppl
e
rat
e
:
δI
%
∗
.
é
√
.
.
..
(
5
)
5.
2. C
o
ntr
o
l
P
a
rt
5.
2.
1
Calcul
ating the
Set-P
o
int of Injec
t
ed Curr
ent
The s
h
unt
ST
ATCOM m
u
st inject t
h
e
ne
gative sequ
e
n
ce
of the
curre
nt
cons
um
ed by the si
ngle-
pha
se l
o
a
d
i
n
t
h
e
po
we
r g
r
i
d
con
n
ect
i
o
n
poi
nt
(a
ut
ot
ra
ns
fo
rm
er’s seco
n
d
a
r
y
)
.
Acc
o
r
d
i
n
g
t
o
e
quat
i
o
n
(
1
) an
d
kn
o
w
i
n
g t
h
at
t
h
e i
n
ject
ed
c
u
r
r
ent
s
ha
ve a
ne
gat
i
v
e se
q
u
ence
or
der
,
t
h
e
bl
oc
k
di
ag
ram
for t
h
e s
e
t
-
p
o
i
n
t
g
e
n
e
ration
o
f
t
h
e inj
ected
cu
rren
ts i
n
to
t
h
e t
h
ree ph
ases pow
er gr
id
is pr
esen
ted in
f
i
gu
re 3
[2
].
Fig
u
re
3
.
Ob
tain
ing
th
e set-p
o
in
t curren
t
s to
b
e
inj
ected
5.
2.
2
DC
Bus V
o
lta
g
e Co
nt
r
o
l
(fi
g
ure 4)
The DC
bu
s v
o
l
t
a
ge
V
DC
acros
s the capacitor m
u
st be
m
a
intained at a fixe
d
value (
V
DC.ref
).
The m
a
in
cau
se
wh
ich
affects t
h
e stabilit
y o
f
t
h
is vo
ltag
e
is
t
h
e
p
o
wer lo
sses i
n
th
e co
m
p
ensato
r
(power switch
,
filterin
g
indu
cto
r
). Con
t
ro
l o
f
th
e av
erag
e vo
ltag
e
acro
ss t
h
e cap
acitor mu
st b
e
realized b
y
d
e
term
in
in
g
the
refe
rence
cu
rre
nts that m
a
intain
V
DC
co
n
s
tan
t
, fro
m
th
e set-po
in
t curren
t
to
b
e
inj
ected. For
g
e
n
e
rating
the
referen
ce cu
rren
ts
m
a
in
tain
ed
V
DC
co
n
s
tan
t
,
we are b
a
sed
on
th
e in
stan
taneo
u
s p
o
wer m
e
th
od
with
th
e
Clark
tran
sform
a
t
i
o
n
(
α
-
β
) [5
]. This tran
sfo
r
m
a
ti
o
n
is app
lied
to
th
e p
o
wer g
r
i
d
vo
ltag
e
V
r
, and
th
e neg
a
tiv
e
sequence
of the injecte
d
c
u
rrent
.
I
t
e
√
3
3
I
.
.
t
a
a
I
.
.
t
I
.
.
t
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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94
I
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PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
45
–
5
5
50
Fi
gu
re 4.
Di
a
g
r
a
m
cont
r
o
l
bl
o
c
ks of
t
h
e v
o
l
t
a
ge VDC
Wi
t
h
:
C
√
0
√
√
√
√
√
2
√
√
A
n
d
C
V
α
V
β
V
β
V
α
5.
2.
3
DC
Bus Voltage Contr
o
ller
In or
der
t
o
kee
p
t
h
e
V
DC
con
s
tan
t
, it is n
ecessary th
at th
e vo
lta
ge controller creates an instantane
ous
powe
r whic
h corrects the value of th
e inject
ed curre
n
t refe
rence
.
The
R
u
(p)
con
t
ro
ller is a p
r
op
ortio
nal with
d
e
lay, th
e t
r
ansfer
fu
n
c
tion
is
[5
] :
R
p
(
6
)
5.
2.
4
C
o
n
t
ro
l o
f
t
h
e
I
n
j
e
ct
e
d
C
u
rr
e
n
t
s
in the d-q Fr
ame
(fi
g
u
re
5 an
d 7)
:
The c
u
rre
nt
c
o
nt
r
o
l
l
o
op
i
m
poses t
h
e
val
u
e
o
f
t
h
e c
u
rrent
s
injected by t
h
e s
h
unt
ST
ATCOM.
The
ch
o
i
ce
of th
e
cu
rren
t con
t
ro
ller is b
a
sed on
th
e con
t
ro
l
o
b
j
ectiv
es and th
e
o
u
t
p
u
t
filter
o
r
d
e
r. Th
e
cu
rrent
cont
rol in t
h
e
cont
rol
part is
realized by a c
o
m
p
arison
of
the real injecte
d
curre
nt
with
the refe
re
nce c
u
rrents
th
at m
a
in
tain
V
DC
con
s
tan
t
.
Th
is co
n
t
ro
l is realized
i
n
the
d-q
fram
e
for
both c
u
rre
nt injected se
quences
(po
s
itiv
e sequ
en
ce and
n
e
g
a
tiv
e sequ
en
ce) [6
]. Th
e g
e
n
e
ratio
n
o
f
three-ph
ase PW
M con
t
ro
l sig
n
a
ls fro
m
th
e
corrected m
o
dulating
signals
i
s
sh
ow
n i
n
fi
g
u
re
6
.
Wi
t
h
:
P
2s
i
n
θ
2
s
i
n
θ
2
s
i
n
θ
2
cos
θ
2
cos
θ
2
cos
θ
11
1
P
2s
i
n
θ
2s
i
n
θ
2
s
i
n
θ
2
cos
θ
2
cos
θ
2
cos
θ
11
1
I
.
é
t
C
-1
p
dc.
correcte
d
I
.
t
I
.
t
I
.
t
α‐β
Trans
formation
Matri
x:C
V
t
V
t
V
t
α‐β
Trans
formation
Matri
x:C
q
t
p
t
‐
‐
V
DC.réf
V
D
R
u
p
I
.
I
.
V
t
V
t
C’
C’
-1
I
.é
I
.
é
I
.
é
t
I
.
é
t
I
.
é
t
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An Ex
peri
ment
al
St
udy
of
t
h
e
Un
b
a
l
a
nce C
o
mpe
n
s
a
t
i
o
n
by
VSI
B
a
sed
S
T
A
T
C
O
M (
A
nas
Bensl
i
m
ane)
51
Fi
gu
re
5.
Di
a
g
r
a
m
cont
r
o
l
bl
o
c
ks
of
t
h
e i
n
j
e
c
t
ed cu
rre
nt
ne
g
a
t
i
v
e seq
u
e
n
ce
Fi
gu
re
6.
Ge
ne
rat
i
o
n
o
f
t
r
ee
-
p
hases
P
W
M
si
gnal
s
Co
m
p
ar
a
t
o
r
x
t
x
t
x
t
x
t
x
t
x
t
PWM
PWM
PWM
Carrier
In
v
e
rse Park
tr
ansform
a
tion for
negative sequence
P
x
x
In
v
e
rse Pa
rk
tr
ansform
a
tion for
positive sequence
P
x
x
x
t
x
t
x
t
+
+
+
+
+
+
I
m
R
L
p
I
Lω
2
V
.
é
I
.
é
I
.
é
I
.
é
Par
k
tr
ansform
a
tio
n for
negative
sequence
P
I
.
é
I
.
é
V
.
+
I
m
R
L
p
‐
x
V
.
é
2
-
R
I
p
Lω
2
V
.
é
I
‐
R
I
p
x
V
.
é
2
V
.
‐
Physical
syst
e
md‐axis
Physicalsystemq
‐
axis
Controllercomp
ensation
q‐axi
s
Controllercomp
ensation
d‐axi
s
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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94
I
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PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
45
–
5
5
52
Fig
u
re
7
.
Diagram
co
n
t
ro
l
b
l
o
c
ks
o
f
t
h
e inj
e
cted
curren
t
positiv
e sequ
ence
5.
2.
5
Injec
t
ed
c
u
rre
nt Contr
o
ller
The injected c
u
rrent re
fere
nc
e is variable depe
nding on the powe
r cons
um
ed by the s
i
ngle-phase
l
o
ad.
S
o
i
n
o
r
d
e
r t
o
i
m
pro
v
e t
h
e
per
f
o
r
m
a
nce of
t
h
i
s
c
ont
r
o
l
,
we
use a m
i
xed
PI c
o
nt
r
o
l
l
e
r
R
I
(p)
. Its t
r
ansfe
r
fun
c
tion
is:
R
p
K
(
7
)
Th
is co
n
t
ro
ller allo
ws to
can
c
el th
e static
error and t
o
re
duc
e
the
dynam
i
c error.
6.
E
X
PERI
MEN
T
AL RES
U
L
T
S
We presen
t in
th
is p
a
rt th
e resu
lts o
b
t
ain
e
d
with
an
d wi
t
h
out
com
p
ensat
i
on by
cu
rre
nt
i
n
ject
i
o
n i
n
st
at
i
c
and dy
n
a
m
i
c regim
e
.
The v
o
l
t
a
ge u
nbal
a
nce fact
o
r
(
T
iv
(%
)
), t
h
e vol
t
a
ge t
o
t
a
l
harm
oni
c di
st
ort
i
o
n
(
THD
v
(%
)
), a
n
d
t
h
e
DC
bus
v
o
l
t
a
ge are
ac
qui
red
by
osci
l
l
o
sco
p
e a
nd
p
l
ot
t
e
d u
s
i
n
g M
A
TL
AB
t
o
ol
s.
Thi
s
expe
ri
m
e
nt
al
test
i
s
real
i
zed t
h
r
o
ug
h t
h
e f
o
l
l
o
wi
ng
pa
ram
e
ters:
I
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Parktrans
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tive
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P
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Physicalsystemd
‐
axis
Controllercomp
ensation
d‐axi
s
Controllercomp
ensation
q‐axi
s
Physicalsyst
e
mq‐axis
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
An Ex
peri
ment
al
St
udy
of
t
h
e
Un
b
a
l
a
nce C
o
mpe
n
s
a
t
i
o
n
by
VSI
B
a
sed
S
T
A
T
C
O
M (
A
nas
Bensl
i
m
ane)
53
Tabl
e 1. Po
wer
ci
rcui
t
param
e
t
e
rs
Pow
er circuit
Para
m
e
ter
Value
L
i
ne-
line power grid voltage (
a
utotr
a
nsform
er’
s
secondar
y
)
80V
Refer
e
nce of the DC bus voltage
V
DC.réf
300V
Variable single-ph
ase resistive load
Apparent power
S
L
with supply
b
y
8
0
V [50VA
→
530V
A]
DC Capacitor
6
m
F
Filtering inductor
30
m
H
/0.4
Ω
Tabl
e
2. C
ont
r
o
l
pa
rt
param
e
ters
Control part
Para
m
e
ter
Value
Carrie
r
f
r
equency
5KHz
Gain of cur
r
e
nt sensor
100
m
V
/A
Gain of voltage sensor
1/100
Gain of voltage contr
o
ller
K
v
95.
47
tim
e
constant of the voltage contr
o
ller
τ
v
9,
43
m
s
Gain of cur
r
e
nt co
ntr
o
ller
K
I
10
tim
e
constant of the cur
r
e
nt
contr
o
ller
τ
I
75
m
s
Static Regime
Fi
gu
re 8.
V
o
l
t
a
ge un
bal
a
nc
e
f
act
or
T
iv
a
n
d
v
o
l
t
a
ge t
o
t
a
l
har
m
oni
c di
st
ort
i
o
n
THD
v
in functio
n
o
f
th
e l
o
ad
po
we
r (
S
L
)
Fi
gu
re 9.
DC
b
u
s vol
t
a
ge V
DC
in
fun
c
tion
o
f
th
e
lo
ad
p
o
wer
(
S
L
)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l. 7,
No
.
1,
Mar
c
h
2
016
:
45
–
5
5
54
Dy
namic
Re
gi
me
Fig
u
r
e
10
.
Step r
e
sp
on
se of
the in
j
ected
cu
rren
t
in
t
h
e
dq
-f
ra
m
e
(
a
: d-
ax
is, b : q-
ax
is)
Fig
u
re
11
.
DC
b
u
s
Vo
ltag
e
in
fun
c
tion
o
f
i
n
jected
curren
t set-po
in
t ch
ange
Fi
gu
re
1
2
. E
x
p
e
ri
m
e
nt
al
banc pi
ct
u
r
e
Evaluation Warning : The document was created with Spire.PDF for Python.