Internati
o
nal
Journal of P
o
wer Elect
roni
cs an
d
Drive
S
y
ste
m
(I
JPE
D
S)
Vol.
6, No. 4, Decem
ber
2015, pp. 788~
796
I
S
SN
: 208
8-8
6
9
4
7
88
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJPEDS
Devel
o
p
m
ent of Digit
a
l Cont
roll
er for DC-DC B
u
ck Con
v
ert
e
r
Saru
n S
o
m
a
n
1
,
Sa
ng
eeth
a
T.S
.
2
1
Departm
e
nt
of
Ele
c
tri
cal
and
E
l
ectron
i
cs Eng
i
ne
ering,
Manip
a
l
I
n
stitute
of
Te
chn
o
log
y
, Ind
i
a
2
Departm
e
nt of
I
n
form
ation
and
Com
m
unication Tec
hno
log
y
, Manipal
Institu
te of
Technolog
y
,
In
dia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
May 2, 2015
R
e
vi
sed Oct
8,
2
0
1
5
Accepted Oct 25, 2015
This paper pr
esents a design
& impl
ementation of 3P3Z (3-pole 3-zero
)
digital
controller
based on
DSC (Dig
ital
Signa
l
Controller
)
for
l
o
w voltag
e
s
y
nchronous Bu
ck Converter. The proposed co
ntrol involv
e
s one voltag
e
control
loop. Analog Ty
p
e
-3
con
t
roller is d
e
signed for Buck Conv
erter
using
standard frequ
en
cy
r
e
sponse tech
niques.
Ty
p
e
-3 analog controller
transforms
to 3P3Z controller in discrete d
o
ma
in.Matlab/Simulink model of the Buck
Converter wi
th digital contr
o
ll
er
is de
veloped
.
S
i
m
u
altion resul
t
s for stead
y
state response
an
d load
tr
ansient r
e
sponse is tested
using th
e model.
Keyword:
D
C
-D
C conv
erter
Dig
ital Con
t
ro
l
Dig
ital Sign
al
co
n
t
ro
ller
Vol
t
a
ge
M
o
de
C
ont
r
o
l
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Sarun Som
a
n,
Depa
rtem
ent of Electrical a
n
d
El
ect
ro
ni
cs E
n
gi
nee
r
i
n
g,
Min
i
p
a
l In
stitute o
f
Techno
log
y
.
Em
a
il: saru
n
.
so
m
a
n
@
m
a
n
i
p
a
l.ed
u
1.
INTRODUCTION
The o
b
j
ect
i
v
e
of a c
ont
r
o
l
sy
st
em
i
s
t
o
m
a
ke a phy
si
cal
sy
st
em
behave i
n
a usef
ul
fas
h
i
o
n
,
causi
n
g
i
t
s
out
p
u
t
t
o
t
r
ack a de
si
re
d r
e
fere
nce i
n
p
u
t
even i
n
t
h
e
pre
s
ence
of
noi
se
,
m
odel
i
ng
er
ro
r &
di
st
ur
ba
nc
es. I
n
the control sys
t
e
m
one of t
h
e m
a
in
com
p
o
n
ent
s
i
s
t
h
e c
o
nt
r
o
l
l
e
r,
whi
c
h
ge
nerat
e
s t
h
e
ap
pr
op
ri
at
e c
ont
ro
l
si
gnal
f
o
r t
h
e
phy
si
cal
sy
st
em
perf
orm
a
nce. Ty
pe-
3
co
nt
r
o
l
l
e
r i
s
on
e o
f
t
h
e m
o
st
co
m
m
on t
y
pes of f
eedba
c
k
cont
rollers
that
are
use
d
in DC-DC c
o
nve
rters [1].
Trad
ition
a
lly reg
u
l
ation
of the o
u
t
p
u
t
v
o
ltag
e
of
DC
-DC
co
nv
erter h
a
s
b
een
ach
i
ev
ed th
roug
h
t
h
e
use of analog cont
rol techniques. An
al
o
g
co
n
t
rol
sy
st
em
ope
rat
e
s i
n
real
t
i
m
e and can
ha
ve a hi
gh
ban
d
w
i
d
t
h
.
In
ad
d
ition
th
e v
o
ltag
e
regu
latio
n
fo
r an
an
alo
g
system
is
t
h
eoretically in
fin
ite. Howev
e
r an
an
alog
syste
m
is
usu
a
l
l
y
com
posed
o
f
di
scret
e
ha
rd
wa
re t
h
at
m
u
st
be m
odi
fi
ed t
o
c
h
a
nge
co
nt
r
o
l
l
e
r
gai
n
s
or
al
g
o
r
i
t
h
m
s
.
In
ad
d
ition
th
e i
m
p
l
e
m
en
tatio
n
o
f
ad
v
a
n
c
ed
co
n
t
ro
l algo
rit
h
m
s
req
u
i
re an
ex
cessiv
e
nu
m
b
er o
f
co
mp
on
en
ts
wh
ereas th
e com
p
lex
i
t
y
o
f
a d
i
g
ital co
n
t
ro
l
syste
m
is
cont
ai
ned m
o
st
l
y
in so
ft
wa
re.
Di
gi
t
a
l
pro
cesso
r
s
al
so
have
t
h
e a
d
va
n
t
age o
f
bei
n
g l
e
ss su
scept
i
b
l
e
t
o
a
g
ei
n
g
& e
nvi
ro
nm
ent
a
l
or
param
e
t
e
r var
i
at
i
ons.
Th
e
im
p
l
e
m
en
tatio
n
o
f
3
P
3
Z
(3-po
l
e3-zero) d
i
g
ital
con
t
ro
ller u
s
ing
DSC
(Dig
ital
Sign
al Co
n
t
ro
ller)
requ
ires
o
n
l
y on
e in
pu
t ch
an
nel with
an
alog
to
d
i
g
ita
l co
nversion
cap
ab
ilities if v
o
ltag
e
m
o
d
e
co
n
t
ro
l is u
s
ed.
Thi
s
i
n
p
u
t
c
h
a
nnel
capt
u
res
t
h
e si
gnal
o
f
si
gnal
o
f
o
u
t
p
ut
vol
t
a
ge
.
Fu
rt
he
r t
w
o
P
W
M
o
u
t
p
ut
s a
r
e
nee
d
ed
f
o
r
switch
con
t
ro
l. Th
ese requ
ire
m
en
ts
are available in
m
a
ny low cost di
gi
t
a
l
devi
ces and
hence t
h
e
t
r
u
e
challenge is to accom
p
lish the control aim
s
with a
n
acce
pt
able processing tim
e. Thus
it
is wort
h to point out
th
at in
fo
rm
atio
n
lo
sses cau
s
ed b
y
q
u
a
n
tizatio
n
,
ou
tpu
t
reso
l
u
tio
n, acq
u
i
sitio
n ti
m
e
s & processin
g
ti
m
e
s can
b
e
accentuate
d
by lim
i
tations in
a lo
w cost di
gital im
ple
m
entation.
Thi
s
pape
r
pre
s
ent
s
a si
m
p
l
e
m
e
t
hod
ol
o
g
y
fo
r
desi
g
n
a
n
d
im
pl
em
ent
a
t
i
on
of
di
gi
t
a
l
co
nt
r
o
l
l
e
r f
o
r
DC
-
D
C
C
o
nve
rt
er usi
ng M
a
t
l
ab/
S
i
m
ul
i
nk. T
h
e desi
gn a
p
pr
oach st
a
r
t
s
wi
t
h
m
odel
l
i
ng an
d si
m
u
l
a
t
i
on o
f
t
h
e
cont
rol
l
e
d
sy
st
em
of
sy
nc
hr
o
n
o
u
s
b
u
c
k
c
o
n
v
ert
e
r
i
n
M
a
t
l
a
b/
Si
m
u
l
i
nk. T
h
e st
ruct
ure
i
n
u
s
e i
m
pl
em
ent
s
Ty
pe-
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Developme
nt
of Digital C
ontr
o
ller for
DC-DC Buck C
o
nver
ter (Sar
un
Soman)
78
9
3
co
n
t
ro
l laws in
d
i
screte ti
me sy
ste
m
. So
th
e co
n
t
ro
ller is fo
rm
u
l
ated
in
th
e con
tinuo
u
s
-tim
e d
o
m
a
i
n
and
cont
rol
l
e
r
eq
ua
t
i
ons a
r
e
di
scre
t
i
zed t
o
i
m
pl
em
en
t th
e co
n
t
ro
ller as co
m
p
utatio
n
a
l algo
rith
m
.
2.
CLOSE
D
LO
OP
CO
NTRO
L SYSTE
M
Fi
gu
re 1 s
h
ow
s t
h
e bl
oc
k di
a
g
ram
of a t
y
pi
cal
di
gi
t
a
l
cont
rol
sy
st
em
. A
di
gi
t
a
l
sy
st
em
ope
rat
e
s o
n
th
e sam
p
les o
f
th
e sen
s
ed
p
l
an
t ou
tpu
t
. ADC is fo
r sam
p
li
n
g
ou
tpu
t
vo
ltag
e
,
DPWM is fo
r
g
e
n
e
rating driv
er
sig
n
a
l accor
d
i
ng
to co
rr
espond
ing
con
t
r
o
l
law
s
. Th
e co
m
p
en
sator
is fo
r gen
e
r
a
ting
t
h
e co
n
t
r
o
l
sign
al y(
n)
b
y
co
m
p
en
satin
g th
e er
ro
r sign
al
e(
n)
.
Th
e inpu
t &
ou
tpu
t
of a
d
i
g
ital con
t
ro
ller are related
by a lin
ear d
i
fferen
ce
equat
i
o
n suc
h
as:
(1
)
, (2)
is th
e sam
p
ling
freq
u
e
n
c
y.
In
t
h
e
d
e
sign
of d
i
g
ital co
n
t
roller, two techn
i
q
u
e
s are
g
e
n
e
rally ap
p
lied
.
Th
e fi
rst is d
i
g
ital red
e
si
gn,
wh
ere an
y zero
-o
rd
er
h
o
l
d
& sam
p
lers in
the con
t
ro
l lo
o
p
& do
a pr
elimi
n
ar
y
d
e
sign
i
n
s do
m
a
in
. Th
e
d
e
sign
i
s
t
h
en c
o
nve
rt
ed t
o
a di
sc
ret
e
t
i
m
e
by
sam
e
ap
pr
oxi
m
a
t
i
on t
ech
ni
q
u
e t
o
y
i
el
d a di
scr
e
t
e
t
i
m
e
co
m
p
en
sat
o
r.
Th
e secon
d
meth
od
is t
o
con
v
e
rt th
e con
tin
uou
s tim
e p
l
an
t with zero
-
ord
e
r
h
o
l
d
& sam
p
lers to
a d
i
screte
pl
ant
usi
n
g s
o
m
e
app
r
o
x
i
m
ati
on t
e
c
hni
qu
e.
Once
t
h
e
di
scr
e
te ti
m
e
ap
p
r
ox
im
a
tio
n
of t
h
e p
l
an
t is av
ailab
l
e, th
e
di
scret
e
t
i
m
e com
p
ensat
o
r
i
s
desi
g
n
e
d
di
rect
l
y
i
n
z
dom
ai
n.
Di
gi
t
a
l
redesi
gn
ap
p
r
oac
h
i
s
use
d
he
re t
o
d
e
si
gn
th
e con
t
ro
ller
fo
r Bu
ck
C
o
nv
erter.
3.
3P
3Z
CONT
R
O
L ALG
O
R
I
THM
For
di
gi
t
a
l
3P
3Z co
nt
r
o
l
l
e
r wi
t
h
sam
p
l
i
ng peri
o
d
, t
h
e f
o
l
l
o
wi
ng
di
gi
t
a
l
3P3Z co
nt
r
o
l
al
gori
t
hm
can
b
e
ob
tain
ed
b
y
transfo
r
min
g
th
e typ
e
-3
co
n
t
ro
ller
t
o
d
i
screte tim
e u
s
in
g
b
ilin
ear t
r
an
sform
a
t
i
o
n
[2
]. Th
e
resp
ectiv
e d
i
g
ital co
m
p
en
sator is g
i
v
e
n b
y
:
C
onse
q
uent
l
y
t
h
e
di
scret
e
t
i
m
e-d
o
m
a
i
n
equa
t
i
on
fo
r t
h
e
o
u
t
put
o
f
t
h
e
com
p
en
sat
o
r
i
s
obt
ai
ned a
s
:
W
h
er
e e (n
-3
),
e(n
-
2
)
.
e
(n
-1
),
e(
n)
are the error signals of the
,
,
&
sam
p
le
r
e
sp
ectiv
ely. y
(
n-
3)
,y(n-
2
)
,
y(n
-
1
)
is
the
duty cycle command st
ored from
previous cy
cles, y(n) is t
h
e curre
nt
duty cycle command whic
h is the controller output for n
th
sam
p
l
e
. For
t
h
e dsP
I
C
DS
C
im
pl
em
ent
a
ti
on
of
architecture, the cont
roller c
o
-efficient A
0
,A
1
, A
2
, A
3
, B
1
, B
2
, B
3
uses fi
x
e
d val
u
es & a
r
e det
e
rm
i
n
ed o
ffl
i
n
e
fr
om
t
h
e wel
l
-
desi
g
n
e
d
c
ont
r
o
l
l
e
r t
o
be
di
sc
usse
d i
n
ne
xt
s
ect
i
o
n
Fi
gu
re
1.
Ty
pi
cal
di
gi
t
a
l
co
nt
rol
sy
st
em
bl
oc
k
di
ag
ram
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l.
6
,
No
.
4
,
D
ecem
b
er
2
015
:
78
8 – 796
79
0
4.
3
P
3
Z
CONT
ROLLER
DESIGN
To
d
e
sign
th
e
3
P
3
Z
co
n
t
ro
ller
fo
r
sy
n
c
h
r
o
n
o
u
s
bu
ck
conver
t
er
; a lin
ear
i
zed
m
o
d
e
l o
f
th
e p
l
an
t is
devel
ope
d t
o
o
b
t
a
i
n
t
h
e
pl
a
n
t
m
odel
.
4.
1.
Power s
t
age
model
For t
h
e ge
nera
l
buc
k co
nve
rt
er, t
h
e sm
al
l
signal
c
ont
r
o
l
t
o
out
p
u
t
t
r
a
n
sfe
r
fu
nct
i
o
n
i
s
gi
ve
n
b
y
[3
].
(
5
)
The follo
win
g
param
e
ters
are
considere
d
for the
m
odel.
V
i
=9V, R=5
Ω
, V
0
=5V
±
0.
5%,
r
c
=25m
Ω
, r
L
=38m
Ω
, L=10µ
H, C
=
3
00µ
F.S
w
i
t
c
hi
n
g
fre
q
u
e
ncy
and
sam
p
l
i
ng f
r
eq
ue
ncy
.
W
i
t
h
the
s
p
ecified
param
e
ter
i
s
g
i
ven
by
:
(6)
4.
2.
Contr
o
ller model
The system
transfe
r
function
has
t
w
o c
o
m
p
l
e
x c
o
n
j
ugat
e
pol
es
an
d
o
n
e
zero
i
n
t
r
o
duce
d
b
y
cap
acito
r esr.
A typ
e
3
con
t
oller is u
s
u
a
lly req
u
i
red to
co
mp
ensate th
e syste
m
.
(7)
Eq
uat
i
on
(7
) s
h
o
w
s a t
y
pe
3 cont
rol
l
e
r, i
t
’
s a
com
b
i
n
ation of PI c
o
m
p
ensator, Lead c
o
m
p
ensator a
nd
an extra
pole
whic
h is used t
o
com
p
ensate capacitor es
r zer
o
.
A t
y
pe 3 c
ont
rol
l
e
r h
a
s t
h
e adva
nt
ages
o
f
a
lead and la
g c
o
m
p
ensator.
At low
fre
quenc
i
es, the c
o
m
p
ensator inte
grat
es
t
h
e e
r
r
o
r
si
gnal
,
l
eadi
ng t
o
very
hi
g
h
l
o
w
fre
q
u
e
ncy
l
o
op
g
a
i
n
an
d acc
urat
e
r
e
gul
at
i
o
n
of
o
u
t
p
ut
v
o
l
t
a
ge
.
At
hi
gh
f
r
eq
ue
ncy
t
h
e c
o
m
p
ensat
o
r
in
trodu
ces
p
h
a
se lead
i
n
to
t
h
e lo
op
g
a
in.
4.
2.
1.
Contr
o
ller des
i
gn
Fi
rst
desi
g
n
st
ep f
o
r a di
gi
t
a
l
cont
r
o
l
l
e
r i
s
sel
ect
i
ng t
h
e app
r
op
ri
at
e sam
p
l
i
ng
fre
que
nc
y
.
For l
o
w
swi
t
c
hi
n
g
fre
q
u
enci
es
sam
p
l
i
ng
f
r
e
que
ncy
i
s
sam
e
as swi
t
c
hi
n
g
fre
q
u
enc
i
es, b
u
t
as
we
go
f
o
r
hi
g
h
s
w
i
t
c
hi
n
g
fre
que
ncies it may not be possible to s
a
mple the outp
ut
every PWM
cycle because
of
processi
ng tim
e
constraints. In
this case sam
p
ling
fre
quency i
s
take
n as
1/3
rd
of
sw
itch
i
ng
fr
equ
e
n
c
y wh
ich
is
13
3 KH
z.
Th
is
ens
u
res
that
duty is updated once in every
3
PW
M cycles
. The pl
ant
t
r
ans
f
er f
unct
i
o
n gi
ven
i
n
e
q
uat
i
o
n (6
)
i
s
u
s
ed
to d
e
si
g
n
a Typ
e
-3
con
t
ro
ller. Th
e
fo
llowing
d
e
sign
criteria
m
u
st satisfy.
The gai
n
at
l
o
w f
r
eq
ue
ncy
sho
u
l
d
be
hi
g
h
eno
u
gh
t
o
minimize the steady stat
e error. The c
r
oss
over
fre
que
ncy
of
t
h
e cl
ose
d
l
o
o
p
s
y
st
em
shoul
d
b
e
l
o
we
r t
h
an
o
n
e t
h
i
r
d
o
f
t
h
e
sam
p
l
i
ng fre
q
u
e
ncy
[
4
]
.
The
p
h
ase m
a
rgi
n
o
f
t
h
e
com
p
en
sat
e
d sy
st
e
m
shoul
d
be
ab
ove
4
5
0
[5
].
Next step is to
com
p
ensate the capacitor es
r
zero
by
placing a pole exactly
on the zero. Capacitor es
r
zero
en
ha
nces
hi
g
h
fre
q
u
enc
y
gai
n
a
n
d i
t
need
s t
o
be
c
o
m
p
ensat
e
d.
F
i
gu
re (
2
a
)
s
h
o
w
s t
h
e
b
o
d
e
p
l
ot
o
f
capacitor es
r c
o
m
p
ensated sy
ste
m
and Figure (2b) show
s
the step res
ponse. Ta
ble 1 s
h
ows the c
o
mparis
on
bet
w
ee
n
obt
ai
n
e
d s
p
eci
fi
cat
i
o
n a
n
d
t
h
e
desi
r
e
d s
p
eci
fi
cat
i
o
n.
Ti
m
e
d
o
m
ain
sp
ecification
s
lik
e ov
ershoo
t, settlin
g
tim
e
an
d stead
y
state erro
r are
d
e
p
e
nd
en
t
on
closed l
o
op da
m
p
ing factor
Ɛ
. E
quat
i
o
n
(8
) sh
o
w
s t
h
e re
l
a
t
i
on bet
w
ee
n
phase m
a
rgi
n
(
ɸ
)
and
closed loop
dam
p
i
ng fact
o
r
[3]
whe
r
e
.
(
8
)
Ov
ersh
oo
t is a
critical d
e
sign
p
a
ram
e
te
r, f
o
r
10
% o
v
e
r
sh
o
o
t
dam
p
i
ng
fact
o
r
Ɛ
=0
.6
, thu
s
th
e requ
ir
ed
p
h
a
se m
a
rg
in
is
. Here th
e
phase
m
a
rg
in
is fix
e
d
to
to obt
ain an overshoo
t less th
an
10%. On
ce th
e
pha
se m
a
rgi
n
i
s
fi
xe
d
next
st
e
p
i
s
sel
ect
t
h
e
gai
n
c
r
os
s o
v
e
r
fre
que
ncy
(
). i
t
m
u
st b
e
way
b
e
low th
e
Nyqu
ist
rat
e
.
Ty
pi
cal
l
y
bet
w
ee
n 1/
6
th
to
1
/
1
0
th
of
sam
p
lin
g fr
equ
e
n
c
y, h
e
r
e
is tak
e
n
as 15
KHz.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
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:
208
8-8
6
9
4
Developme
nt
of Digital C
ontr
o
ller for
DC-DC Buck C
o
nver
ter (Sar
un
Soman)
79
1
4.
2.
2.
Desi
gn
o
f
l
e
ad
com
p
ens
a
t
o
r
.
From
t
h
e p
h
as
e pl
ot
i
n
Fi
g
u
r
e
2a i
t
can
be
obs
er
ved
t
h
at
pha
se at
1
5
K
H
z
i
s
.
On
c
e
th
e g
a
in
cro
ss
ov
er frequ
c
n
y
is fix
e
d
to
15
KHz th
e
ph
ase m
a
rg
in
will co
m
e
d
o
w
n
to
fr
om
.The r
e
qui
red
pha
s
e
marg
in
is
pl
us
a
m
a
rgi
n
of
to com
p
ensate any lag that oc
cur in
later stag
e of d
e
sign
.
Thu
s
th
e lead
com
p
ensat
o
r
m
u
st
provi
de
a phase l
e
a
d
o
f
Ɵ
=
=
at
fre
que
ncy
.
Z
e
r
o
o
f
lead
com
p
ensator
m
u
st be place
d at
and p
o
l
e
at
.The
pol
e
and zer
o p
o
s
i
t
i
on can be c
a
l
c
ul
at
ed usi
n
g
equat
i
o
n (
9
)
a
n
d (1
0)
, whe
r
e
Ɵ
=
.
(
9
)
(10)
Table 1
Para
m
e
ter
Capacitor esr
co
mpensated syte
m
specif
i
cation
Desired Specif
acti
o
n
Gain over
fr
equency
(
7.3KHz 15KHz
Phase Ma
rgin (
ɸ
)
Settling ti
m
e
1.1
m
s
600µs
Final value
4.
22V
5V
Over
shoot
78.
8%
<10%
Fi
gu
re
2a.
B
o
d
e
pl
ot
ca
paci
t
o
r es
r c
o
m
p
ensat
e
d sy
st
em
Fig
u
r
e
2b
.
Step r
e
sp
on
se of
ca
pacitor esr com
p
ensated syste
m
The zero is pl
aced at 2.9 KHz and pole at
77.2
KHz
. T
h
e lead com
p
ensator tra
n
sfe
r
function thus
obt
ai
ne
d i
s
sh
o
w
n
i
n
e
q
uat
i
o
n
(
1
1
)
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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088
-86
94
I
J
PED
S
Vo
l.
6
,
No
.
4
,
D
ecem
b
er
2
015
:
78
8 – 796
79
2
(
1
1)
The freque
ncy response and step response
of th
e syste
m
after adding the lead com
p
ensator is
depi
ct
ed
i
n
Fi
gu
re
(3a
)
a
n
d
(3
b)
res
p
ect
i
v
e
l
y
.
Gai
n
c
r
oss
over frequce
n
cy and ph
ase marg
in
is as per
th
e
d
e
sign
requ
iremen
ts. Step resp
on
se shows
th
at ov
ersho
o
t
h
a
s co
m
e
d
o
wn to
21
% and
settlin
g ti
m
e
has
im
pro
v
ed t
o
1
33µs
.
Fr
om
t
h
e freq
u
e
n
cy
re
spo
n
se i
t
seen
t
h
at
l
o
w fre
q
u
cny
gai
n
i
s
o
n
l
y
14
dB
. Fo
r
go
od
reject
i
o
n
o
f
l
o
w f
r
e
que
ncy
n
o
i
s
e a
n
d
bet
t
e
r
reg
u
l
a
t
i
o
n
t
h
e l
o
w
f
r
eq
ue
ncy
gai
n
m
u
st
be
4
0dB
o
r
great
er
.
Fi
gu
re
3a.
Fre
q
uency
res
p
o
n
se
wi
t
h
l
e
a
d
c
o
m
p
en
sat
o
r
Figure
3b.
Step res
p
onse
woth lead c
o
m
p
ens
a
tor
Lo
w fre
que
nc
y
gai
n
can be im
pro
v
ed by
a
ddi
ng a PI c
o
m
p
ensat
o
r.
Whi
l
e addi
n
g
a PI com
p
ensat
o
r
two a
s
pects
ne
eds t
o
be take
n care, the c
r
oss
over freque
nc
y
m
u
st
not
shi
f
t
fr
om
15K
Hz,
t
h
e p
h
ase
m
a
rgi
n
m
u
st
not
com
e
bel
o
w
as PI
will in
trod
u
c
e
p
h
a
se lag
.
Th
e zero of
PI com
p
en
sato
r is arb
itarly tak
e
n
as
. Equ
a
tio
n (1
2)
sh
ow
s t
h
e PI
co
m
p
en
sato
r
(
1
2)
B
y
com
b
i
n
i
ng
t
h
e P
I
a
n
d
l
ead
com
p
ensat
o
r t
y
pe 3
co
nt
r
o
l
l
e
r t
r
a
n
sfe
r
fu
nct
i
on i
s
gi
ven
by
eq
uat
i
o
n
(
1
3)
(13)
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Developme
nt
of Digital C
ontr
o
ller for
DC-DC Buck C
o
nver
ter (Sar
un
Soman)
79
3
The f
r
eq
ue
ncy
resp
on
se an
d st
ep res
p
o
n
se f
o
r t
h
e
desi
g
n
e
d
t
y
pe-
3
co
nt
r
o
l
l
e
r i
s
sho
w
n i
n
Fi
gu
re
4
a
and
4b res
p
ec
tively. The syste
m
parem
e
te
rs of the
com
p
ensated system and th
e des
i
red s
p
ecification i
s
depicted in Ta
ble-2. T
h
e c
o
m
p
ensated
syste
m
m
eets the de
sired specificat
ions
.
On
ce th
e s-domain
tran
sfer fun
c
tion
is availab
l
e
it can
b
e
con
v
e
rted
t
o
z-d
o
m
ain
u
s
in
g
b
ilin
ear
t
r
ans
f
o
r
m
a
ti
on.
The
di
scret
e
t
i
m
e
t
r
ansfe
r
f
u
nct
i
o
n
i
s
gi
ve
n
by
e
quat
i
o
n
(1
4)
. A
3
p
o
l
e
-
2
z
e
ro t
r
ans
f
e
r
f
u
nct
i
o
n
in
s-do
m
a
in
tran
sfers t
o
3
-
po
le-3-zero
i
n
th
e
z-d
o
m
a
i
n
whi
c
h i
s
k
n
o
w
n as
3p
3z c
o
nt
r
o
l
l
e
r
.
(
1
4)
Fi
gu
re
4a.
B
o
d
e
Pl
ot
fo
r B
u
ck
co
nve
rt
er
wi
t
h
Ty
pe-
3
c
o
nt
r
o
l
l
e
r
Fig
u
r
e
4b
.
Step r
e
sp
on
se fo
r Bu
ck Conv
er
ter
typ
e
-
3
con
t
ro
ller
Table-2
Para
m
e
ter
Co
m
p
ensated s
y
st
e
m
specif
i
cation
Desired
specif
i
cation
Gain over
fr
equency
(
14.
6 KHz
15KHz
Phase Ma
rgin (
ɸ
) 69.
6
0
70
0
Settling ti
m
e
596µs
600µs
Final value
5V
5V
Over
shoot
5.
25%
<10%
5.
SIMULATION AND RESULTS
Th
is sectio
n
describ
e
s th
e con
t
ro
l circu
it and
t
h
e
powe
r st
age a
n
d
how the
overall syst
e
m
can
be
m
o
d
e
lled
u
s
ing Sim
u
lin
k
.
Aft
e
r th
at it
p
r
esen
t and
d
i
scu
sses th
e
ob
tain
ed resu
lts.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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-86
94
I
J
PED
S
Vo
l.
6
,
No
.
4
,
D
ecem
b
er
2
015
:
78
8 – 796
79
4
5.
1.
Digital c
o
ntr
o
ller model
Fi
gu
re 5 s
h
ow
s t
h
e Si
m
u
l
i
nk m
odel
of b
u
ck
con
v
e
r
t
e
r i
n
st
eady
st
at
e. The
m
odel
i
s
deve
l
ope
d usi
n
g
st
eady
st
at
e i
n
duct
o
r
v
o
l
t
a
ge
equat
i
o
n a
n
d c
a
paci
t
o
r
cu
rre
n
t
equat
i
o
n.
C
l
o
s
ed l
o
o
p
buc
k
con
v
e
r
t
e
r
wi
t
h
di
gi
t
a
l
co
n
t
ro
ller is im
p
l
e
m
en
ted
as shown in
Fig
u
re
6
.
Usu
a
lly a Dig
ital Si
g
n
a
l C
o
n
t
ro
ller (DSC
) is
u
s
ed
d
i
g
ital
co
n
t
ro
ller
n
e
ed to
to b
e
realized
in h
a
rd
ware. A DS
C will
h
a
v
e
in
bu
ilt ADC t
o
d
i
g
itize th
e
o
u
t
p
u
t
fro
m
th
e
sy
st
em
, a DSP
en
gi
ne t
o
i
m
pl
em
ent
t
h
e co
n
t
rol
l
a
w a
n
d
D
P
W
M
bl
oc
k t
o
ge
nerat
e
t
h
e
desi
re
d P
W
M
wi
t
h
dut
y
c
ont
rol
l
e
d as
pe
r c
ont
r
o
l
l
a
w
[
6
]
.
Fi
g
u
re
6
sh
o
w
s
h
o
w
t
h
e e
n
t
i
r
e
sy
t
e
m
can be
m
odel
l
e
d i
n
Si
m
u
li
nk.
Thi
s
m
odel
e
n
abl
e
s
us t
o
ve
ri
fy
t
h
e c
o
nt
rol
l
e
r
per
f
o
r
m
a
nce bef
o
re
g
o
i
n
g
f
o
r
act
ual
har
d
ware
t
e
st
i
ng.
The s
p
eci
fi
cat
i
on
o
f
ds
PIC
3
3
F
DSC
fr
om
M
i
crochi
p Tec
h
n
o
l
o
gy
i
s
t
a
k
e
n t
o
m
odel
t
h
e cont
rol
l
e
r
.
The output
vol
t
age of
t
h
e buc
k
co
nv
erter is
scaled
d
o
wn
to 3V
b
y
th
e
senso
r
n
e
t
w
ork
.
Th
is is
requ
ired
as th
e
ADC
vo
ltag
e
ran
g
e
is 0
t
o
3.3
V
t
h
is is b
ecau
s
e
Dig
ital Sign
al Con
t
ro
llers typ
i
cally u
s
e 3
.
3
V
supp
ly Th
e 10-
bi
t
ADC
i
s
m
odel
l
e
d usi
n
g zer
o-
or
de
r hol
d, A/
D q
u
a
nt
i
zer, A/
D
l
i
m
i
t
e
r bl
ocks
.3P
3
Z c
ont
rol
l
er i
s
im
pl
em
ent
e
d wi
t
h
t
r
a
n
s
f
er
f
unct
i
o
n
bl
ock
.
The
16
-b
it
DPW
M
m
o
du
le
is m
o
d
e
lled
u
s
in
g DPWM
quan
tizer
an
d DPW
M
li
miter b
l
o
c
k
s
.
DPW
M
limiter
restricts th
e
d
u
t
y
bet
w
ee
n
7
5
% a
n
d
10%
p
r
eve
n
t
i
n
g f
u
l
l
y
o
n
a
n
d
fu
lly o
f
f co
nd
i
tio
n
of th
e Mo
sfet.
Th
e t
r
ansp
ort d
e
la
y
bl
ock m
odel
s
t
h
e t
i
m
e
bet
w
een sam
p
l
i
ng t
h
e er
r
o
r
sig
n
a
l and
updatin
g
th
e du
ty cycle co
mm
an
d
wh
ich
is appr
ox
im
ate
l
y 3
µ
s. A
pu
lsatin
g
l
o
ad
is in
co
rpo
r
ated
to
test th
e lo
ad
tran
sien
t
b
e
h
a
v
i
o
r
.
Fi
gu
re
5.
St
ead
y
st
at
e
m
odel
o
f
B
u
c
k
C
o
nve
r
t
er
Fi
gu
re
6.C
l
o
s
e
d
l
o
o
p
m
odel
o
f
B
u
c
k
C
o
nve
r
t
er
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
PED
S
I
S
SN
:
208
8-8
6
9
4
Developme
nt
of Digital C
ontr
o
ller for
DC-DC Buck C
o
nver
ter (Sar
un
Soman)
79
5
5.
2.
Simula
ti
o
n
Results
Th
e co
n
t
ro
ller
effev
tiv
eness i
s
tested
u
s
i
n
g a lo
ad
tran
sien
t.
W
h
en
t
h
ere is
su
dd
en
ch
ang
e
in
lo
ad
th
e
o
upu
t will h
a
ve a h
a
v
e
an
overshoo
t o
r
v
o
l
t
a
g
e
droop
. Th
e syte
m
m
u
st th
en
rev
c
ov
er sm
o
o
t
h
l
y to
its
stead
y
sat
e
val
u
e
[
7
]
.
The
rec
ove
ry
t
i
m
e
i
s
depen
d
ent
o
n
t
h
e
ba
nd
wi
dt
h
of t
h
e
co
nt
rol
l
e
r
w
h
i
c
h i
s
i
n
ve
rse
o
f
w
h
ich
is ar
ound
6
6
µ
s. Fi
g
u
r
e
6
sh
ow
s th
e l
o
ad
tr
an
sien
t
r
e
sp
on
se ob
tain
ed u
s
i
n
g Sim
u
lin
k
m
o
d
e
l fo
r the lo
ad
cur
r
ent
c
h
an
ge
s fr
om
0.1A t
o
1A a
nd
1
A
t
o
0.
1A
res
p
ect
i
v
ely. It can be
observe
d
th
at the lo
ad
tran
sient tak
e
ab
ou
t 3
0
µ
s
to co
m
p
lete
wh
ich
is with
in
th
e ex
p
ected
v
a
lu
e
66
µs.
Th
e start-up
tran
sien
t is show
n
i
n
Figu
re
8. It is o
b
s
erv
e
d th
at o
u
t
pu
t voltag
e
settles to
5
V
i
n
aro
und
80
0µs.
A 13
% out
p
u
t
v
o
l
t
a
ge o
v
ers
h
oot
i
s
present
w
h
i
c
h can
be r
e
duce
d
by
i
n
c
o
r
p
orat
i
n
g so
f
t
st
art
.
Si
m
u
latio
n
resu
lts are
fav
o
rab
l
e
fo
r actu
a
l
hardware testin
g.
Th
e sim
u
latio
n
resu
lts sho
w
t
h
at th
e co
n
t
ro
l
l
er is efficien
t. Th
e ou
pu
t voltag
e
is well r
e
g
u
l
ated
at
5V. T
h
e
res
p
onse is
fast
whe
n
s
u
bjecte
d
to
disturt
b
ance
.
Fig
u
re
7
.
Lo
ad tran
sien
t respon
se
ob
tain
ed with
Sim
u
lin
k
mo
d
e
l
Fi
gu
re
8.
St
art
-
up
t
r
a
n
si
ent
ob
t
a
i
n
ed
wi
t
h
Si
m
u
li
nk m
odel
6.
CO
NCL
USI
O
NS
Th
is p
a
p
e
r d
e
scrib
e
s co
m
p
lete d
e
sig
n
an
d
i
m
p
l
e
m
en
tattio
n
o
f
a d
i
g
ital co
n
t
ro
ller fo
r
bu
ck
co
nv
erter.
A desi
g
n
exam
pl
e base
d
on a
sy
nch
r
o
n
ous
buc
k c
o
n
v
e
r
t
e
r
ope
rat
i
n
g at
t
h
e swi
t
c
hi
n
g
f
r
e
que
ncy
o
f
40
0 K
H
z
i
s
prese
n
t
e
d. T
h
e co
nt
r
o
l
l
e
r d
e
si
gn i
s
base
d
on
di
rect
di
gi
t
a
l
desi
gn a
p
p
r
o
ach an
d st
an
da
rd f
r
e
que
ncy
d
o
m
a
i
n
desi
g
n
t
e
c
hni
q
u
es.
Si
m
u
l
a
t
i
o
n re
sul
t
s
a
r
e s
h
o
w
n t
o
val
i
d
at
e t
h
e de
si
g
n
ap
pr
oac
h
.T
he
de
vel
o
ped
Si
m
u
li
nk
m
odel can be used to m
odel any DSC as the
specifications
chan
ge
wi
t
h
t
h
e ven
d
o
rs
. Fu
rt
her
wo
rk
nee
d
s
t
o
be
do
ne t
o
i
m
pl
em
ent
t
h
e con
v
e
rt
er l
o
gi
c usi
ng a
di
gi
t
a
l
si
gnal
c
ont
rol
l
e
r
and t
e
st
a p
r
o
t
ot
y
p
e B
u
c
k
C
o
n
v
e
r
t
e
r
with
sam
e
sp
ecificatio
n
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-86
94
I
J
PED
S
Vo
l.
6
,
No
.
4
,
D
ecem
b
er
2
015
:
78
8 – 796
79
6
REFERE
NC
ES
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Cristophe Basso, ”Switch-Mode Power S
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ducation
,
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IS
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9780071823463
[2]
Martin,
TW., S
S
. Ang, “Digital contro
l for s
w
itching
conver
t
ers”, In Proceedings of the I
E
EE International
S
y
mposium on Industrial Electro
nics
,
vo
l. 2, pp.
480–484, 1995
.
[3]
R. Erickson, D.
Maksimovic, ”Funda
mentals of
Power Electronics”, 2
nd
ed
. Norwell, MA:Kluwer, 2000. ISBN:
0-
7923-7270-0.
[4]
Peterch
e
v, AV.,
SR. Sanders, “Quantizat
ion resolution and
limit cy
cling
in di
g
itally
controlled
PWM converters”,
IEEE Transactio
ns on Power
Electronics,
vol. 18
, pp. 301–308, 20
03.
[5]
Lopez-S
a
n
t
os
O
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u
rci
a
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a
rrero
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M
., ”D
i
g
ital Con
t
ro
l of
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i
ngle P
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as
e
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ier
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act
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,
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BIOGRAP
HI
ES OF
AUTH
ORS
Sar
un Soman
,
rece
ived the E
l
e
c
troni
cs
Enginee
r
ing Degree fro
m
Kerala Univers
i
t
y
, Keral
a
,
India in 2007, and the M.Tech
degree in Po
wer Electronic Sy
stems & Control from the
Manipal Institu
t
e
of Technolog
y, Manipal
,
India,
in 2010. He is currentl
y
a ful
l
ti
m
e
professo
r
in the Departm
e
nt of Elect
ric
a
l
& Elec
troni
cs
. His
res
earch int
e
res
t
s
are in di
gital con
t
rol
,
digital sign
al p
r
o
cessing and
pow
er electronics.
Sange
e
t
ha T.
S.
,
rece
ived
the C
o
m
puter S
c
ienc
e and Eng
i
ne
er
ing from
Kerala
Univers
i
t
y
,
Kerala, India in
2008, and th
e M.Tech d
e
gree
in Computer Science and Eng
i
n
eering from
Visvesvaray
a
Technological
Universi
ty
, Belg
au
m, India, in 201
3. She is
currently
working
as a
professor in the department of
Informati
on and
Communication Technolog
y
.
Her resear
ch
inter
e
sts ar
e pa
ra
llel
com
pu
ting
and embedded
s
y
stems.
Evaluation Warning : The document was created with Spire.PDF for Python.