TELKOM
NIKA
, Vol.14, No
.2, June 20
16
, pp. 497~5
0
6
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v14i1.3042
497
Re
cei
v
ed
No
vem
ber 1
5
, 2015; Re
vi
sed
April 22, 201
6; Acce
pted
May 3, 201
6
State-space Modelling and Digital Controller Design for
DC-DC Converter
Oladimeji Ibrahim*
1
, Nor Zaihar Yahay
a
2
, Nordin Saad
3
Electrical
and
Electron
ics En
gin
eeri
ng D
epa
rtment, Univers
i
ti T
e
knologi P
E
T
R
ONAS,
Band
er Seri Iskand
er, 326
10,
Perak, Mala
ys
ia
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: reacho
lai
b
ra
him@gm
ail.co
m
1
, n
o
r
za
i
h
a
r
_y
ah
ay
a@
pe
tron
a
s
.co
m
.my
2
,
nord
i
ss@p
e
tro
nas.com.m
y
3
A
b
st
r
a
ct
T
he rec
ent d
e
v
elo
p
m
ent
in
digit
a
l tec
h
n
o
l
ogy
offers bett
e
r pl
atform for
easy
i
m
pl
e
m
e
n
tation
of
adva
n
ce co
ntrol al
gorith
m
in
pow
er conv
erter desi
gn
mak
i
ng di
gita
l contr
o
l a via
b
l
e
alter
native to a
nal
o
gue
counter
part.
C
ontrol
l
er desi
g
n
for pow
er converters
ha
s be
en v
e
ry
chall
e
n
g
in
g
d
ue to
no
n-li
n
ear
character
i
stics
of pow
er sw
itc
hes, the
su
ppl
y volta
ge
v
a
ri
a
b
ility, l
o
a
d
c
u
rrent ch
an
ges
a
nd c
i
rcuit
ele
m
ent
variati
on. T
h
is pap
er prese
n
ts
dyna
mic av
era
ged st
ate-sp
ac
e mo
de
lli
ng of non-
ide
a
l dc-
d
c boost convert
e
r
w
i
th parasitic
and d
i
git
a
l co
ntroll
er desi
g
n
for boost
con
v
erter usin
g di
gital re
desi
gn
and d
i
rect di
gi
tal
design
m
e
thods. The syst
em
was
sim
u
lated in
Matlab
/Sim
ulink to investigate t
he dy
nam
i
c perfor
m
ance
of
the tw
o control
l
ers
’
trans
ie
nt respo
n
se, co
ntrol b
andw
idt
h
and r
e
spo
n
se
to varia
b
le s
u
p
p
ly volt
age. T
h
e
results d
e
m
ons
trated fast tran
sient a
nd w
i
de
control
ban
dw
idth for tight vo
l
t
age re
gul
atio
n
to varia
b
le
inp
u
t
voltag
e.
Ke
y
w
ords
:
dc-dc co
nvert
e
r, state-spac
e
mo
d
e
l,
dig
i
tal co
mpe
n
sat
o
r, close
d
l
o
o
p
resp
ons
e, c
ontro
l
ban
dw
idth
Copy
right
©
2016 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
Powe
r conve
r
ters found their ap
plications in
ne
arly
all electri
c
al
gadget
s by providin
g
necessa
ry powe
r
co
nversion an
d po
wer q
ualit
y improvem
ent for smo
o
th operatio
ns. Po
we
r
conve
r
ters al
so pl
ays imp
o
rtant role in
r
ene
wa
ble
energy syste
m
s by
p
r
ovi
d
ing n
e
cessary
control in
stabilizing the variabl
e generated output [1]. The generat
ions from renewable
energy
resou
r
ces a
r
e cha
r
a
c
teri
zed by chan
ging dy
nami
cs
with varying output voltage, cu
rre
n
t,
freque
ncy
an
d po
we
r
whi
c
h de
mand
s a
d
vance
cont
rol sch
e
me
s t
o
fully tap
th
eir
potential
s
[2,
3]. Increa
sin
g
ele
c
troni
cs interface h
a
s
cont
ri
bute
d
immen
s
ely
to small a
nd large
scale
rene
wa
ble e
nergy
deploy
ment by p
r
o
v
iding be
tte
r con
d
itionin
g
with imp
r
ov
e efficien
cy
and
diverse suita
b
ility for wide rang
e of load
appli
c
ation.
The
swit
ch
mode
co
nve
r
ter to
polo
g
i
e
s
are
wi
d
e
ly used i
n
ene
rgy
co
nversi
on
appli
c
ation
s
owin
g to the
advantag
e hi
gh efficie
n
cy.
The
co
nvert
e
r top
o
logy i
s
an a
r
rang
em
ent
of powe
r
swi
t
ching d
e
vice
s and the m
agneti
c
elem
ents which form
s the po
wer m
odule.
In
addition to th
e po
wer ci
rcu
i
t, there is
a control
uni
t re
spon
sible fo
r p
o
we
r flow re
g
u
lation to m
e
et
the output vo
ltage re
qui
re
ment. The
co
ntrolle
r de
sig
n
ha
s be
en
very ch
alleng
ing du
e to n
on-
linear n
a
ture
of powe
r
switchin
g eleme
n
t
s, vari
ation of supply voltage and lo
ad
current [4-6]
.
The impl
eme
n
tation the
control
unit is achi
evabl
e
via analo
gue
or
digital
co
ntrol inte
grat
ed
circuit. Th
e a
nalog
ue te
ch
nique
ha
s b
e
en
widely u
s
e
d
till re
ce
nt time du
e to its
desi
gn
simpli
city
and hig
h
co
ntrol ban
dwi
d
th [7-9]. Th
e techni
que
has di
sa
dvan
tages of la
rg
e numbe
r pa
rts,
compl
e
x hard
w
are configu
r
ation,
and
se
nsitivity to environme
n
t in terms
of thermal and
agei
ng
[10, 11]. Re
cently, the interest i
n
digital
control
of p
o
w
er converte
r is gai
ning
po
pularity, credi
t to
high
sp
eed
microcontroll
ers a
nd
digit
a
l si
gnal
p
r
o
c
e
s
sor with
l
e
ss p
o
wer consumption
at low
co
st [12]. Dig
i
tal cont
rol
sy
stem a
r
e l
e
ss se
nsit
ivity to parametri
c v
a
riation, m
oni
toring
and
au
to
diagn
osin
g in
ope
ration
are po
ssible, fl
exible a
s
the
y
can
be
re
progra
m
to
different fu
nctio
n
an
d
compl
e
xity of
control is mo
ved fr
om hardwa
r
e to soft
ware [12, 13].
This pa
per p
r
ese
n
ts de
sig
n
and analy
s
i
s
of digital controlle
r for d
c
-d
c bo
ost converte
r
usin
g both
di
gital re
desi
g
n
and di
re
ct d
i
gital
de
sign approa
che
s
. A
non-i
deal boo
st
co
nverter
wa
s mo
delle
d u
s
ing
ave
r
age
d
state-spa
c
e
tech
ni
que
s which
are
pre
r
e
qui
site to effe
ct
ive
controlle
r design. The mod
e
l took in to consi
derat
ion the parasiti
c
param
eters of circuit eleme
n
t
s
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 497 – 50
6
498
in order to
ob
tain improved
dynami
c
mo
del for
e
ffecti
v
e cont
rolle
r
desi
gn. Th
e d
i
gital co
ntroll
ers
are
de
signe
d
usin
g the di
rect
digital d
e
sig
n
an
d di
gital red
e
si
gn
app
roa
c
h
using the M
a
tla
b
-
SISO_tool co
ntrol de
sig
n
tools. The
effectiv
ene
ss o
f
the
controll
ers on
the b
oost conve
r
ter
demon
strated
fast transi
ent respon
se
with
improv
es dynami
c
perfo
rman
ce
nece
s
sary for
eliminating
voltage flu
c
tu
ations
asso
ciated to
hi
g
h
ly variabl
e
voltage
so
urce li
ke
so
lar
photovoltai
c
system.
2.
Design a
nd Modelling of Boos
t Conv
erter
A DC-DC bo
ost co
nverte
r is a non
-i
solati
on po
we
r co
nverte
r that pro
d
u
c
e
s
output
voltage larg
er than the inpu
t voltage. Figure 1
sho
w
s t
he po
wer
circuit module an
d the cont
roll
er
unit which
can b
e
im
ple
m
ented
u
s
in
g digital
si
gn
al controller
(DS
C
). T
h
e
two
ba
sic co
ntrol
method
s a
r
e
the voltage a
nd current
co
ntrol mo
de. T
he voltage m
ode
control i
s
a
singl
e lo
op
control
syste
m
with
only o
u
tput voltage
used
as
con
t
rol si
gnal,
while
curre
n
t control
mod
e
i
s
a
multi-loo
p
co
ntrol with i
n
n
e
r current fee
dba
ck l
oop in
addition to t
he oute
r
voltage fee
dba
ck [5,
14]. The
sch
e
matic
of the
boo
st
conve
r
ter
sh
own
in
Figu
re
1 i
s
a voltage
mo
de
control, th
e
output voltag
e
which se
rves a
s
feedb
a
ck
i
s
se
nsed
by opt-isol
a
to
r
and transfo
rmed to
discrete
valu
es via
an
alog
ue to
digital
conve
r
ter (A
DC). Th
e
se
nse
d
voltag
e
is
co
mpa
r
ed
wit
h
the desi
r
ed
referen
c
e volt
age
to generate error
sign
al
. The error i
s
then p
r
o
c
e
s
sed by
a comp
en
sat
o
r
blo
c
k to
determi
ne th
e duty
cy
cl
e
of p
u
lse
wi
dth mo
dulati
on
(PWM
)
which
controls the
converte
r switchin
g
‘o
n
’
an
d
‘o
ff
’
period.
i
c(t
)
Vc
(
t
)
+
-
i
ou
t(t)
C
D
L
Co
m
p
en
s
a
t
o
r
Hy
b
r
i
d
DP
W
M
H
D
i
gi
t
a
l
S
i
g
n
al
P
r
oc
e
s
s
o
r
1
Q
PW
M
V
ou
t
(t
)
V
re
f
e
AD
C
V
o
(t)
R
L
i
L(
t
)
V
in
d(t)
i
in
(
t
)
Figure 1. Boost conve
r
ter
with digital co
ntrolle
r
2.1. Stead
y
State
Desig
n
To stu
d
y the
dynami
c
b
e
haviour of d
c
-dc bo
ost
co
nverter with
respe
c
t to th
e digital
controlle
rs, t
he
steady
st
ate an
d dyn
a
mic
mo
d
e
lli
ng for
conti
nuou
s
cu
rre
n
t mode
(CCM)
operation of non-i
deal b
o
o
s
t conve
r
ter a
r
e present
ed
in sub
-
sectio
n 2.1 and 2.2
.
Table 1 sho
w
s
the summ
ary
of the steady st
ate de
sign
example u
s
e
d
as case stu
d
y in the proj
ect.
Table 1. Steady state parameters
Parameters
S
y
mbol
Value
Input voltage
in
V
12 [V]
Output voltage
out
V
48 [V]
Output voltage
ripple
o
V
500 [mV]
Rated po
wer
o
P
500 [W]
Average output c
u
rrent
o
I
9.6 [A]
Sw
itch on r
e
sistance
on
R
0.1 [
Ω
]
Parasitic inductor resistance
L
r
0.01 [
Ω
]
Parasitic capacit
or resistance
C
r
0.01 [
Ω
]
Load resistance
L
R
5 [
Ω
]
Dut
y
c
y
cle
d
0.75
Inductor
L
90 [µH]
Output capacitor
C
100 [µF]
Sw
itching freq
ue
ncy
s
f
100 [kHz]
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
State-space Modelling an
d Digital Cont
roller Design
for DC-
DC
Converter (Oladim
e
ji Ibrahi
m
)
499
The detail
s
o
f
the steady st
ate de
sign
equatio
ns for dc-d
c bo
ost
conve
r
ters ha
ve been
pre
s
ente
d
in
[4-6]. A 500
W, 48V b
o
o
s
t conve
r
ter
was d
e
si
gn
with 12V n
o
min
a
l input
and
50% input v
a
riation. T
h
e
swit
chin
g freque
ncy of
p
u
lse width switchi
ng cont
rol
i
s
10
0
kHz
to
ensure
hig
h
power den
sit
y
by re
du
cin
g
filter
co
mp
onent
si
ze
a
nd the
loa
d
wa
s m
odelle
d a
s
resi
st
an
ce.
T
he
on
r
e
s
i
s
t
an
c
e
o
f
th
e
p
o
w
e
r sw
itc
h
, th
e
in
te
rn
a
l
r
e
s
i
s
t
an
ce
o
f
filte
r
in
d
u
c
t
or
and
cap
a
cito
r e
q
u
i
valent re
si
stance were all
con
s
id
ered f
o
r imp
r
ove
d
modellin
g an
d analy
s
is of
the
boo
st conve
r
ter.
2.2. D
y
namic
State Mod
e
l
Switchin
g
co
nverter is a
p
e
riodi
c tim
e
-v
ariant
syste
m
that
can be modelle
d
u
s
i
ng circuit
averagi
ng or
state sp
ace averagin
g
tech
nique [6].
The dynamic m
odel
s of conv
erters are useful
for co
ntroll
er
desi
gn, predi
cti
ng the
syst
em stability
margi
n
, and
f
o
r st
udying transi
ent re
sp
o
n
se
to sup
p
ly/loa
d pert
u
rb
atio
n [6]. It helps to pre
d
ic
t dy
namic beh
aviour
of the co
nverter
prio
r
to
system p
r
oto
t
yping to red
u
ce d
e
si
gn cycle ti
me an
d co
st. The state sp
ace averag
e mod
e
l
method i
s
u
s
ed to mo
de
l the non-i
d
e
a
l boo
st co
n
v
erter
con
s
id
ering
com
p
o
nents p
a
rasit
i
c
para
m
eters [15, 16]. This modelling te
chni
que give
s a co
mplete
converte
r m
odel with b
o
th
steady state (DC) and dynamic (AC)
q
uantities
and
the tran
sfer
f
unction
s of t
he converte
r
are
readily obtai
n
able for dyna
mi
c analy
s
is
of the system
.
Based
on blo
ck di
ag
ram in
Figure 1, the
switching p
e
r
iod for
com
p
l
e
te cycle i
s
d
enoted
is
s
f
T
1
and
d
is the duty cycle. T
he switch tot
a
l
on
-time i
s
dT
t
on
and
off-
time is
T
d
t
off
)
1
(
.
Whe
n
swit
ch
is
on
at ti
me interval
dT
,
by applying KVL and KCL, the differential state
variable
s
for
boo
st the con
v
erter a
r
e de
rived as follo
ws:
L
r
R
t
i
L
t
V
d
t
t
di
L
on
L
in
L
)
(
)
(
)
(
)
(
(1)
c
L
L
c
out
r
R
R
t
V
t
V
)
(
)
(
(2)
)
(
)
(
)
(
c
L
r
R
C
t
Vc
dt
t
dVc
(3)
The state
spa
c
e re
presenta
t
ion for the
on
-s
tate is
:
)
(
0
1
)
(
)
(
)
(
1
0
0
)
(
)
(
)
(
t
V
L
t
V
t
i
r
R
C
L
r
R
dt
t
dV
dt
t
di
in
c
L
c
L
L
on
c
L
(4)
)
(
)
(
)
(
0
)
(
t
V
t
i
r
R
R
t
V
c
L
c
L
L
out
(5)
Similarly, when switch
1
Q
is in
of-
state
at time interval
T
D
)
1
(
, applying
KVL and KCL, the
differential st
ate variable
s
for boo
st the conve
r
ter a
r
e
derived a
s
follows:
)
(
)
(
)
(
)
(
t
V
r
t
i
t
V
dt
t
di
L
out
L
L
in
L
(6)
c
//r
)
(
)
(
)
(
L
L
c
L
L
c
out
R
t
i
r
R
R
t
V
t
V
(7)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 497 – 50
6
500
L
r
R
R
t
V
L
R
r
t
i
L
t
V
dt
t
di
c
L
L
c
L
L
L
in
L
)
(
)
(
)
//r
(
)
(
)
(
)
(
c
(8)
)
(
)
(
)
(
t
i
t
i
t
i
out
L
c
(9)
)
(
)
(
)
(
)
(
)
)
(
c
L
c
L
c
L
L
r
R
C
t
V
t
i
r
R
C
R
dt
t
dVc
(10)
The state
spa
c
e re
presenta
t
ion for the
off
state is:
)
(
0
1
)
(
)
(
)
(
1
)
(
)
(
//
)
(
)
(
t
V
L
t
V
t
i
r
R
C
r
R
C
R
r
R
L
R
L
r
R
r
dt
t
dVc
dt
t
di
in
c
L
C
L
c
L
L
c
L
L
c
L
L
L
(11)
)
(
)
(
)
(
//
)
(
t
V
t
i
r
R
R
r
R
t
V
c
L
c
L
L
c
L
out
(12)
For dyn
a
mi
c
state an
alysi
s
an
d
control
l
er d
e
sig
n
for the bo
ost
co
nverter, the
converte
r
contin
uou
s-ti
me tran
sfe
r
functio
n
)
(
s
G
is o
b
tained
by p
e
rformi
ng
sta
t
e avera
g
ing
on the
state
equatio
ns
usi
ng the d
u
ty cycle
d
as weig
hting facto
r
.
The ave
r
ag
e
d
state
spa
c
e
equatio
ns fo
r a
conve
r
ter a
r
e
given by (13) and (14
)
[3], [17-18].
)
(
)
(
)
(
t
u
B
t
x
A
t
x
(13)
)
(
)
(
t
x
C
t
y
(14)
Whe
r
e, the state average
d matrix are
defined a
s
)
1
(
2
1
d
A
d
A
A
,
)
1
(
2
1
d
B
d
B
B
and
)
1
(
2
1
d
C
d
C
C
. The term
)
(
t
x
is the
co
n
v
erter
DC
st
ate vecto
r
d
e
fined a
s
in
d
u
ctors
curre
n
ts a
nd
cap
a
cito
rs vo
ltages,
)
(
t
u
is con
v
erter
DC i
n
put vecto
r
an
d
)
(
t
y
is the
co
nverte
r
DC o
u
tput vector.
The average
d matrix base
d
on stea
dy stat
e param
eters in T
able 1
is derived a
s
:
)
1
(
2
1
d
A
d
A
A
(15)
23
.
1996
01
.
2495
23
.
2772
17
.
972
A
(16)
)
1
(
2
1
d
B
d
B
B
(17)
0
1
.
11111
B
(18)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
State-space Modelling an
d Digital Cont
roller Design
for DC-
DC
Converter (Oladim
e
ji Ibrahi
m
)
501
)
1
(
2
1
d
C
d
C
C
(19)
9985
.
0
002495
.
0
C
(20)
Usi
ng the Ma
tlab state-spa
c
e (
ss
) to tran
sfer-fun
ction (
tf
), the converter cont
rol to output
contin
uou
s-ti
me tran
sfer f
unctio
n
is obt
ained a
s
(2
1):
07
20
6
27
.7
2
2
.
7
7
4
()
296
8
8
.8
57
se
Gs
s
se
(21)
3. Digital
Com
p
ensa
tor
De
sign
The t
w
o
app
roa
c
he
s for
desi
gning
dig
i
tal co
ntrolle
r are the
digit
a
l rede
sign
a
ppro
a
c
h
kno
w
n
as
de
sign
by emul
ation an
d direct digi
tal
de
sign
app
roa
c
h [6, 17]. De
sign
by emul
ation
employs
co
ntrol de
sig
n
in the co
ntinuo
u
s
time
s
-do
m
ain and th
en
transfo
rme
d
to discrete/dig
ital
z
-domai
n usi
ng any of the discretization met
hods such as backward Eul
e
r, bilinear
and
pole/zero m
a
tching
(Equat
ion 22-25
) [3, 6]. Digital rede
sign met
hod p
r
ovide
s
good respo
n
se
usin
g well kn
own
continu
o
u
s-tim
e
analo
gue de
sign
m
e
thod but suff
ers from discretization d
e
la
y
ef
f
e
ct
s.
The alte
rnati
v
e app
roa
c
h
is the
dire
ct
digital de
sig
n
whe
r
e
digita
l cont
rolle
r d
e
sig
n
is
done di
re
ctly in
z
-do
m
ain.
A switchin
g
action of a conve
r
ter i
s
con
s
id
ere
d
a
nd treated a
s
a
sampl
e
d
-
data
system l
e
a
d
ing to a
di
screte
-t
ime
model [6]. T
h
is a
pproa
ch
provide
s
go
od
transi
ent re
sp
onse with bet
ter pha
se ma
rgin an
d co
ntrol band
width
[18].
1
1
:
Ba
z
ckEul
e
r
s
T
s
amp
(22)
1
1
21
:
1
samp
z
Biline
a
r
s
T
z
(23)
:
1
1
Po
l
e
z
e
ro
M
a
t
c
hi
ng
aT
s
am
p
sa
z
e
(24)
2
12
12
c
o
s
sa
m
p
aT
aT
s
amp
sam
p
sj
a
z
e
b
T
z
e
(25)
Figure 4. Con
v
erter bo
de-p
l
ot with unity
feedba
ck
Figure 5. Con
v
erter ste
p
re
spo
n
se with u
n
ity
feedba
ck
-
150
-
100
-5
0
0
50
M
agn
i
t
u
de (
d
B
)
10
-1
10
0
10
1
10
2
10
3
10
4
-
180
-
135
-9
0
-4
5
0
P
has
e (
d
e
g
)
B
ode D
i
agr
am
G
m
=
I
n
f
,
P
m
=
52
.
7
de
g
(
a
t
1.
16 k
H
z
)
F
r
equ
enc
y
(
k
H
z
)
S
t
ep R
e
s
pon
s
e
T
i
m
e
(
s
ec
on
ds
)
A
m
pli
t
ud
e
0
1
2
3
4
x 1
0
-3
0
0.2
0.4
0.6
0.8
1
1.2
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 497 – 50
6
502
In order to p
r
edict th
e
clo
s
ed-lo
op
stabil
i
ty
of the con
v
erter, the
cl
ose
d
-lo
op f
r
e
quen
cy
and ste
p
re
spon
se with
u
n
ity feedback is pre
s
e
n
ted
in Figure 4 a
nd Figu
re 5
resp
ectively. The
bode
-plot h
a
s
infinite gai
n margi
n
(G
M), 52.7º ph
ase m
a
rgi
n
(PM) at 1.16
kHz cro
s
so
ver
freque
ncy. T
he
clo
s
ed
loo
p
ste
p
respo
n
se
sho
w
s th
at the
system
is
und
er
da
mped
with
so
me
oscillation
s. It has ste
ady state erro
r with
settling time of
3ms and a
bout 44% ove
r
sh
oot.
3.1. Digital Redesign
Con
t
roller
A pro
portio
n
a
l
-de
r
ivative (PD)
co
ntrolle
r is fi
rst de
sig
n
in
co
ntinuo
us time
do
ma
in u
s
in
g
the sy
stem
Z
i
egler Ni
ch
ol
freque
ncy
re
spo
n
se a
pproach a
s
deta
iled in
[19,
2
0
]. The
co
ntroller
desi
gn specif
ication i
s
set
at 10% oversh
oo
t, 23 kHz g
a
in cro
s
s-ove
r
freq
ue
ncy and ph
a
s
e
margi
n
of g
r
e
a
ter tha
n
6
0
º. The
de
sign
e
d
contro
ll
er i
s
furthe
r fine
-tuned
in the
M
a
tlab_SISO t
ool
environ
ment
via freque
ncy
bode
plot an
d then di
scre
tized u
s
in
g bi
linear
(Tu
s
tin
)
discretizatio
n
method. Th
e
Tustin a
p
p
r
o
x
imation met
hod
h
a
s the
advantag
e of
good m
a
tchi
ng bet
ween t
he
contin
uou
s a
nd discrete time model
s in
the frequen
cy domain [18].
The co
ntinuo
us-tim
e tran
sf
er functio
n
s o
f
the design
e
d
controlle
r
)
(
s
C
:
s
e
s
e
s
C
06
05
1
1
6
.
6
1
733
.
79
)
(
(26)
The e
quivale
nt digital
con
t
roller i
n
di
screte-time
do
main
)
(
z
C
is obtai
ned at
sam
p
l
i
n
g
time of
5
sec
o
n
d
s.
4286
.
0
1447
1560
)
(
)
(
)
(
z
z
z
e
z
U
z
C
(27)
The equival
e
nt difference equatio
n of
the controlle
r can be written as:
)
1
(
1447
)
(
1560
)
1
(
4286
.
0
)
(
k
e
k
e
k
U
k
U
(28)
3.2. Direct
Digital Design
Con
t
roller
The pl
ant
(bo
o
st
conve
r
ter) is first di
scretized
to
z
-d
o
m
ain u
s
in
g
zero
hold
o
r
de
r (ZHO)
at sampli
ng p
e
riod
of
5
se
co
nd. The digit
a
l cont
rolle
r i
s
then d
e
si
gn
ed in (p
se
ud
o-continu
o
u
s
)
w-pl
ane
u
s
in
g the
same
Ziegle
r
Nicho
l
freq
uen
cy
resp
on
se
app
roa
c
h
a
s
in
digital
rede
si
gn
approa
ch whi
c
h is late
r tra
n
sform ba
ck
equivalent
z-
domain [18, 2
1
].
The discrete-t
i
me tran
sfer f
unctio
n
of the plant is obtai
ned a
s
:
9853
0
985
1
0002058
0
0004826
0
)
(
2
.
z
.
z
.
z
.
z
G
(29)
With tra
p
e
z
oi
dal rule, the
plant tra
n
sfe
r
functi
on
is t
r
ansfo
rme
d
to
pse
udo
-conti
nuou
s d
o
mai
n
,
w-pl
ane
a
s
p
r
ese
n
ted in (3
8).
6
2
7
2
5
857
.
8
2968
774
.
2
46
.
41
973
.
6
)
(
e
w
w
e
w
w
e
w
G
(30)
The co
ntroll
er is then de
sig
ned in
w-
plan
which results in (39):
1
1
07
.
75
004955
.
0
)
(
6
w
e
w
w
C
(31)
The digital eq
uivalent of the controlle
r transfe
r functio
n
in
z-pl
ane
i
s
obtain
ed a
s
:
4286
.
0
1362
1469
)
(
)
(
)
(
z
z
z
e
z
U
z
C
(32)
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
State-space Modelling an
d Digital Cont
roller Design
for DC-
DC
Converter (Oladim
e
ji Ibrahi
m
)
503
The differe
nce equatio
n of the cont
rolle
r can b
e
writte
n as:
)
1
(
1362
)
(
1469
)
1
(
4286
.
0
)
(
k
e
k
e
k
U
k
U
(33
)
4. Resul
t
s
and
Discus
s
ions
4.1. Digital Redesign
Con
t
roller (DRC) Respo
n
se
The
step
an
d fre
quen
cy
respon
se
of t
he
cl
o
s
ed
lo
op p
e
rfo
r
man
c
e
of digital
rede
sig
n
controlle
r (DRC) o
n
the
boo
st co
nverter are p
r
e
s
e
n
ted in Fi
gur
e 6 an
d Fig
u
re
7. The
step
respon
se pl
ots of the sy
stem sho
w
s that the syste
m
is able
to achi
eve rise time of 15µs
and
settling time
of 200µ
s with
6% overshoo
t. The clo
s
ed
loop ph
ase m
a
rgin i
s
1
57º
with an
d co
ntro
l
band
width of
9.49 kHz.
Figure 6. Clo
s
ed lo
op ste
p
resp
on
se wit
h
DRC
Figure 7. Clo
s
ed lo
op bo
d
e
-plot with
DRC
4.2. Direct
Digital Con
t
rol
l
er (DDC) Re
spons
e
From th
e
clo
s
ed
loop
ste
p
and
bo
de-plot of
the b
oost conve
r
t
e
r with
di
re
ct
digital
controlle
r (DDC) in
Fig
u
re
8 a
nd
Figu
re
9
re
spe
c
ti
vel
y
. This
co
ntro
ller h
a
s an
im
proved
ri
se
time
of 10µs
with
settling time
of 160µ
s an
d 7% ov
ersh
oot. The p
h
a
s
e m
a
rgi
n
of
the freq
uen
cy
respon
se i
s
1
38º with
an i
m
prove
d
cont
rol ba
nd
width
of 16.5 kHz f
r
equ
en
cy and
a gain
margi
n
of 5.55dB.
Figure 8. Clo
s
ed lo
op ste
p
resp
on
se wit
h
DDC
Figure 9. Clo
s
ed lo
op bo
d
e
-plot with
DDC
Presented in
Table 2 i
s
t
he summa
ry of the
time a
nd freq
uen
cy
respon
se
of the two
controlle
rs, di
gital rede
sig
n
and dire
ct d
i
gital controll
er. The controller’
s re
sp
on
se sho
w
s th
at
there
were improvem
ents in the conv
erter
star
t u
p
tran
sient b
y
redu
cing
settling time and
0
1
2
3
x 1
0
-4
0
0.
2
0.
4
0.
6
0.
8
1
1.
2
1.
4
S
t
ep R
e
s
pons
e
T
i
m
e
(
s
e
c
onds
)
A
m
pl
i
t
ude
-4
0
-3
0
-2
0
-1
0
0
10
M
agni
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
-
180
-
135
-9
0
-4
5
0
P
h
as
e (
d
eg)
B
ode
D
i
agr
am
G
m
=
I
n
f
, P
m
=
157 deg (
a
t 9.4
9
k
H
z
)
F
r
eque
nc
y
(
k
H
z
)
S
t
ep
R
e
s
p
on
s
e
T
i
m
e
(
s
ec
on
d
s
)
A
m
pli
t
ud
e
0
1
2
3
x 1
0
-4
-0
.
2
0
0.2
0.4
0.6
0.8
1
1.2
-1
0
-5
0
5
M
agni
t
u
d
e
(
d
B
)
10
0
10
1
10
2
10
3
10
4
18
0
22
5
27
0
31
5
36
0
P
h
as
e (
d
e
g
)
B
o
de
D
i
a
g
r
am
G
m
=
5.55
dB
(
a
t I
n
f
k
H
z
)
, P
m
=
13
8 d
eg (
a
t 16
.5 k
H
z
)
F
r
e
que
nc
y
(
kH
z
)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 497 – 50
6
504
respon
se
ov
ershoot. T
h
e
settling
time
of the
digi
tal
red
e
si
gn
an
d direct
digit
a
l controll
ers are
200µ
s an
d 1
60 µ
s
respe
c
tively as ag
ai
nst that
co
nverter re
sp
on
se with
unity feedb
ack h
a
ving
13ms settling time. The di
rect digital
co
ntrolle
r ha
s
a
faster t
r
an
si
ent as
co
mp
ared
with th
a
t
of
digital re
desi
gn co
ntroll
er though
with
slightly
high
er oversh
oot
which satisf
ied the de
si
gn
requi
rem
ent
of 10% maxi
mum ove
r
sho
o
t. Direct
di
g
i
tal cont
rolle
r
control b
and
width of
16.5
kHz
again
s
t 9.5
kHz
of digital rede
sign
co
ntroller a
nd al
so
a pha
se m
a
rgin of 15
7º a
s
compa
r
e
d
to
138º of digit
a
l red
e
si
gn
controlle
r. Th
e com
pari
s
o
n
of the two
digital co
ntroller p
a
ra
met
r
ic
respon
se
sh
ows that
the
direct
digital
co
ntroll
er produ
ced
a
be
tter control
a
c
tion
with
fa
ster
transi
ent an
d
highe
r control band
width
for tighter
o
u
tput voltage regulatio
n in converte
r co
nt
rol
as compa
r
e
d
with digital re
desi
gn ap
pro
a
ch.
Table 2
.
Sum
m
ary on cl
osed loop fre
q
u
ency an
d time respon
se
Design approach
Digital redesi
gn
(DRC)
Direct digital design
(DDC)
Time response
Rise time
15µs
10µs
Settling time
200
µs
160
µs
Over shoot
6%
7%
Fre
que
nc
y
re
s
pons
e
Contro
l ban
d
w
i
d
th
9.49kHz
16.5kHz
Gain margin
In
finite
5.55
dB
Phase mar
g
in
157º
138º
4.3. Matlab-S
imulink Implementa
tion
The ope
n lo
op simul
a
tion
of the converter i
s
impl
emented in
Simulink e
n
vironm
ent
based on the
converte
r de
sign
ed exam
ple with stea
dy state para
m
eters pre
s
e
n
ted in Table
1.
The co
nverte
r re
spo
n
se to variable inp
u
t voltage varied from 1
2
V
nominal to
18V is sho
w
n in
Figure 10.
Figure 10. Co
nverter o
pen l
oop inp
u
t-out
put voltage
To verify the
system
clo
s
e
d
loop
pe
rformance, the d
e
sig
ned
co
ntrollers
with th
e boo
st
conve
r
ter
wa
s implem
ente
d
in Simulink as pres
ente
d
in the Figu
re 11 a
nd Fi
gure
12 for b
o
th
digital red
e
si
gn co
ntrolle
r (DRC) a
nd di
rect digital con
t
roller (DDC)
respe
c
tively.
The output resp
on
se pre
s
ente
d
in
Fi
gure
13
an
d
Figu
re
14
shows th
at th
e outp
u
t
voltage of th
e converte
r i
s
4
8
V
with n
o
minal
12V
supply a
nd
re
mains con
s
ta
nt and
bum
pl
ess
after 50ms
whe
n
the inp
u
t voltage is incre
a
sed b
y
50% from
12V to 18V. This sho
w
s the
robu
stne
ss of the two desi
gned
contro
ll
ers
to supply voltage
varia
b
ility.
0
0.
02
0.
04
0.
0
6
0.
0
8
0.
1
5
10
15
20
T
i
m
e
(
s
ec
ond
s
)
V
o
l
t
ag
e (
V
)
In
p
u
t
v
o
l
t
a
g
e
0
0.
02
0.
04
0.
0
6
0.
0
8
0.
1
0
20
40
60
80
T
i
m
e
(
s
ec
on
ds
)
V
o
l
t
age (
V
)
O
u
tp
u
t
v
o
l
t
a
g
e
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
State-space Modelling an
d Digital Cont
roller Design
for DC-
DC
Converter (Oladim
e
ji Ibrahi
m
)
505
Figure 11. Co
nverter
clo
s
e
d
loop with
DRC
Fi
gure 12. Co
nverter
clo
s
e
d
loop with
DDC
Figure 13. Co
nverter
respo
n
se to varia
b
l
e
sup
p
ly voltage
Figure 14. Co
nverter transi
ent respon
se
with
DR
C & DD
C
5. Conclu
sion
A non
-ideal
DC-DC
boo
st conve
r
ter h
a
s
bee
n mo
delled
and
d
i
gital controll
er
wa
s
desi
gne
d u
s
i
ng di
gital
red
e
sig
n
a
nd
direct di
gital
de
sign
ap
pro
a
ches.
The
sy
stem
step
re
sp
on
se
of the
controll
ers sho
w
s th
at the di
re
ct
digital
de
sig
n
co
ntrolle
r h
a
s
fa
stest t
r
an
sient
and
hig
her
control b
and
width
as com
pare
d
with th
e digital
re
de
sign
ap
pro
a
ch.
The direct digital control
l
er
exhibited
better dyn
a
mi
c p
e
rform
a
n
c
e
with fa
stes
t t
r
an
sient
with
high
er
co
ntrol ba
nd
width
of
16.5 kHz aga
inst
9.5
kHz of
digita
l red
e
sig
n
controll
er.
Th
e clo
s
e
d
loo
p
impl
e
m
entation of the
controlle
rs
were a
b
le to g
i
ve con
s
tant output
voltag
e to variable
input voltage
even whe
n
the
input voltage
wa
s increa
se
d by 50% from the 12V no
minal to 18V.
R
e
fe
re
nc
es
[1]
S Chakrab
o
rt
y
,
MG
Simões,
W
E
Kramer.
Pow
e
r Electroni
cs for Renew
able a
nd Distrib
u
ted Ener
g
y
System
s
. Spri
n
ger. 201
3.
[2]
JM Carrasc
o,
LG
F
r
anq
ue
lo,
JT
Bialasi
e
w
i
cz, E G
a
lvá
n
,
RP G
u
isa
do,
MA Prats
,
et al. P
o
w
e
r-
electro
n
ic s
y
stems for the grid i
n
tegrati
o
n of rene
w
a
b
l
e ener
g
y
sou
r
ces: A survey.
Industri
a
l
Electronics, IEEE Transactions on.
20
06; 5
3
: 1002-
10
16.
[3]
O
Ibrahim,
N
Yaha
ya,
N S
a
ad, K A
h
me
d.
Desi
gn
an
d
Analys
is of
a
Digita
l C
ontro
ll
er for B
oost
Conv
erter w
i
th
Ren
e
w
abl
e
Energy
Sourc
e
s for D
o
mes
t
ic DC
Lo
ad.
In
Ap
pl
i
e
d
Mech
a
n
i
cs and
Materials. 2
0
1
5
: 141-1
45.
[4]
M Rashi
d
, C Press. Po
w
e
r Ele
c
tronics Ha
ndb
ook.
Devic
e
s, Circuits, an
d Applic
atio
ns
. 20
10.
[5] N
Kularatna.
P
o
w
e
r electro
n
ic
s desig
n h
and
book: l
o
w
-
pow
er co
mpo
n
e
n
ts and a
p
p
licati
o
ns
. Ne
w
n
es.
199
8.
[6]
S Ang, A Oliva. Po
w
e
r-s
w
i
tc
hi
ng conv
erters. CRC press. 2
0
05.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 497 – 50
6
506
[7]
HH Park, GH
Cho. A DC–D
C
Convert
e
r for a F
u
ll
y
Inte
grated PID Co
mpens
ator W
i
th a Sing
l
e
Capacitor.
Circ
u
its and System
s II: Express Briefs, IEEE Tr
ansactions on.
201
4; 61: 629-
633.
[8]
S Kap
a
t, PT
Krein. F
o
rm
ulati
on
of pi
d c
ontr
o
l for
dc–
d
c c
onverters
bas
e
d
o
n
ca
pac
itor
curre
nt: A
geom
etric cont
ext.
Power Electronics, IEEE Transactions on.
2012; 2
7
: 14
24-1
432.
[9]
YI Son, IH K
i
m. Comp
lem
entar
y PID c
ontrol
l
er to
p
a
ssivit
y
-b
ased
non
lin
ear c
o
ntrol of
boost
converters
w
i
t
h
in
ductor r
e
si
stance.
Co
ntro
l Syste
m
s T
e
c
hno
logy, IEEE
T
r
ansactio
n
s
on.
20
12; 20:
826-
834.
[10]
L Bal
o
g
h
. A pr
actical
introd
u
c
tion to d
i
g
i
tal
po
w
e
r su
ppl
y control.
T
e
xa
s Instruments
Incorpor
ated.
200
5: 6-1.
[11]
C Bucce
lla, C
Cecati, H
Lataf
at. Digita
l
cont
rol of p
o
w
e
r c
onverters-A s
u
rve
y
.
Industrial Inform
atics,
IEEE Transactions on.
2
012; 8:
437-4
47.
[12]
YF
Liu, P Se
n
.
Digita
l
contr
o
l of sw
it
ching
pow
er
conv
erters.
In Contr
o
l
Appl
icatio
ns,
200
5. CCA
200
5. Procee
di
ngs of 20
05 IEEE
Confere
n
ce
on. 200
5: 635-
640.
[13]
A Prodic, D Maksimovic.
D
e
si
gn
of a
di
gita
l
PID reg
u
lat
o
r b
a
sed
o
n
l
ook-
u
p tab
l
es
for co
ntrol
of h
i
gh-
freque
ncy DC-
DC conv
erters
.
In Computer
s in Po
w
e
r El
ectronics, 2
0
0
2
. Procee
din
g
s. 2002 IEE
E
W
o
rkshop o
n
, 200
2: 18-2
2
.
[14]
S Sag
g
i
n
i, E O
r
ietti, P Mattav
e
lli,
A Pizz
utell
i
,
A Bia
n
co.
F
u
l
l
y-dig
i
tal
hyster
etic vo
ltag
e-mode
co
ntrol
for dc-dc c
onv
erters bas
ed
o
n
async
h
ro
no
u
s
sa
mpl
i
ng
. In
Appl
ied
Po
w
e
r
Electron
ics C
o
nferenc
e a
nd
Ex
p
o
siti
on, 20
08. APEC 20
0
8
.
T
w
e
n
t
y
-T
hird Annu
al IEEE. 2008: 5
03-5
0
9
.
[15]
C N
w
osu, M Eng. State-
Spac
e Averag
ed Mo
deli
ng of a N
o
n
i
de
al Boost C
o
nverter.
T
he pa
cific jour
na
l
of science a
nd
T
e
chno
logy.
2
008; 9: 30
2.
[16]
V Jha, P Rai. State
Space A
v
erag
ed Mo
del
ing of Basic C
onverter T
opol
ogi
es.
VSRD International
Journ
a
l of Elec
trical, Electron
i
cs & Commu
n
i
c
ation En
gi
nee
ring.
20
12; 2: 5
66-5
75.
[17]
A Prodic, D Maksimovic, RW
Erickson.
Desi
gn an
d i
m
pl
e
m
entatio
n of a di
gital PW
M con
t
roller for a
hig
h
-frequ
ency
sw
itching DC-
DC pow
er co
n
v
erter.
In Indus
trial Electro
n
ics
Societ
y
,
200
1. IECON'
01.
T
he 27th Annu
al Co
nferenc
e
of the IEEE. 2001: 893-
89
8.
[18]
Y Duan, K Ji
n.
Digita
l
cont
roller d
e
si
gn for sw
itchmo
de
pow
er conve
r
ters.
In Appli
ed Po
w
e
r
Electron
ics Co
nferenc
e an
d Ex
p
o
siti
on, 19
99
. APEC'99. Fourteenth A
nnu
al. 199
9: 967-
9
73.
[19]
KJ Aström,
T
Hägg
lun
d
. PID contro
l
l
ers: theo
r
y
, desi
gn a
nd
tunin
g
. 199
5.
[20]
KJ Åström, T
Häg
g
lu
nd.
Ad
va
n
c
ed
PID
contro
l
:
ISA-T
he Instrumentati
o
n.
System
s, and Autom
a
tion
Society
. Rese
a
r
ch T
r
iangle Pa
rk, NC. 2006.
[21]
GF
F
r
anklin, JD Po
w
e
l
l
, A Emami-Na
ein
i
. F
eedb
ack cont
rol of d
y
namic
s s
y
stems. MA: Addison-
We
sl
ey
, Re
ad
in
g
.
199
4.
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