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ISSN:
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■
Hard
wa
re
-R
eso
u
r
c
e Sa
vi
ng for Re
aliz
ation of Space Vector P
W
M Based
…
…
(Tole Suti
kno)
161
HARDWARE-RESOURCE SAVI
NG FOR REALIZATION
OF SPACE VECTOR PWM BASED ON FPGA USING
BUS-CLAMPING TECHNIQUE
Tole Sutikno
Dep
a
rtme
nt of Electrical En
ginee
ring, Fa
culty of Industrial Technol
o
g
y
Universita
s Ahmad Dahla
n
(UAD), Yogyaka
r
ta
e-mail: tole
@ee.uad.a
c
.id
A
b
st
r
a
k
Modula
s
i l
e
bar pul
sa
vector ruan
g
(
SV-P
W
M) adal
ah l
e
b
i
h sesuai
d
an d
apat
m
eningkat
ka
n peroleh
an
rasi
o tega
ng
an DC lebi
h ban
ya
k diba
n
d
ing
k
an d
e
n
gan teknik P
W
M
lainn
y
a. Selai
n
itu,
m
odula
s
i ini m
e
m
p
u
n
yai
fa
ktor di
storsi ha
rm
onik total (THD) tegangan
ya
ng
lebih bai
k. Nam
un sam
p
a
i
sekarang,
belum
ada p
enelitian
yan
g
foku
s pad
a peng
hem
atan
sum
ber d
a
ya
pera
n
g
k
at kera
s dal
am
m
e
realia
sa
sikan SV-PWM
berb
a
si
s FP
GA. Makal
a
h
ini
m
engusul
ka
n
se
bua
h te
knik
baru u
n
tuk
reali
s
a
s
i SV-PWM berbasi
s
FPGA.
Sebua
h
te
knik
sed
e
rh
ana u
n
tuk pe
nent
uan sekto
r
,
kalkula
s
i p
u
lsa
-
pul
sa p
enyalaa
n da
n pem
bang
kitan
gelom
bang
SV-PWM tan
pa kal
k
ul
asi
fungsi tri
gon
om
etri m
engguna
ka
n teknik bu
s-clam
ping
diusulkan unt
uk pen
ghem
a
t
an sum
ber d
a
ya p
e
ra
ng
ka
t kera
s. Tekn
ik SV-PWM b
e
rba
s
i
s
FPGA
APEX20KE ini telah diimplementas
ikan s
e
c
a
ra
s
u
kses
untuk
mengemudik
a
n motor induk
s
i
tiga
fasa 1,5
kW
deng
an ria
k
-riak yang
ren
dah pa
da a
r
us da
n tegan
gan, dan tela
h m
enunjukkan
bah
wa m
e
tode yang SV
M diusulkan
m
e
m
e
rlukan
su
m
ber da
ya
pera
n
g
k
at kera
s yang
pa
ling
m
i
nim
a
l diba
nding
ka
n pen
elitian lainn
y
a
.
Kata kunci
:
bus-c
lamping, FPGA, SV-
PWM,
hardware
-re
so
urce
sa
ving
A
b
st
r
a
ct
The spa
c
e ve
ctor p
u
lse
wi
dth m
odulation (SV-PWM
)
is m
o
re suita
b
le and
can i
n
crea
se
the obtai
nabl
e DC
volta
g
e
utilizatio
n ratio very m
u
ch
com
p
a
r
ed
to
othe
rs PWM
.
More
over, t
he
m
odulation can
o
b
tain a
b
e
tter voltag
e total
ha
rm
onic di
sto
r
tion
(THD) fa
cto
r
.
But until n
o
w,
no
studie
s
that
concern
at ha
rdware re
so
u
r
ce
s
sa
ving t
o
reali
z
e SV-PWM ba
se
d
on FPGA. Th
is
pape
r p
r
op
oses
a ne
w te
chniqu
e to
rea
lize SV-P
W
M
ba
sed
on
FPGA. In order to get h
a
rdwa
re
resou
r
ce sa
ving, a sim
p
le techniq
ue to judge sect
ors, to cal
c
ul
ate the firing
pulse
s and
to
gene
rate SV-PWM wavefo
rm
without calcul
ation
of
trigonom
etri
c function u
s
i
ng bu
s-clam
ping
techni
que i
s
prop
osed. The techniq
ue ha
s be
e
n
im
plem
ented su
cce
ssf
ully ba
se
d
on
APEX20KE FPGA to drive
three phas
e
induc
t
ion mach
ine 1.5 k
W
with
low ri
pples
in c
u
rrent and
voltag
e, and
has be
en
shown
that th
e propo
se
d
SVM m
e
thod req
u
ire
d
the
m
o
st m
i
nimum
hard
w
a
r
e resource
s com
p
ared to othe
rs re
sea
r
ch.
Key
w
ords
:
bus
-
c
l
amping, FPGA, SV-PWM,
hardware-resource sa
ving
1. INTRODUCT
I
ON
The main ai
m of any modulatio
n techniqu
e is to obtain varia
b
le output h
a
ving a
maximum fu
ndame
n
tal
compon
ent
wi
th minimum
harm
oni
cs a
nd le
ss
swit
ching l
o
sse
s
.
The
Space Ve
ctor Pulse Width
Modulatio
n (SV-PWM)
me
thod is an ad
vance
d
PWM
method and i
t
is
possibly the
best a
m
ong
all the PWM
techni
que
s f
o
r vari
able freque
ncy d
r
ive appli
c
atio
n
s
.
Comp
ared to the Sinusoid
a
l Pulse Widt
h Modul
atio
n
(SPWM), SV-PWM is m
o
re suitable
and
can increase t
he obtainable DC voltage utiliz
ation ratio very much. Moreover, it can obtai
n a
better voltage
total harmoni
c disto
r
tion fa
ctor [1-13].
In most engi
neeri
ng p
r
a
c
tice, the SV-PWM algo
rit
h
m is mai
n
l
y
implement
ed with
softwa
r
e b
a
sed on mi
cro
c
ontrolle
r [2, 13-1
8
] or
di
gital sig
nal p
r
ocesso
rs (DSP) [19-2
1
] are
widely ado
pted. They perf
o
rm cont
rol p
r
ocedu
re
seq
uentially by ex
ploiting their mathematica
lly
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ISSN: 1693-6
930
TELKOM
NIKA
Vol. 7, No. 3, Desem
b
e
r
2009 : 161
- 168
162
oriente
d
reso
urces.
That i
s
the i
n
structi
ons
of
differe
nt pro
c
e
dure
s
a
r
e exe
c
ut
ed on
e after
the
other. Thu
s
, the purely so
ftware
-
ba
se
d
techniq
ue
is not an ideal
solution. Dif
f
er to softwa
r
e
impleme
n
tation; FPGA perform
s the e
n
tire pro
c
e
d
u
r
es
with con
c
urre
nt opera
t
ion by using
its
reconfigu
r
a
b
le hardware. A FPGA
is consi
dered a
s
an ap
pro
p
ri
ate sol
u
tion t
o
boo
st sy
stem
perfo
rman
ce
of a digital co
ntrolle
r incl
ud
ing an SV-P
W
M algo
rith
m [2, 6, 13, 2
2
-26].
Ho
wever, th
e
conve
n
tional
SV-PWM
suffers
f
r
om t
he d
r
a
w
ba
cks like
comp
u
t
ational
burd
en, inferior pe
rform
a
nce at hig
h
modulat
io
n indices a
nd
high switchin
g losse
s
of the
inverter. Hen
c
e to red
u
ce the swit
ch
ing losse
s
a
nd to impro
v
e the perfo
rman
ce in hi
gh
modulatio
n re
gion,
several
bus-cl
a
mpi
n
g
SV-PWM
me
thods have
b
een
pro
p
o
s
ed
[5, 21, 2
7
-3
1
].
Unfortu
nately
,
those are
based on th
e conve
n
tion
al SV-PWM without con
s
i
derin
g hardware
resou
r
ce
savi
ng. Thi
s
p
a
p
e
r p
r
e
s
e
n
t th
e de
sig
n
an
d
implem
entati
on of
bu
s-cla
m
ping SV
-PWM
based on FP
GA usin
g ne
w techniqu
e. To get ha
rd
ware re
so
urce saving, the
simplification
of
se
ctor id
entification m
e
tho
d
, re-arran
ge
the dw
elling
time to avoid the comple
x trigonom
etric
cal
c
ulatio
ns,
and a novel
method to cal
c
ulate t
he d
u
ration of active vector a
r
e p
r
opo
se
d.
2.
A NEW
APPROACH TO IMPLEMEN
T 5-SE
GMENT BUS-CLAMPING SV-PWM
ALG
O
RIT
H
M
This sectio
n
pre
s
ent
sym
m
etrical 5
-
se
gment
bu
s-cl
amping
switching se
que
n
c
e with
new
j
udg
e
m
e
thod
of se
ctors, and new SV-PWM
g
e
n
e
rating metho
d
ba
sed on calcul
ation
of
t
h
e
duratio
n of active vectors t
o
avoid com
p
licat
ed comp
utations with
trigon
ometri
c
functio
n
.
2.1.
Proposed S
V
-PWM s
w
i
t
ching Patter
n
(5-segmen
t
bus-clamping s
w
i
t
chin
g
pulses)
There ha
s be
en rep
o
rte
d
many bus-cla
mping SV-P
W
M pattern [5, 6, 26-28]. Ho
wever,
not all tho
s
e
pattern
s hav
e lower
swit
ching lo
sses,
simple
r alg
o
ri
thm and
can
be imple
m
ent
ed
based on
FPGA easily. In this pa
pe
r, a nov
el sym
m
etric
5-seg
m
ent
bu
s-cla
m
ping SV-P
W
M
desi
gn, whi
c
h
it is always a
chan
nel stayi
ng co
nsta
nt for the entire PWM pe
riod i
s
pro
p
o
s
ed.
2.2.
Proposed id
entific
a
tion
of the s
e
c
t
or
The metho
d
s to judge the se
ctor h
a
ve
been intro
duced which
the refere
nce spa
c
e
voltage ve
cto
r
lie
s in.
Zhi-p
u
[32] h
a
s co
mpared th
e referen
c
e
spa
c
e ve
ctor’
s
a
ngle
with
0
0
, 60
0
,
120
0
, 180
0
, 240
0
, and 300
0
to obtain the numbe
r of the se
ctor th
at the V
ref
in. The others, Yu
[33], Jiang [2
3] and Xin
g
[7] have an
alyzed th
e relati
onship b
e
twe
en
V
and
V
to determin
e
the
se
ctor. They
have cal
c
ulat
ed the proj
ect
i
ons
a
V
,
b
V
and
c
V
of
V
an
d
V
in (a,b,c) pl
ane by usi
n
g
inverse Cla
r
k transfo
rmatio
n, as follow:
2
3
2
3
V
V
V
V
V
V
V
V
c
b
a
(1)
Then, ba
se
d
on equ
ation
(4) ab
ove, the
y
calcul
ate
N=si
gn(V
a
) + 2*sig
n
(Vb
)
+ 4*sig
n
(V
c).
M
a
p
N to the actu
al se
ctor of th
e output voltage refe
ren
c
e
by referring to the followin
g
relation
shi
p
:
Table 1. Map
N to the actu
al se
ctor of th
e output voltage refe
ren
c
e
N
1 2
3 4 5
6
se
ctor
2 6
1 4 3
5
In [34], Zeliang ha
s ado
p
t
ed the new
interme
d
iate
vectors
X
and
X
that he has
defined
V
X
2
3
and
V
X
3
as d
e
compo
s
e of the
co
nventional S
V
-PWM, whi
c
h
will
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TELKOMNI
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ISSN:
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■
Hard
wa
re
-R
eso
u
r
c
e Sa
vi
ng for Re
aliz
ation of Space Vector P
W
M Based
…
…
(Tole Suti
kno)
163
prop
erly co
u
n
tera
ct the redun
dant cal
c
ulatio
ns to
identify secto
r
location, but
it imported the
compli
cate
d matrix
calcul
ations. He
nce,
thro
ugh
th
e an
alyzin
g
of SV-PWM
mentione
d
a
bove,
this research
has
create
d
a sim
p
ler
me
thod to
dete
r
mine the
se
ct
ors of voltag
e vecto
r
s
ba
sed
on the com
pari
s
on b
e
tween
V
V
V
3
,
3
,
and 0
as sho
w
n in
Fig.
1. By using the
comp
ari
s
o
n
, we can dete
r
mine the se
ct
ors of
voltage
vectors simpl
e
r than [7, 23
, 32-34].
Fig. 1. A simpler metho
d
to determi
ne the
secto
r
s
2.3.
The propo
se
d calculating
of the dur
ati
on of ac
tiv
e
v
ectors
In this re
sea
r
ch, throu
gh the analy
z
ing
of refe
re
nce [12], a new se
t of equation to calculate
the du
ration
of active ve
ctors for
ea
ch
se
ctor
ha
s re
-arran
ged
in
orde
r to
easi
e
r to im
plem
ent
based on FP
GA. It is shown in Tabl
e 2
.
Table 2. The
swit
chin
g time of the active vector for e
a
ch
se
ctor
Sec
t
or T
a
T
b
T
a
+T
b
I
dc
dc
V
V
V
V
T
3
4
3
dc
V
V
T
3
2
4
3
dc
dc
V
V
V
V
T
3
4
3
II
dc
dc
V
V
V
V
T
3
4
3
dc
dc
V
V
V
V
T
3
4
3
dc
V
V
T
3
2
4
3
III
dc
V
V
T
3
2
4
3
dc
dc
V
V
V
V
T
3
4
3
dc
dc
V
V
V
V
T
3
4
3
IV
dc
dc
V
V
V
V
T
3
4
3
dc
V
V
T
3
2
4
3
dc
dc
V
V
V
V
T
3
4
3
V
dc
dc
V
V
V
V
T
3
4
3
dc
dc
V
V
V
V
T
3
4
3
dc
V
V
T
3
2
4
3
VI
dc
V
V
T
3
2
4
3
dc
dc
V
V
V
V
T
3
4
3
dc
dc
V
V
V
V
T
3
4
3
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ISSN: 1693-6
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TELKOM
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Vol. 7, No. 3, Desem
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e
r
2009 : 161
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164
2.4.
Proposed m
e
thod
to gen
e
rate SV-PWM s
w
i
t
ching
pulses
The bu
s-clam
ping 5-seg
m
e
n
t
bu
s-clam
pi
ng
SV-P
W
M has
symm
etri
cal switchi
ng pulses
as in th
e 7-segm
ent con
v
entional SV
-PWM.
Th
e
r
efore, the similar meth
o
d
to gen
erat
e
conve
n
tional
SV-PWM swi
t
ching p
u
lses can b
e
ado
pted in the p
r
opo
se
d SV-PWM. To ea
sier
impleme
n
t it
based
on FP
GA, in thi
s
re
sea
r
ch h
a
s created
a
grap
hical
metho
d
to gen
erate
the
SV-PWM swit
ching pul
ses as
illustrated i
n
Fig. 2.
Fig. 2 The propo
sed meth
od to gene
rat
e
set of SV-PWM switchin
g pulses
By consi
deri
n
g equatio
n
x
T
m
y
2
in
Fig. 3, the PWM gen
era
t
ing for odd
sector
we
re
impleme
n
ted throug
h com
pari
s
on
bet
ween
tri
angl
e
and
a
T
, and
bet
wee
n
tria
ngle
and
b
a
T
T
with oth
e
r switchi
ng
wa
s set
eq
ual t
o
1;
while
f
o
r even se
ct
or,
the
PWM
gen
erating
are
impleme
n
ted
throug
h com
p
lement of
co
mpari
s
o
n
bet
wee
n
triangle
and
a
T
, and co
mpleme
nt of
comp
ari
s
o
n
b
e
twee
n
triang
le
and
b
a
T
T
with other switchi
n
g
is set equ
al to 0. For example in
se
ct
or I
,
if
x=T
a
=
2
0
T
then
)
2
(
2
0
T
T
m
y
and if x=T
b
=
2
1
T
then
)
2
(
2
1
T
T
m
y
. For simpler of
circuit de
sign
, in this paper the term
T
m
2
is set equal to 1, so if x=
2
0
T
=T
a
then y=
2
0
T
=T
a
, a
nd
also if x=
2
1
T
then y=
b
T
T
2
1
. Obvious
ly, if x=
b
a
T
T
T
T
2
2
1
0
then y=
b
a
T
T
T
T
2
2
1
0
.
Therefore, th
e PWM ge
ne
rating for S
b
and
S
c
ch
an
nels in
se
cto
r
I can b
e
o
b
tained th
rou
gh
comp
ari
s
o
n
b
e
twee
n tria
ng
le and
a
T
, and
betwe
en tri
a
n
g
le an
d
b
a
T
T
respec
tively, wit
h
S
a
Cha
nnel is
set equal to 1. The PWM g
enerating in
other secto
r
s can be obtai
ned in a simi
lar
way
.
3.
FPGA RE
ALI
Z
ATIO
N OF
A PROPOSE
D
NOVEL SV
-PWM
In previo
us
se
ction, the
prin
ciple
of
SV-
PWM h
a
s
a
nalyze
d
.
In this
se
ction, the
implementation of proposed SV
-PWM based
on
FPGA will
be presented. The overall of
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W
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kno)
165
prop
osed SV-PWM de
sig
n
is sho
w
n in Fig. 3. This top modul
e has divided int
o
5 sub mod
u
les,
namely
ajus
t_freq
,
Vbeta_
Valfa
,
find_se
c
tor
,
SVM_ge
nerato
r
an
d
d
eadtim
e_syst
em
module.
Fig. 3 Overall
of the propo
sed SV-PWM
desi
g
n
3.1.
Adjustable Freque
nc
y
Module
In this modul
e, the source
of clock gen
erat
ing i
s
de
sign
ed to co
nne
ct L6 pin. In this
resea
r
ch, carrier
signal fre
quen
cy is set
to 40 kHz a
nd refe
ren
c
e
sign
al frequ
e
n
cy is set to 50
Hz. To g
e
t de
sire
d ca
rri
er a
nd refe
ren
c
e
sign
al frequ
e
n
cy, the clo
c
k dividing is do
ne.
3.2.
V
α
and V
β
Module
In this
res
e
arc
h
, V
α
and V
β
is gen
erate
d
throu
gh lo
o
k
up ta
ble (L
UT)
sin
e
an
d
co
sine
function
with
memory ma
p
p
ing 36
0 ad
d
r
esse
s.
Th
e lowe
r, ba
se, and hig
h
e
r
n
u
mbe
r
s of
si
ne
and cosi
ne fu
nction a
r
e 96,
224 and 3
52
respe
c
tively (in 9 unsi
gne
d bits).
3.3.
Sector Iden
tification Mo
dule
This mo
dule
is used to de
termine
se
cto
r
bas
ed on T
able 2. The simplification
of truth
table for
com
pari
s
on
re
sult
s a
s
sho
w
n i
n
Table
3 we
re u
s
ed to
de
termine
num
ber of
se
ctor
in
“
cs
ec
tor
” sub-module.
Table 3. Co
n
v
ersio
n
of co
mpari
s
o
n
re
sult betwee
n
V
V
V
3
,
3
,
a
nd 0 to numb
e
r of se
ctor
Sector
Vector
Angl
e
Inpu
t
O
upu
t (S
2
S
1
S
0
)
I (0
0
, 60
0
)
101
001
II
(60
0
, 120
0
)
111
010
III
(120
0
, 180
0
)
110
011
IV (180
0
, 240
0
)
010
100
V (240
0
, 300
0
)
000
101
VI (300
0
, 360
0
)
001
110
3.4.
Three pha
s
e
SV-PWM si
gnal gener
a
tor module
This mo
dule
can be div
i
ded into 4
sub
-
mo
dule
s
,
namely
Tri
angle
,
Durati
on_Ta
,
Duration_
TaT
b
, and
SVM pattern
s
u
b-
mo
du
le
.
T
r
i
angle
sub-m
odule
was u
s
ed
to g
ene
rate
triangle
carri
e
r
sig
nal. In
this
re
sea
r
ch
, triangl
e
sig
nal g
ene
rato
r wa
s
sa
mple
d 32
time
s p
e
r
perio
d and 9
unsi
gne
d bits were u
s
ed to
repre
s
e
n
t, which lo
we
r nu
mber (equ
al to base n
u
mb
er
of referen
c
e
sign
al)
and
h
i
gher num
ber each a
r
e
22
4 and
35
2 re
spe
c
tively. The
Duration_
Ta
and
Duration
_TaTb
su
b-module
ha
s
cre
a
ted b
a
se
d on di
gital solutio
n
of seco
nd a
nd f
ourth
colum
n
in
Ta
ble 3
respe
c
tively. Then,
S
V
M pattern
sub-m
odul
e was used
to
ge
nerate
set
of SV-
PWM pul
se
s refer to sectio
n 2.4 and Fig.
2 above.
Evaluation Warning : The document was created with Spire.PDF for Python.
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930
TELKOM
NIKA
Vol. 7, No. 3, Desem
b
e
r
2009 : 161
- 168
166
4. SIMULATION
A
ND EXPERIMENT
RESULTS
The
software
to de
sig
n
, compilation, v
e
rificatio
n
a
n
d
ha
rd
wa
re
realization
ba
sed
on
FPGA APEX
20KE in this
res
e
arc
h
has
us
ed
Quartus II Vers
ion 9.0 Web Edition.
4.1. Simulation
The pa
ram
e
ters
ha
s u
s
e
d
in this
re
search a
r
e li
sted as follo
ws: V
dc
/T=
1
, switc
h
ing
freque
ncy 40
kHz, and refe
ren
c
e fre
que
ncy 50 Hz.
The com
p
ilatio
n
repo
rt of propo
sed SV-P
W
M
gene
rato
r ha
s sho
w
n that
the de
sign
re
quire
s 5
20 lo
gic ele
m
ent
s
and 9.21
6 m
e
mory bit
s
. If
the
requi
rem
ent of hard
w
a
r
e
reso
urce to
gener
ate propo
sed SV-PWM is co
mpared to o
t
her
resea
r
che
s
, the meth
od requires i
s
m
o
st saving a
s
sho
w
n in
Fig. 4. It has prove
d
that
the
prop
osed SVM method re
quire
d the mo
st minimum h
a
rd
wa
re re
so
urces.
T
h
e u
s
a
ge of
r
e
s
o
u
r
c
e
s
(
L
E
/
LC
)
re
f
[
2
]
11
56
re
f
[
8
]
2880
r
e
f
[
26]
3011
r
e
f
[
28]
1
159
re
f
[
3
1
]
235
2
re
f
[
3
2
]
1560
ref
[
33]
3011
pr
op
os
ed
52
0
0
500
1000
1500
2000
2500
3000
3500
m
e
t
h
ods
LE
/
L
C
Fig. 4 The co
mpari
s
o
n
of required ha
rd
ware re
so
urces
4.2. Experiment
The adva
n
ce
d testing
of FPGA based
prop
osed SV
-PWM g
ene
rator de
sig
n
h
a
s b
een
done
to d
r
ive
a three
pha
se i
n
verte
r
system with
in
ductio
n
ma
ch
ine 1.5
kW.
The
re
sults a
r
e
sho
w
n i
n
Fig.
5. They a
r
e
eac
h sho
w
n
stator
cu
rrent
output (I
a
), p
hase-to
-ph
a
se voltage o
u
tput
(V
ab
) and fre
quen
cy sp
ect
r
um. The p
r
a
c
tical
re
sults
from test-rig
were in go
od
agre
e
ment t
o
drive indu
ctio
n machi
ne 1.
5 kW, with lo
w rippl
es in
current and vol
t
age.
(a)
curre
n
t an
d voltage out
put
(b) freque
ncy
spe
c
trum
Fig.5 The pe
rforman
c
e of p
r
opo
se
d SV-
PWM gen
erat
or de
sign b
a
sed on FPGA.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOMNI
KA
ISSN:
1693-6930
■
Hard
wa
re
-R
eso
u
r
c
e Sa
vi
ng for Re
aliz
ation of Space Vector P
W
M Based
…
…
(Tole Suti
kno)
167
5. CO
NCL
USIO
N
This
pap
er
h
a
s p
r
e
s
e
n
ted
the re
alization
of a
nove
l
5-segm
ent
bus-cl
a
mpi
n
g
SV-PWM
based
on FP
GA at
swit
chi
ng fre
que
ncy
40
kHz, i
n
which
the simp
le
jud
g
ing of se
ctors,
the
re-
arrang
e cal
c
ulation meth
od of the firi
ng time
and
the simpl
e
method to g
enerate SV-PWM
pulses
withou
t complicated
computatio
n
s
with
trig
ono
metric fun
c
tio
n
have bee
n prop
osed. Th
e
techni
que has been implemented successfully bas
ed on APEX20KE FPGA to
drive three phase
indu
ction m
a
chin
e 1.5
kW with lo
w
rippl
es in
current
and voltag
e,
and h
a
s be
e
n
sh
own that
th
e
prop
osed SV
M method
re
quire
d the m
o
st minim
u
m
hard
w
a
r
e
re
sou
r
ces
co
m
pare
d
to oth
e
rs
r
e
sear
ch.
REFERE
NC
ES
[1].
H. W. van de
r Broe
ck, H.
C. Skud
elny, and G. V. Stanke, "
An
aly
s
is and realiza
t
ion of a
pulse
w
i
dth
modulator b
ased on v
o
ltage sp
ace v
ector
s
," Indus
t
ry Applic
ations
, IEEE
Tran
sa
ction
s
on, vol. 24, pp. 142-1
50, 1
988.
[2].
A. Jidin an
d
T. Sutikno, "
Matlab/Simulink Bas
e
d
Analy
s
is of Voltage Sou
r
ce Inv
e
rter
w
i
th Spa
c
e
Vecto
r
Mo
dulation
,"
Jurnal
TELKO
M
NIKA, Teknik Ele
k
tro,
Universita
s
Ahmad Dahla
n
, Vol.7, No.1, April 2009.
[3].
C. S. Moreira
,
R. C. S. Fre
i
re, E. U. K.
Melch
e
r, G.
S. Deep, S.
Y. C. Catund
a, and R.
N.
C. Alv
e
s, "
F
P
GA-based
SVPWM trig
ger generator fo
r a 3-p
h
ase v
o
ltag
e sour
ce
in
v
e
rter
," in
Instrum
entat
ion an
d Me
a
s
ureme
n
t
Te
chn
o
logy Co
nferen
ce, 20
00.
IMTC
2000. Proceedings of the 17th I
EEE, 20
00, pp. 174-178 vol.1.
[4].
J
.
Holtz
,
"
Pulse
w
i
d
th mo
dulation-a s
u
rv
e
y
," Industrial Electronic
s, IEEE Transactions
on, vol. 39, pp. 410-4
20, 1
992.
[5].
A. Gopinath,
A. S. A. Moh
a
med, an
d M.
R. Baiju, "
Fr
actal
Bas
e
d
Space Vec
t
o
r
PWM fo
r
Multilev
e
l
Inv
e
rters: A
Nov
e
l Approach
," Indust
r
ial Electronic
s,
IEEE Transactions on,
vol. 56, pp. 1230-123
7, 20
09.
[6].
Z. Keliang a
nd W. Dan
w
ei, "
Relation
ship bet
w
e
e
n
spac
e-v
ector modula
t
ion and
three
-
ph
ase
carrier
-bas
e
d
PWM
:
a c
o
mprehensiv
e analy
s
is [three-phas
e
i
n
v
e
rters]
,"
Industri
a
l Electroni
cs, IEEE Transacti
ons on, vol. 49, pp. 186-196, 2002.
[7].
Y.-Y. Tz
ou
and H.
-J
.
Hsu, "
FPGA re
a
lization o
f
s
p
ace
-v
ector PWM co
ntro
l IC for
three
-
ph
ase PWM
inv
e
rters
," Power El
ectronics, IEEE Transacti
ons on, vol. 12, pp. 953-
963, 199
7.
[8].
S. Xing and K.-Y. Zhao, "
Research
on A Nov
e
l SVPWM Algorithm
," in Industrial
Electronics and
Applications
, 2007.
ICI
EA 2007.
2nd IEEE
Conference on, 2007, pp.
1869
-18
72.
[9].
Z. Yinhai, W. Song
son
g
, X. Haixia, and G. Ji
nfa, "
A Nov
e
l SVPWM Modulation
Scheme
," in
Applied P
o
wer Ele
c
tro
n
ics
Confe
r
en
ce
and
Expositi
on, 20
09. AP
EC 20
09.
Twenty-Fourth Annual IEEE, 2009, pp. 128-131.
[10].
M. F. Nagui
b and L. Lo
pes, "
Minimize Lo
w
-
O
r
d
e
r Harmo
n
ics in Lo
w
-
S
w
i
t
ching
-
Freque
nc
y
Space-V
ecto
r
-Modula
t
ed
Cur
r
en
t S
ource
Co
nv
erter
s
w
i
th
Minimum
Harmonic Tr
acking Te
ch
nique
," Power Elec
tronics
, IEEE Trans
ac
tions
on, vol. 24, pp.
881-893, 20
0
9
.
[11].
L. Lop
es an
d
M. F. Nagui
b, "
Space
Ve
ctor
Modula
t
ion for
Lo
w
S
w
i
t
ching
Fr
equenc
y
Curre
nt Source
Co
n
v
erters Wi
th
Red
u
ce
d Lo
w
-
Or
d
e
r
Nonch
a
racteristic
Harmonic
s
," Power Electronics, IEEE T
r
ansactio
ns on, vol. 24, pp. 903-910, 2009.
[12].
D. Ca
sad
e
i, G. Serra, an
d K. Tani, "
Implementa
tion of a dire
ct con
t
rol algorithm for
induction m
o
tors ba
sed
on discrete
space v
ector modulation
," Power
Elec
tronics
,
IEEE Transactions on, vol.
15, pp. 769-777, 2000.
[13].
K. Bong-Hwan, K. Ta
e-
Woo,
and
Y. Ja
ng
-Hyo
un
, "
A n
o
v
e
l
SVM-base
d
h
y
steresis
curren
t
co
ntroller
," Power Electronics, IEEE Transa
ctions on, vol. 13, pp. 297-307,
1998.
[14].
M. W. Naou
a
r
, E. Monmasson, A. A.
Naassani, I. Slama-Bel
k
ho
dja
,
and N. Patin, "
FPGA-
Bas
e
d Cu
rre
nt Co
ntroller
s
for A
C
Ma
chine Driv
es-A
Rev
i
e
w
," Industri
a
l
Ele
c
troni
cs,
IEEE Transactions on, vol.
54, pp. 1907-1925, 2007.
[15].
J. J. Rod
r
ig
u
e
z-A
ndin
a
, M. J. Moure, a
nd M. D. Valdes, "
Fea
t
ur
es, Design T
ools, and
Applica
t
ion Domains o
f
FPGAs
," Indus
t
rial Elec
tronics
, IEEE
Trans
a
c
t
ions
on, vol. 54,
pp. 1810
-18
2
3
, 2007.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 1693-6
930
TELKOM
NIKA
Vol. 7, No. 3, Desem
b
e
r
2009 : 161
- 168
168
[16].
E. Monma
sson a
nd M.
N.
Ci
rstea,
"
FPGA
De
sign
Metho
dolog
y
for Industr
ial Con
t
rol
Sy
stems: A Rev
i
e
w
," Indus
t
rial Elec
tronics
, IEEE Tran
s
a
c
t
ions on, vol. 54,
pp. 1824-
1842, 20
07.
[17].
L.-S. Xuefang
, F. Morel, A.
M. Llor, B. Allard, an
d J. M
.
Retif, "
Implementa
tion of
H
y
brid
Con
t
rol for Motor
Driv
es
," Indus
t
rial Elec
tronic
s
,
IEEE
Transac
t
ions
on, v
o
l. 54,
pp.
1946
-19
52, 2
007.
[18].
J. Ace
r
o,
D.
Navarro, L.
A. Barra
ga, I.
Gard
e, J. I.
Artiga
s, and
J. M. Bu
rdio
, "
FPGA-
Bas
e
d Po
w
e
r Measuring
for Inductio
n
He
a
t
ing Appliances
Using Sigma Delta
A/D
Conv
ersion
," Industrial Electroni
cs,
IEEE Transactions on, vo
l. 54, pp. 1843-1852, 2007.
[19].
E. Monmasson an
d Y. A. Chapui
s,
"
Contributi
ons
of FPG
A
's to
the Con
t
rol
of
Electrical Sy
stems
:
A
Re
v
i
e
w
," IEEE Ind. Elec
tron. Soc
.
News
let
t
er, vol. 49 no.4, pp. 8-
15, 2002.
[20].
A. Fyntanaki
s
, G. Adamidi
s
, and Z. Kout
sogi
anni
s, "
Comparison
b
e
t
w
e
e
n
t
w
o
differ
e
nt
method
s of calculation
of s
w
i
t
chin
g time
w
h
ic
h is used for implementa
tion of
SVPWM usi
ng DSP
," in
Electri
c
al
Machi
n
e
s
, 2
008. ICEM
2008.
18th I
n
ternatio
nal
Confe
r
en
ce o
n
, 2008, pp. 1
-
6.
[21].
Y. Gui-jie, S.
Li, C. Nai-zhe
ng, and L. Yo
ng-pi
ng, "
Stu
d
y
on Metho
d
of the s
p
a
ce v
ector
PWM
," in CSEE. vol.
21 China, 2001, pp. 79-83.
[22].
Z. Yu, "
Space-Vec
t
or PWM With TMS
320
C24
x
/F24
x Using Har
d
w
a
re an
d Soft
w
a
re
Determined
S
w
i
t
hing
Pa
tterns
," Texa
s
Instrument
s Applicatio
n Report
SPRA5
24,
Ma
rch
1999.
[23].
Z. Zhaoyong,
L. Tiecai, T. Taka
ha
shi, a
nd E. Ho, "
Design of a u
n
iv
ersal spa
ce v
ector
PWM contr
o
ller based
on FPGA
," in Applied Powe
r Electronics Co
nference and
Exposition, 2004. APEC '04.
Nineteenth Annual IEEE,
2004, pp. 1698-1702 Vol.
3.
[24].
[K. I. P. M. Q
ueiro
z, F. R. d. S
ousa, R. L. A. Ribeiro, and E. C. Braz, "
A Flexible SVPWM
implemente
d in FPG
A
," Powe
r Ele
c
t
r
oni
cs, IEEE
Tra
n
saction
s
o
n
, vol. 22
, pp. 140
2-
1414, 20
07.
[25].
V. M. Mora, C. A. Nune
z,
V. M. Carde
n
a
s, and
H. Mi
rand
a, "
Simple and Prac
tical FPGA
Implementation of Space Vec
t
or
Modula
t
ion Bas
e
d
on Geometrical
Consid
era
t
ions
," in International Power Electroni
cs
Congress, 10th IEEE, 2006, pp. 1-6.
[26].
Y. Zhou, F.-p. Xu, and Z.-y. Zhou, "
Realization o
f
an
FPGA-Bas
e
d
Space-Ve
c
t
or PWM
Controller
," in Powe
r Electroni
cs and
Motion Co
ntrol Confe
r
en
ce, 2006. IPEMC 200
6.
CES/IEEE 5th International, 2006, pp. 1-5.
[27].
C. Bharatiraj
a, T.
B. Prasad, and
R. Latha, "
Comparativ
e Realizatio
n of Differ
e
nt
SVPWM Schemes in Linear Modulation Using FPGA
," in IEEE Region 8
Sibircon,
2008, pp. 16
4
-
168.
[28].
K. S. Gowri,
T. B.
Redd,
and
C. S. B
abu, "
Nov
e
l Space V
ecto
r
Based
G
e
neralized
Discon
t
inuo
us PWM
Al
gorithm for
Induction
Motor
Driv
es
," ARPN
Journ
a
l of
Enginee
ring
and Applie
d Scien
c
e
s
, vol. 4 no.1, February 200
9.
[29].
W.-F. Zhang and Y.-H.
Yu, "
Comparison of Three SVPWM Strategis
," Jou
r
nal
of
Electro
n
ic Sci
ence and Te
chnolo
g
y of China,
vol. 5 no.3, pp. 283-287, Septem
ber 20
07.
[30].
A. R. Beig
and V. T.
Ran
gan
athan
, "
Space v
ector
bas
e
d
bus
clamp
e
d PWM
algorithms
for thr
ee lev
e
l in
v
e
rters: implementation, per
f
o
r
mance a
n
a
l
y
s
is and
application consider
atio
ns
," in Applied Powe
r Electro
n
ics Co
nferen
ce a
n
d
Exposition,
2003. APEC '03. Eighteent
h Annual
IEEE, 2003, pp. 569-575 vol.1.
[31].
G. Narayana
n, H. K. Kris
hnamu
r
thy, Z. Di, and R. Ayyanar, "
Ad
v
a
nced bus-clamping
PWM Tech
niques
B
ase
d on spac
e
v
ector a
pproac
h
," Power Elec
tronics
,
IEEE
Tran
sa
ction
s
on, vol. 21, pp. 974-9
84, 2
006.
[32].
Z. Zhi-pu, "
Design an
d Realizatio
n of Space Ve
ctor PWM
Ba
s
e
d on SG
," Jou
r
nal
of
Drive an
d Co
ntrol, vol. 7, pp. 29-32, 20
0
5
.
[33].
F. Yu, X. Yan, and
H. Yu
wen, "
A fast algorithm
for SVPW
M i
n
three phase po
w
e
r
fac
t
or corr
e
c
tion applic
ation
," in Power Elec
tronics
S
peci
a
li
sts Conferen
ce, 200
4
.
PESC 04. 2004 IEEE 35th Annual, 2004, pp. 976-979 Vol.2.
[34].
S. Zeliang, T.
Jia
n
, G. Yuh
ua, and
L.
Jisan, "
An E
fficient SVPWM Algorithm
With
Lo
w
Compu
t
atio
nal Ov
erhead for T
h
r
ee-Pha
se In
v
e
rters
," Power Elec
tronic
s
,
IEEE
Tran
sa
ction
s
on, vol. 22, pp. 1797-180
5
,
2007.
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