TELKOM
NIKA
, Vol.12, No
.3, Septembe
r 2014, pp. 5
57~562
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v12i3.78
557
Re
cei
v
ed Ap
ril 4, 2014; Re
vised July
2
3
, 2014; Accept
ed Augu
st 4, 2014
A Different Single-Phase Hybrid Five-Level V
o
ltage-
Source Inverter Using DC-Voltage Mo
dules
Suroso
1
,
Ag
ung Mub
y
arto
1
, Toshihiko Noguc
hi
2
1
Department o
f
Electrical Eng
i
ne
erin
g, Jend
eral So
edirm
an
Universit
y
, Ind
ones
ia
2
Graduate Sch
ools of Electric
al an
d Electro
n
i
cs Engi
neer
in
g, Shizuok
a Un
iversit
y
, Ja
pa
n
e-mail: sur
o
so.
t
e.unsoe
d@
gmail.com
A
b
st
r
a
ct
T
h
is pa
per pr
e
s
ents an
other
circui
t confi
gur
ation
of sing
le-
phas
e hy
br
id fi
ve-lev
el vo
ltag
e-sourc
e
inverter
obta
i
n
ed fro
m
th
e H
-
bridg
e
i
n
verte
r
and
DC-v
o
lt
age mod
u
les. Some
fe
atures
are achi
eve
d
by
usin
g the
pro
p
o
sed
inv
e
rter c
onfig
uratio
n s
u
ch as
it
s mod
u
l
a
r
structure an
d min
i
mu
m nu
mb
er
of
th
e po
w
e
r
devic
es re
qu
ired to
co
nstruc
t the i
n
verter
circuits. T
h
e
p
r
opos
ed fiv
e
-l
e
v
el
inverter
cir
c
uit is
exa
m
in
ed
throug
h co
mp
u
t
er simulati
on
usin
g PSIM so
ftw
are. F
u
rthermor
e
, la
borato
r
y experi
m
enta
l
tests w
e
re al
so
perfor
m
e
d
to
v
e
rify the
pr
ototype
of the
pr
o
pose
d
fiv
e
-lev
e
l
i
n
verter c
i
rcui
ts. T
he co
mput
er si
mulati
on
a
n
d
exper
imenta
l
test results sho
w
s that
the pro
pose
d
hybri
d
five-lev
el volta
g
e
source i
n
vert
er w
o
rks prope
rly
to gener
ate a fi
ve-lev
el volta
g
e
w
a
veform a
n
d
sinus
oid
a
l cu
rrent w
i
th low
harmonics c
onte
n
ts.
Ke
y
w
ords
: vol
t
age-so
urce, in
verter; H-brid
g
e
, five-leve
l
; voltage
mo
dul
e
1. Introduc
tion
The nee
d of high power
conve
r
ter
,
an
d t
he gro
w
th
of modern
power semicondu
ctor
swit
che
s
such as po
we
r MOSFET
an
d IGBT
s bo
o
s
t the research interest in
powe
r
co
nverters
su
ch a
s
multi
l
evel voltage sou
r
ce invert
ers
(MVSI
) a
nd its dual
circuit, multileve
l current
sou
r
ce
inverters (MCSI).
They are
cap
able to g
enerate
a hi
g
h
output po
wer with l
o
wer
gradi
ent volta
ge
or cu
rrent, and higher q
uali
t
y of output waveform
s re
sulting in less
EMI noise an
d smalle
r size
o
f
output filter required by th
e co
nv
erte
r [1]-[4].
The de
sign
ation of
multilevel ine
v
erter in
clud
e
s
the
three
-
level in
verter ci
rcuits, and the inverter
s with mo
re level numb
e
r of output waveform.
Many
topologi
es of multilevel inverters especi
a
lly M
VSI circuits have be
en pre
s
ente
d
and develop
ed
by resea
r
chers.
Three m
a
jo
r varia
n
ts of
MVSI topolog
ies
h
a
ve be
e
n
pre
s
e
n
ted i
n
the literatu
r
es.
These top
o
lo
gies
are the
ca
scade
d H-bridg
e
s M
VSI with sepa
ra
te DC po
we
r sou
r
ce
s, dio
de
clamp
ed MV
SI, and flying capa
cito
rs M
VSI topologie
s
[1]-[5].
The config
uratio
n of
ca
sca
ded H-
bridg
e
MVSI has
a great
advantag
e with
its mo
d
u
lar
circuit configuration.
Nev
e
rt
h
e
le
ss,
t
he
requi
rem
ent
of isolated
DC po
we
r sou
r
ce
s, an
d the
power
swit
ching devi
c
e
count can be
the
sho
r
tage of this inverte
r
.
The topology
of diode clamped MVSI has be
en wi
dely used in high
power ap
plication su
ch a
s
high p
o
wer motor drive.
The third to
pology is the
flying capa
ci
tor
MVSI.
The number
of the
capacitors used in t
he flying capacitor M
VSI
will cause problem
s
such
as the voltag
e balan
cin
g
control of the i
n
terme
d
iate l
e
vel voltages
.
Another vari
ant of MVSI, i.e.
hybrid topolo
g
y have been developed to eliminate so
me dra
w
ba
cks in the three main topologi
es
of MVSI previously defin
ed
.
A circuit co
nfiguratio
n o
f
MVSI achiev
ed usi
n
g
seri
es-conn
ected
sub
-
m
u
ltilevel
conve
r
ter bl
o
c
ks an
d H-bridge inverte
r
wa
s pre
s
e
n
te
d in [6]. Referen
c
e [7] de
scrib
ed a MV
SI
applying H-bridg
e
VSI
and additio
n
a
l bidire
ctio
nal power
swit
che
s
.
Neverthele
s
s, the
bidire
ction
a
l power switch
es u
s
ed in th
e inverter
ci
rcuit co
nfigura
t
ions present
ed in [6] and [7
]
can
be th
e l
a
ck of the
ci
rcuit
s
. In p
r
a
c
tical,
the
bi
dire
ctional p
o
we
r swit
che
s
built by
using
config
uratio
n of
two control
l
ed
po
we
r swi
t
che
s
o
r
com
b
ination
of a
singl
e switch
and fou
r
p
o
wer
diode
s will in
cre
a
se the losses of the inverter.
Anoth
e
r co
nfiguration of MVSI a
ttained from the
c
o
nn
ec
tio
n
of s
e
ve
r
a
l tw
o-
le
ve
l p
o
w
e
r
c
e
lls
w
a
s
pre
s
en
te
d
in
[8].
The requi
rement of ma
ny
controlled
po
wer
switch
es, and splitte
d DC vo
ltag
e so
urce
s will add t
he
cost an
d ci
rcuit
compl
e
xity of the inverter.
Referen
c
e [9] conveyed a
symmetri
c
al
hybrid MVSI comp
osed u
s
ing
three
-
level
ce
lls an
d H-b
r
id
ge invert
er. T
o
tal, eight
po
wer switche
s
are
req
u
ire
d
t
o
create
a five-
level inverter
circuit.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 12, No. 3, September 20
14: 55
7 – 562
558
In this
pape
r,
a different
configuration
o
f
fi
ve-level hy
brid VSI d
e
ve
loped
usi
ng
H-b
r
id
ge
inverter an
d DC-voltage
module
s
, is prop
osed
.
In the propo
se
d topology, the DC volta
g
e
module
s
a
r
e
con
n
e
c
ted in
serie
s
. As a
result it
is possible to util
ize no
n isol
ated DC voltag
e
sou
r
c
e
s
.
All of the controlled po
we
r
swit
che
s
a
r
e
a single
switch
(si
ngle
IGBT or po
wer
MOSFET).
T
he op
eration
and p
e
rfo
r
ma
nce
of the p
r
opo
sed five
-l
evel hybri
d
V
S
I was exami
ned
and ve
rified
thro
ugh
co
mputer si
mu
lations u
s
ing
PSIM Software a
n
d
e
x
perime
n
tally in
laboratory prototype.
2.
Proposed In
v
e
rter Circuit Con
f
igura
t
ion and Its Pr
inciple Oper
ation
2.1.
Opera
t
ion Principle of Propose
d
Inverter Circ
uit
Figure 1 sh
ows the ci
rcuit configu
r
at
ion of
the DC-voltag
e
m
odule, an
d its ba
si
c
operation [10]
.
The pro
p
o
s
ed multilevel
VSI is achi
eved by
conn
ecting the H-b
r
i
dge inve
rter
with
singl
e o
r
m
o
re DC-volta
ge
mod
u
les to
gene
rate
a m
u
ltilevel volta
ge
waveform. Figu
re
2
sho
w
s
the ci
rcuit co
nfiguratio
n of
the
p
r
opo
se
d hybri
d
five-l
evel VSI.
It is clea
r that i
n
this
circuit, all
of
the DC volta
ge
sou
r
ce
s a
r
e
co
nne
cted
in
se
ri
e
s
.
He
nce, non
-i
sol
a
ted DC
voltage so
urce
s ca
n
be a
pplie
d in
this topol
og
y.
Furthe
rmo
r
e, all
po
we
r switch
es a
r
e a
si
ngle
switch, i.e
IG
BT or
power
MOS
F
ET, no
ne
ed bi
dire
ctio
nal p
o
wer
switch.
A
hig
her
num
ber
of output vol
t
age
waveform ca
n be a
c
hi
eve
d
by co
nne
cti
ng
mo
re
DC-voltage mod
u
les. If there
a
r
e
X
DC-volta
ge
-
module
s
con
necte
d to the
H-b
r
idg
e
VSI, the level numbe
r of the
output voltage wavefo
rm
(Y)
can b
e
expre
s
sed a
s
:
X
Y
2
3
(1)
and the count
DC voltage
source
s (V) i
s
:
1
X
V
(2)
In the prop
o
s
ed inve
rter
topology, a single-
pha
se f
i
ve-level VSI need
s a si
n
g
le DC-
voltage mod
u
le and an
H-bri
dge inve
rter with total six power switche
s
.
Table
1 presents t
he
swit
chin
g co
mbination
s
o
f
the propo
sed hybrid
fiv
e
-level VSI for five-level
output voltag
e
waveform g
e
neratio
n, i.e.
V, V/2,
0,
-V/2 an
d
–V voltage
lev
e
ls.
It is
ass
u
med that
the
magnitud
e
s o
f
the DC-volta
ge so
urce
s are the same a
s
V/2 volt.
Figure 1. DC
voltage-m
odu
le, and
its ba
sic o
peration
[10]
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
A Different Single-P
h
as
e Hy
br
id Five-Lev
el Voltage-S
ourc
e
Inveter
Us
ing .... (Suros
o)
559
Figure 2. Pro
posed si
ngle
-
pha
se
hybri
d
five-level VSI
[10]
Table 1. Switchin
g state
s
of hybrid five-level VSI
S
1
S
2
S
3
S
4
S
5
S
6
Output Voltage
0 1
0 1
1 0
V
0 1
0 1
0 1
V/2
0 1
1 0
0 0
0
1 0
1 0
0 1
-V/2
1 0
1 0
1 0
-V
2.2
Pulse
Width Modulation Techniqu
e
In orde
r to ge
nerate
a bett
e
r outp
u
t voltage
waveform, a pulse wi
dth modul
atio
n (PWM
)
techni
que i
s
utilized in the
the propo
se
d inverter
circuits.
In this
pape
r, multi-triang
ula
r
ca
rrie
r
waveforms
with level-shifted si
nu
soidal
PWM techni
que i
s
empl
o
y
ed to gen
erate the gatin
g
sign
als for th
e inverter po
wer
swit
che
s
as sho
w
n in Figure 3 and
Figure 4.
All triangular carrier
waveforms
a
r
e in p
h
a
s
e,
and
with the
same f
r
eq
u
ency.
The f
r
eque
ncy of t
he outp
u
t cu
rre
n
t
waveform is
determi
ned
b
y
the referen
c
e
sinu
soi
dal
wavefo
rm, which i
s
al
so t
he fund
amen
tal
freque
ncy
of
the P
W
M v
o
ltage
wavef
o
rm.
The
freque
ncy
of the tri
angul
ar ca
rri
er wave
form
determi
ne
s the swit
chin
g freque
ncy of
in
verter ci
rcuits [10]-[12].
Figure 3. Modulation
circui
ts of t
he prop
ose
d
five-level inverter
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 12, No. 3, September 20
14: 55
7 – 562
560
Table 2. Te
st para
m
eters
DC po
w
e
r sourc
e
voltage
100 V
Inverter s
w
itching frequenc
y
22 kHz
Load
R
= 20
,
L
= 5 mH
Fundament
al fre
quenc
y
60 Hz
Figure 4. Level-shifted mul
t
i-ca
rrie
r
ba
se
d sinu
soi
dal
PWM
3. Resul
t
s
and
Analy
s
is
Comp
uter
si
mulation
s a
n
d
expe
riment
al test
s a
r
e
con
d
u
c
ted in
ord
e
r to
exa
m
ine the
operation of
the pro
p
o
s
ed
inverter
circuits by
u
s
ing
PSIM software. Thi
s
p
a
rt pre
s
ents so
me
comp
uter
si
mulation a
n
d
experim
enta
l
test re
su
lt
s
of the propo
sed
hybrid
five-level VSI.
The
simulatio
n
p
a
r
amete
r
s a
r
e
pre
s
e
n
ted i
n
Tabl
e 2.
T
he
single
-
p
h
a
se
hybri
d
fi
ve-level VSI
as
s
h
ow
n
in
F
i
gu
r
e
2
is
tes
t
ed
.
The hyb
r
id
five-level VSI circuit is
con
necte
d with a
n
indu
ctive lo
ad,
i.e. resi
stor
R = 20
Ω
, an
d i
ndu
ctor
L =
5
mH.
Th
e swi
t
ching f
r
equ
e
n
cy of the i
n
verter’
s
swit
ch
es
is ch
osen to
be 22
kHz in
orde
r to avoi
d swit
chin
g n
o
ise. Th
e fre
quen
cy of the
output cu
rre
n
t is
60 Hz. Th
e
magnitud
e
of
the DC-volta
ge sou
r
ce is
100 V, ea
ch.
Figure 5
sho
w
s th
e
comp
ute
r
simulatio
n
test re
sults of the pro
p
o
s
ed
hybrid
five-le
v
el VSI. It can be se
en th
at a prope
r five-
level PWM
voltage
wavef
o
rm
wa
s
deli
v
ered to
t
he
load
by the
prop
osed i
n
verter ci
rcuits.
A
s
i
nus
o
idal load c
u
rrent wav
e
form, I
Load
,
also flo
w
s through the lo
ad
.
In order to
verify the o
p
e
ration
of th
e p
r
op
ose
d
hybrid
five-le
v
el VSI co
nfiguratio
n
experim
entall
y
, a laboratory protot
ype o
f
the hybrid fi
ve-level VSI wa
s set-u
p
u
s
ing
MOSFE
T
s
as po
wer
switch
es.
Th
e te
s
t
pa
r
a
me
te
r
s
o
f
th
e e
x
p
e
r
ime
n
t
al c
i
rc
u
i
ts
ar
e s
i
milar
w
i
th th
e
comp
uter
si
mulation p
a
rameters a
s
shown in Ta
bl
e 2. The
DC input voltag
e so
urce
s of
the
inverter
are o
b
tained f
r
om
two-DC po
we
r supllie
s.
Fig
u
re
6
sho
w
s
the prototype
of the hyb
r
id
five-level VSI, presenting t
he main p
o
wer inverte
r
ci
rcuits.
Fig
u
re
7 pre
s
e
n
ts th
e experim
ent
al
test re
sults of
the hybrid fi
ve-level VSI sho
w
in
g the five-level PWM voltage an
d sinu
soi
dal l
oad
curre
n
t waveform
s at
mod
u
lation i
ndex
0.93.
It is sho
w
n th
at the
p
r
opo
se
d
hybri
d
five-level
V
S
I
works
well
ge
neratin
g a
five-level P
W
M
output
voltag
e waveform.
Figure 8
(a)
pre
s
ent
s th
e l
o
w
harm
oni
c co
mpone
nts of
the five-level PWM volt
age
waveform. Furthe
rm
ore, Fig
u
re
8 (b
)
sho
w
s the
harm
oni
c sp
ectra
of the
voltage wa
veform in
clu
d
ing the
swi
t
ching
ha
rm
onic
comp
one
nts
cente
r
ed at 2
2
kHz.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
A Different Single-P
h
as
e Hy
br
id Five-Lev
el Voltage-S
ourc
e
Inveter
Us
ing .... (Suros
o)
561
Figure 5. Five-level voltage
waveform
(V
Load
), load current (I
Load
), drain-sou
r
ce vo
ltage of swit
ch
S
3
(V
S3
), drain
-
so
urce volta
ge of swit
ch
S
5
(V
S5
)
Figure 6. Main power ci
rcu
i
ts of
propo
se
d five-level inverter
Figure 7. Loa
d curre
n
t and
five-level PWM output voltage waveforms
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 12, No. 3, September 20
14: 55
7 – 562
562
(a)
(b)
Figure 8. Harmonic
spe
c
tra of the five-lev
el PWM voltage wavefo
rm: (a) lo
w harmonic
comp
one
nts, (b) in
clu
d
ing t
he switchi
ng
harm
oni
c co
mpone
nts
4.
Conclu
sion
In
this pap
er a
different circuit config
ura
t
ion
of hyb
r
id
five-level VSI ha
s b
een
introdu
ced
and discu
s
se
d.
The
propo
sed
hybri
d
five-level VSI in
co
rpo
r
ate
s
DC-voltag
e
m
o
dule
s
a
nd th
ree-
level H-bri
d
g
e
VSI to prod
uce
a five-lev
el voltage
wa
veform.
Mini
mum count o
f
powe
r
swit
ches
requi
re
d to construct thi
s
topology i
s
a
feature of th
e pro
p
o
s
ed i
n
verter.
Ba
se
d on
comp
uter
simulatio
n
s a
nd expe
rime
ntal test resul
t
s, it
has
bee
n co
nfirme
d t
hat the p
r
op
o
s
ed
hybri
d
five-
level VSI circuits
wo
rks
prop
erly g
e
n
e
rating
a five-level volta
ge waveform
.
A low di
storte
d
sinu
soi
dal loa
d
curre
n
t wav
e
form was al
so attaine
d
u
s
ing the p
r
op
ose
d
inverte
r
.
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