TELKOM
NIKA
, Vol.13, No
.3, Septembe
r 2015, pp. 8
13~819
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v13i3.1426
813
Re
cei
v
ed
Jan
uary 15, 201
5
;
Revi
sed
Ap
ril 24, 2015; Accepted Ma
y
15, 2015
Study and Design of 40 nW CMOS Temperature Sensor
for Space Applications
Abhish
ek
Pa
nde
y
*
, Vija
y
Nath
VLSI Desig
n
L
ab, Birla Institu
t
e of
T
e
c
hnol
o
g
y
Mesr
a, Ran
c
hi Jhark
han
d Indi
a 83
521
5
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: a.p.bitmesra
@gmai
l
.com
A
b
st
r
a
ct
In
the prese
n
t study,
a nove
l
CMOS
temper
ature
s
ensor
b
a
sed
on
su
b-th
resho
l
d MOS
o
perati
o
n
has be
en pre
s
ented, w
h
ich
is desig
ned
for space
an
d
satellite a
ppl
i
c
ations. The
prop
osed CM
OS
temp
eratur
e se
nsor is
e
nunc
i
a
ted
a g
o
o
d
l
i
n
earity b
e
tw
een
temper
atures
rang
e fro
m
-
6
0
O
C to 1
5
0
O
C w
i
th
inacc
u
racy of -1.8
O
C. T
h
is circuit is oper
ated
at supply 1V
a
nd static pow
er
cons
u
m
pti
on 4
0nW
at 150
O
C is
achi
eved. T
h
e
circuit util
i
z
e
s
t
he te
mp
eratur
e de
pe
nde
ncy
of thresho
l
d v
o
ltage
of MOSF
ET
, w
h
ich give
s
tw
o types of voltag
e i
n
out
p
u
t, first voltag
e pro
porti
ona
l
to abs
olute t
e
mper
ature (P
T
A
T
)
and sec
ond,
neg
ative te
mp
erature c
oeffici
ent (NT
C
). T
h
e s
ens
itivity of
both PT
AT
a
nd NT
C
is 0.
1
639
0
m
V/
o
C an
d
0.176
07
mV/
o
C
respective
ly b
e
tw
een the sp
ecifie
d rang
e -60
O
C to 150
O
C. This circuit is design
ed
&
simulat
ed us
in
g Ca
denc
e a
n
a
lo
g & di
gita
l
desi
gn to
ols U
M
C90
n
m CMOS techno
lo
gy. T
he lay
out ar
e
a
of
the circuit is 17
.213
μ
m
ൈ
6.655
μ
m.
.
Ke
y
w
ords
:
C
M
OS;
comp
le
me
ntary meta
l oxid
e
se
mic
o
n
ductor,
te
mp
er
ature se
nsor, P
T
AT
, proportio
nal t
o
abso
l
ute te
mp
erature, NT
C, neg
ative te
mp
erature co
effici
ent, low
pow
er
Copy
right
©
2015 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1.
Introduc
tion
Tempe
r
atu
r
e
is very import
ant physi
cal
quantity
in ou
r daily life. It
is appli
ed in variou
s
fields such a
s
indust
r
ial, m
edical, spa
c
e
and defe
n
se etc. In aircraft
, the tempera
t
ure monito
rin
g
play importa
nt role in fuel con
s
um
ption, env
iron
mental co
oli
ng syste
m
s,
oil in hydraulic,
lubri
c
ating
system, fluid in cool
ant, heati
ng syst
em
s a
nd avioni
cs
systems [1]. Today it’s hea
vy
deman
d of th
e CM
OS tem
peratu
r
e
sen
s
or du
e to
use in th
erm
a
l
manag
eme
n
t. The
advanta
g
e
of CMOS b
a
se
d efficien
t temperatu
r
e sen
s
o
r
is monitorin
g
the st
eady i
n
crea
se of
heat
dissipatio
n in
different sy
stem. It is req
u
ired
to track the pro
c
e
s
s te
mperature
and regul
ate its
cooli
ng fan.
Tempe
r
atu
r
e sen
s
o
r
s are commonly
divi
ded
into
two type (a
): conv
entional
sen
s
ors
(b
):
sma
r
t se
nsors. The
conve
n
tional temp
e
r
ature
sen
s
ors are havin
g nume
r
ou
s d
r
awb
a
cks wh
e
n
comp
ared to
the
sma
r
t t
e
mpe
r
ature
sen
s
o
r
s
spe
c
ially ma
nuf
actured
in
CMOS technol
ogy
con
s
umi
ng m
o
re p
o
wer d
u
e
to the larg
er a
r
ea, le
ss accurate an
d non
-line
a
rit
y
[2]. The smart
temperature
sen
s
o
r
can
dire
ctly com
m
unicate wi
t
h
a microco
n
trolle
r / microp
ro
ce
ssor i
n
a
stand
ard di
gital format, result redu
cing t
he com
p
lexity and enha
nce
the resp
on
se
of the system.
CMOS Sma
r
t temperature
sen
s
o
r
ci
rcuit
con
s
i
s
t
temp
eratu
r
e
cell ci
rcuit, its
sign
al co
nditionin
g
circuit and A
nalog to digit
a
l converter
[3]. In
silicon based MOS
F
ET t
here i
s
much property
whi
c
h
dep
en
ds
on te
mpe
r
ature.
On th
e
ba
sis of lite
r
ature
re
port, t
he
sma
r
t tem
peratu
r
e
sen
s
or
further d
e
si
g
ned in to (i) Parasiti
c BJT based tem
peratu
r
e
sen
s
or, (ii
)
del
a
y
-Inverter b
a
s
ed
temperature
sen
s
o
r
, (iii) T
h
re
shol
d voltage tempe
r
at
ure sen
s
o
r
.
CMOS te
chn
o
logy is
use
d
to re
alize
parasiti
c
BJTs
whi
c
h b
a
s
ed
on late
ral PNP
transi
s
to
rs h
a
ve be
en
re
alize
d
achie
v
e ch
allen
g
e
s
relate
d to t
e
mpe
r
ature
sensi
ng li
ke
l
e
ss
accuracy, co
nsumi
ng mo
re power, an
d occupy
in
g a large a
r
ea.
Now
CMOS
technol
ogy is
gro
w
ing
and
semi
con
d
u
c
tor ind
u
st
ry a
dopted thi
s
t
e
ch
nolo
g
y fre
quently du
e to low fa
bri
c
at
ion
co
st and ea
sy fabrication
pro
c
e
ss. Th
e
temperatu
r
e
-
sen
s
in
g accu
racy of BJT
s
is limited by the
effect
of
thei
r saturation cu
rrent (I
S
), which can l
ead
to
errors of
a fe
w d
egree
s. B
u
t this
erro
r
can
be red
u
ced ±0.1 by using t
he cali
bratio
n
[4-7]. Since for re
du
cing t
he ina
c
cura
cy, the calibrat
i
on
techni
que i
s
need
ed, but
this in
crease
s
the
co
st
o
f
the system
. The bip
o
lar techn
o
logy i
s
comp
atible
with tempe
r
ature sen
s
in
g system
s. It was also
much mo
re accurate than
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 3, September 20
15 : 813 – 819
814
conve
n
tional
tempe
r
atu
r
e
se
nsor. B
u
t there a
r
e
use
at l
east
two
PNP t
r
ansi
s
tors,
re
sult
incr
ea
se
s t
h
e
size of
t
he c
h
ip.
Propa
gation
delay-b
ased temperature
sen
s
o
r
i
s
d
e
sig
ned
on
the con
c
ept
of the
prop
agatio
n delay of inverters. Delay lin
e based temp
eratu
r
e sen
s
or con
s
ume
s
less po
wer th
an
a parasiti
c
B
J
T
s
tempe
r
at
ure
sen
s
o
r
.
The del
ay is
a functio
n
o
f
temperatu
r
e
for this type
of
sen
s
o
r
. For the digitizatio
n
we nee
d time to digi
tal conve
r
ter. Su
bse
que
ntly, the output pul
se is
fed to the inp
u
t of a cy
clic
Time-to
-
Di
gital Co
nv
erte
r (TDC) to g
ene
rate the
co
rre
s
po
ndin
g
digi
tal
[8-10]. The same tech
niq
ue ca
n be al
so be impl
e
m
ented in a
nother
way b
y
measu
r
ing
the
variation i
n
f
r
equency of
oscilla
tion caused by vari
ation in
tem
perature. The
frequency is
inversely p
r
o
portion
al to t
e
mpe
r
ature
becau
se
th
e
de
cre
a
se in
the mo
bility is th
e d
o
mi
nant
feature [1
1-1
2
]. Both of these
kin
d
s of
sen
s
o
r
s
re
qui
re a l
a
rger
ch
ip area a
nd p
r
odu
ce
s
difficulty
in attaining lin
earity for the highe
r ra
nge.
To overcome
the limitation of CMOS techn
o
logie
s
in
various tem
peratu
r
e
sen
s
ors (as
discu
s
sed ab
ove), we o
p
te
d thre
shold v
o
ltage, temp
e
r
ature se
nsor with for
the a
pplication in the
avionic
syste
m
, owing to
good a
c
cu
ra
cy with
mini
mum po
we
r con
s
um
ption.
The tempe
r
ature
sen
s
o
r
s ba
sed on th
e t
h
re
shol
d voltage of M
O
S
F
ETs a
r
e
known for th
eir lo
we
r po
wer
con
s
um
ption
and
smalle
r
die area [13
-
16]. The voltage o
r
curre
n
t across M
O
SFETs i
s
al
ways
varies
with th
e temperature, but the ch
alleng
e
is de
signi
ng the
s
e
types of sen
s
ors i
s
accu
racy.
Becau
s
e lin
e
a
rize this vari
ation is a diffi
cult ta
sk. Thi
s
task is a
ccomplished by
prop
er
sele
ction
of circuit arch
itecture
and a
d
justin
g the W/L ratio
of the tran
sist
ors used
so that
the non-li
nea
rity
can b
e
red
u
ced.
The rest
of this p
ape
r h
a
s
be
en o
r
g
a
n
i
zed
as foll
o
w
s. T
he
cha
r
acteri
stic of
MOSFET
operating
in
Basic Pri
n
ci
p
l
e of M
O
SF
ET ba
sed
te
mperature
sensor
is
giv
en in
Se
ctio
n II.
Section III describes the
methodol
ogy
and architec
ture of the proposed tem
perature
sensor
circuit. The
simulation result and di
scu
ssi
on ha
s b
e
en su
mma
rized in Sectio
n
IV. Finally, the
conclusion of the overall paper
is illustrated in Section
V.
2. Basic
Princi
ple
The
small
si
g
nal a
nalysi
s
t
he
squ
a
re
la
w of
mod
e
l i
s
not lo
nge
r
h
o
lds true.
Th
erefo
r
e,
we cann
ot negle
c
t the se
con
d
ord
e
r e
ffect. The se
con
d
ord
e
r e
ffect will cau
s
e tempe
r
atu
r
e
nonlin
earity.
On
chip th
ermal sen
s
ing
demon
strates
seve
ral d
e
g
r
ee Celsi
u
s te
mperature
errors [16]
due to n
onlin
earity. For
short chan
nel
device
s
,
the
effect of velo
city saturatio
n
and m
obility
degradatio
n o
n
the drain
cu
rre
nt in the sa
turation regio
n
[17-20] is d
e
fined a
s
:
DSn
Tn
GSn
V
V
V
0
sat
Tn
GSn
ox
n
D
lV
V
V
l
w
c
I
2
1
2
(1)
Whe
r
e,
GSn
V
= Gate
Sou
r
ce voltag
e
DSn
V
=
Drai
n Sou
r
ce
voltage
Tn
V
=Th
r
esh
o
ld voltag
e
D
I
=
drain
curre
n
t of MOS transistor
n
= mobility of N-type material
ox
c
= oxide capa
citan
c
e
w
= ch
ann
el wi
dth of MOS transi
s
tor
l
= ch
annel le
ngth
of MOS transistor
sat
V
=
n
E =
s
m
/
10
7
c
o
ns
tant s
a
t
u
ration veloc
i
ty
= fitting parameter
1
7
/
10
V
t
ox
The d
r
ain
cu
rrent i
s
temp
e
r
ature de
pen
den
ce
of
CM
OS tran
sisto
r
dire
ctly. Since d
r
ai
n
curre
n
t de
pe
nds up
on the
thre
shol
d vo
ltage a
nd the
mobility. Th
e thre
sh
old v
o
ltage
depe
n
d
s
upon temp
erature a
s
sh
o
w
n in eq
uatio
n (2-3):- [21
-
2
2
].
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Study and
De
sign of 40 n
W
CMOS Tem
peratu
r
e Sen
s
or for Spa
c
e
…
(Abhi
she
k
Pande
y)
815
Whe
r
e
F
SB
F
to
t
V
V
V
2
2
(2)
And,
ox
F
SUB
si
F
FB
SB
t
to
c
N
q
V
V
V
V
2
2
2
)
0
(
(3)
Whe
r
e,
Bulk Th
re
sho
l
d Voltage,
F
Strong Inversi
on Surfa
c
e P
o
tential,
FB
V
=Fla
t Band
Voltage,
SS
Q
Oxid
e-cha
r
ge
=
SS
qN
,
k
B
o
lt
zman
n’s
con
s
t
ant
,
T
Temperature (K
),
i
n
Intrins
i
c
c
a
rrier c
o
ncentration.
0
0
T
T
k
T
V
T
V
(4)
From Eq
uation (4
) it is
proved th
at Thre
sh
old vo
ltage de
crea
se
s with in
crea
sing
temperature
hen
ce th
e d
r
ain
curre
n
t in
cre
a
se. Th
er
efore
the
drai
n current i
n
creases.
Thi
s
i
s
the
reverse d
epe
nden
ce.
In MOS device mo
bility is impo
rtant
para
m
et
ers t
hat are
pre
d
o
minantly se
nsitive to
temperature.
Theo
retically Mobility of th
e carr
ie
r in the cha
nnel
ca
n be define
d
as [23-24].
k
T
T
T
T
0
0
).
(
(5)\
Whe
r
e,
0
T
= Refe
ren
c
e
temperature
T
= Absolute temperature
Whe
r
e
k
= co
nstant val
ue
betwe
en
-1.2
and
2.
42
around
ro
om te
mperature,
causi
n
g
the mobility
decrea
s
e
by about h
a
lf a pe
rcent
pe
r de
gre
e
. Th
e expression
for the
cha
nne
l
mobility can
be furthe
r co
mplicate
d
by introdu
ci
n
g
velocity satu
ra
tion and mob
ility degradati
on.
This word m
eans that the mobilit
y at t
he
reference
temperature
)
(
0
T
depe
nd
s u
p
o
n
the
bias voltag
e
and the threshold voltage.
As tempe
r
atu
r
e in
cre
a
ses,
the ca
rrie
r
m
obility decrea
s
e
s
and re
sultin
g drain
cu
rre
nt decrea
s
e
s
. T
h
is is the n
o
rmal depe
nde
nce.
Thre
sh
old Vo
ltage variatio
n with the temperature
3. Proposed
Circuit
The
sch
emat
ic dia
g
ra
m o
f
temperatu
r
e se
ns
or
circuit is
sh
own in Figu
re
1. The
prop
osed
circuit i
s
ma
de
by 4
NMO
S
and
3 PM
OS
tran
si
stors. Since
in
NMOS
t
r
an
si
stor,
mobility is hi
gher th
an the
PMOS, therefore it is
wo
rkin
g a
s
bett
e
r switch and
PMOS work as
better loa
d
. The loa
d
is
workin
g a
s
a re
sista
n
ce
and the re
sista
n
ce is d
i
rectly rel
a
te
d to
temperature.
The both o
u
tput PTAT an
d NT
C volt
ag
es have b
e
e
n
extracte
d. In the pro
p
o
s
ed
desi
gn the
transi
s
tors PM
1, PM2 an
d
PM3 a
c
t as
active loa
d
,
whi
c
h fo
rm t
he
current
m
i
rro
r
throug
h tran
sistors PM
3,
PM2 an
d PM
1. Fro
m
e
q
u
a
tion
(6) it i
s
cle
a
r that th
e a
s
pe
ct
rati
o of
PM2 an
d PM
3 de
cid
ed th
e
natu
r
e
of te
mperatur
e
vs voltage. Sin
c
e PM2
and
P
M
3 form
current
mirro
r the
r
efo
r
e the
aspe
ct ratio of PM
2
and PM
3 sh
ould b
e
sam
e
. This
sa
me
cu
rre
nt mirror
help
s
in o
b
tai
n
ing the volta
ge du
e to diff
eren
ce
in
current flo
w
. The
W/L ratios
of the tran
si
stors
config
ure
d
as active re
sisto
r
s a
r
e al
so su
itabl
y adjuste
d for linea
riza
tion of the output voltages.
The
tra
n
si
sto
r
s NM1 and NM2
a
nd NM
3,
NM4
a
r
e i
m
porta
nt in term
s of controlling the
NTC o
u
tput voltage ra
nge
with re
spe
c
t to the
temperature range.
This outp
u
t voltage ra
nge
is
given by the
W/L ratios of
these
tra
n
si
stors. F
r
om
eq
uation
(7) it i
s
clea
r that t
he
NTC volta
g
e
depe
nd
s up
on the aspe
ct ratio of tran
sisto
r
NM
1 and NM
2. For co
ntroll
ing the po
wer
con
s
um
ption
of the ci
rcuit
the
tran
si
stor NM3
and
NM4 are very i
m
porta
nt. Th
e bia
s
ing
cu
rrent
sho
u
ld be o
p
timized p
r
o
perly becau
se it not only
limits the powe
r
co
nsum
ption of
the circuit, bu
t
also d
e
fine
s the upp
er limit
of t
he temperature to be sensed [15].
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 3, September 20
15 : 813 – 819
816
Figure 1. Circuit diagra
m
of CMOS Temp
eratu
r
e Sen
s
or Cell
T
N
P
P
T
PTAT
V
k
V
V
1
12
23
23
2
3
1
(6)
T
N
P
N
T
NTC
V
k
V
V
2
12
23
12
3
2
1
(7)
Whe
r
e
3
3
2
2
23
P
P
P
P
P
L
W
L
W
Whe
r
e
2
2
1
1
12
N
N
N
N
N
L
W
L
W
4.
Simulation Result &
Disc
ussion
The propo
se
d temperat
ure sen
s
o
r
circuit ha
s be
en simul
a
ted
in Analog De
sign
Environme
n
t
of Ca
den
ce
u
s
ing
UMC9
0n
m library. Thi
s
circuit
uses a 1V
supply.
The
PTAT a
n
d
NTC charact
e
risti
c
s have
been
extra
c
ted from
th
e
circuit. Th
e
pro
p
o
s
ed
ci
rcuit
ha
s be
en
desi
gne
d for
sen
s
in
g temp
eratu
r
e fro
m
-60
o
C to 150
o
C and
sho
w
s a go
od lin
earity betwee
n
these
ra
nge
s. The PTAT
voltage giv
e
s a
n
outp
u
t voltage of
384.51
987m
V at -60
o
C and
418.93
929
at
150
o
C. The
sensitivity for V
PT
AT
is 0.1
6390mV/
o
C. The NT
C
vol
t
age sho
w
s an
output voltag
e of 6
75.44
5
97mV to
639
.
35949mV
for the tem
perature
ra
nge
of
-60
o
C to
150
o
C
respe
c
tively with a
sen
s
itivity of 0.1760
7mV/
o
C. Both
V
PT
AT
an
d V
NT
C
cu
rves
ha
s
bee
n sho
w
n
in
Figure 2(a
)
.
The maximu
m deviation from a
c
tual value
at any given temperature in between the
spe
c
ified ran
ge of the sensor is
kn
own a
s
ina
c
curacy of a
n
y temperat
ure sen
s
o
r
. The
inaccu
ra
cy of NTC voltage
in a specifie
d rang
e of the prop
osed sensor is -1.8
o
C re
spe
c
tiv
e
l
y
.
The erro
r of NTC
sh
ows
better than
t
he PTAT. The error
curve
s
for V
NT
C
are given in Fi
gure
2(b
)
.
The circuit h
a
s bee
n sim
u
lated at
different
process co
rne
r
s
to get
the wo
rst
ope
ratin
g
con
d
ition
s
. In semi
con
d
u
c
tor p
r
odu
ct m
anufa
c
turin
g
, a pro
c
e
s
s corne
r
meth
od
is used for I
C
fabrication of
semi
con
d
u
c
tor wafers. In pro
c
e
ss
co
rner i
s
nami
n
g conve
n
tion
for to use t
w
o-
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Study and
De
sign of 40 n
W
CMOS Tem
peratu
r
e Sen
s
or for Spa
c
e
…
(Abhi
she
k
Pande
y)
817
letter, beca
u
se two types o
f
MOSFET used in
CMOS
technol
ogy: namely NM
O
S
for n-ch
ann
el
and PM
OS fo
r p
-
chan
nel.
On b
ehalf
of t
he m
obility
of
MOS tran
sist
or th
ere
a
r
e t
h
ree
type
co
rner
rule
s: (i) typical (t), (ii) fast
(f) and (iii
) sl
ow(s), whi
c
h use
d
fast
and
slow for
carri
e
r mobility that
is hi
ghe
r
and
lower than
n
o
rmal,
re
sp
ectively. There
are
five p
r
o
c
ess
co
rne
r
s [
25] a
r
e i
n
volved
to simul
a
ted
my proposed circuit
namely: (i) typica
l-typical (tt),
(ii
)
fast
-f
ast (ff),
(iii)
slow-slow
(ss), (iv) fast
-slow (fnsp), and (v
) slow-fast (snfp). The (i) to (
iii) is called even
corners because
both types
of device
s
a
ffected same
, hence t
here are
no a
d
verse effect
of the logi
cal
corre
c
tne
s
s
of the
circuit
.
This me
an
s the
dev
i
c
e
s
can
op
erate
at slo
w
e
r
or
fa
ster clo
c
k
freque
nci
e
s.
The last two
pro
c
e
ss
corn
ers a
r
e calle
d as ske
w
ed
corn
er an
d come to con
c
ern
corners.
That
is
why i
n
the MOSFET,
NMOS
w
ill
switch much faster
than the PMOS. Thi
s
rep
r
e
s
ent
s
i
m
balan
ce
d switchi
ng ca
n cau
s
e
on
e
e
dge
of the
ou
tput to have
a mu
ch
le
ss
sle
w
than the oth
e
r edg
e. The
Figure 3
(
a)
& Figure 3
(
b
)
sho
w
s the simulate
d re
sult at different
pro
c
e
ss
co
rn
er of PTAT and NT
C re
sp
ectively.
Figure 2(a
)
. Output Voltag
e of Senso
r
with
variation of T
e
mpe
r
ature
Figure 2(b
)
. V
NT
C
Erro
r of temperature
cel
l
Figure 3(a
)
. T
e
mpe
r
ature vs Voltage g
r
a
ph at
different process co
rne
r
in
UMC 9
0nm
techn
o
logy of
VPTAT CMOS Temperature
Senso
r
Figure 3(b
)
.T
empe
rature vs Voltage g
r
a
ph at
different process co
rne
r
in
UMC 9
0nm
techn
o
logy of
VNTC CMO
S
Temperature
Senso
r
Since po
wer con
s
um
ption of
any
CMO
S
circui
t in
creases with i
n
cre
a
si
ng tem
peratu
r
e.
The ci
rcuit draws 40nA
cu
rrent from
the
circuit, whi
c
h
is sh
own in
Fi
gure
4. There
f
ore the ove
r
all
resultant po
wer dissip
ation
of t
he propo
sed se
nsor is
40n
W at 150
o
C.
The layo
ut o
f
prop
osed
circuit i
s
sh
o
w
n i
n
Fig
u
re
5. The
layo
ut are
a
of th
e cell is
17.213
μ
m
ൈ
6.655
μ
m. The
desi
gne
d layout of the cell is fina
lly checked with DRC, it is fully error
free and fully matche
d with
LVS.
In Table
1 the
pro
p
o
s
ed
te
mperature
se
nso
r
h
a
s be
e
n
compa
r
ed
with recent
works. T
h
e
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 3, September 20
15 : 813 – 819
818
V
NT
C
from the
desi
gne
d se
nso
r
i
s
cho
s
e
n
for
comp
ari
s
on
as it p
r
o
d
u
ce
s b
e
tter result tha
n
V
PT
AT
.
From th
e tab
l
e it ca
n be
see
n
that the
power
dissip
ation an
d ina
c
cura
cy i
s
be
tter than oth
e
r
result, while t
he tem
peratu
r
e
ran
ge i
s
q
u
ite la
rge.
Th
e
ina
c
cu
racy
incr
ea
se
s wit
h
r
ang
e.
B
u
t
,
t
h
e
prop
osed de
sign maintain
s the inaccura
cy in che
c
k, well withi
n
-1.
8
o
C.
Figure 4. Dra
w
n current fro
m
powe
r
sup
p
ly of CMOS Tempe
r
atu
r
e
Senso
r
Cell
Table 1. Perf
orma
nce Summary & Co
mpari
s
o
n
of propo
se
d temp
eratu
r
e sen
s
o
r
with re
ce
nt
wor
k
s
Parameter
[12]
[15]
[26]
This
w
o
rk
Technolog
y
1 µm
90 nm
180 nm
90 nm
Power Suppl
y
1 V
1 V
0.6–2.5 V
1 V
Temper
ature
Ra
nge()
+10 to +100
o
C
-60 to 150
o
C +1
0
to120
o
C -
6
0
to150
o
C
Inaccurac
y
w
i
th Temper
ature
+1
o
C
±1.3
o
C ±
2
o
C -
1
.
8
o
C
Power Co
nsumpt
ion
100 µW
862 nW
7 nW at 0.6V
40 nW
Circuit Area
-
-
0.002 mm
2
114.55
µm
2
Figure 5. Layout of Propo
sed Temp
erat
ure Sen
s
o
r
Cell
5. Conclu
sion
The
circuit
de
sign
ed
and
si
mulated
u
s
in
g cade
nce a
n
a
log
and
digit
a
l sy
stem
de
sign tool
UMC90 nm t
e
chnology. The temperature sensor
circuit presented in th
is paper utilizes the
variation in t
h
re
shol
d voltage
with tem
peratu
r
e to
p
r
odu
ce PTA
T
and
NTC vol
t
age si
gnal.
The
NTC voltage
prod
uces bett
e
r result in te
rms
of
a
c
curacy for th
e d
e
sig
ned
se
nsor. Mo
reove
r
the
circuit sen
s
e
s
for tempe
r
at
ure
ran
ge of
-60
o
C to 15
0
o
C, whi
c
h i
s
sprea
d
ove
r
2
10 de
gre
e
s.
The
accuracy
of the
circuit i
s
a
l
so
quite g
o
o
d
in
spe
c
ified
ran
ge
of te
mperature
ra
nge. T
he l
a
yout
area of this
circuit is 17.
213
μ
m
ൈ
6.655
μ
m and its powe
r
dissi
pation is 40
nW. Since t
h
e
prop
osed
se
nso
r
se
nses
for a wide
sp
read ra
nge
of
tempe
r
atu
r
e with satisfa
c
t
o
ry
a
c
curacy
the
sen
s
o
r
ca
n find its appli
c
at
ion in military and ae
ro
spa
c
e appli
c
ation
s
.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Study and
De
sign of 40 n
W
CMOS Tem
peratu
r
e Sen
s
or for Spa
c
e
…
(Abhi
she
k
Pande
y)
819
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g
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y
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w
e
r C
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