TELK
OMNIKA
,
V
ol.
15,
No
.
1,
March
2017,
pp
.
28
35
ISSN:
1693-6930,
accredited
A
b
y
DIKTI,
Decree
No:
58/DIKTI/K
ep/2013
DOI:
10.12928/telk
omnika.v15.i1.3161
28
FPGA-based
Digital
Baseband
T
ransmission
System
P
erf
ormance
T
ester
Resear
c
h
and
Design
Huimin
Duan*
,
J
uanjuan
Gu
,
Guohua
Hu
,
and
Qian
Zhang
Hef
ei
Univ
ersity
No
.99
jinxiu
A
v
en
ue
,
Hef
ei,
Anhui
Pro
vince
,
China.
+86-551-62158571
*Corresponding
author
,
email:
123667426@qq.com,
duan@hfuu.edu.cn
Abstract
Comm
unication
System
T
r
ansmission
P
erf
or
mance
T
ester
,
as
a
digital
comm
unication
system
de-
sign
and
testing
equipment,
pla
ys
an
impor
tant
role
in
the
constr
uction
and
daily
maintenance
of
the
com-
m
unication
system.
The
paper
presents
a
kind
of
tester
,
which
is
designed
using
Cyclone
IV
FPGA
(Field
Prog
r
ammab
le
Gata
Arr
a
y)
and
VHDL
(
V
er
y
High
Speed
Integ
r
ated
Circuits
Hardw
are
Descr
iption
Lan-
guage).
According
to
the
f
eatures
in
the
e
y
e
diag
r
am,
the
system
perf
or
mance
can
in
tuitiv
ely
and
qualita-
tiv
ely
e
v
aluated.
The
results
pr
o
v
e
that
the
system
accur
ately
displa
y
ed
the
e
y
e
diag
r
am,
thereb
y
reflected
the
perf
or
mance
of
the
baseband
tr
ansmission
system
tr
uthfully
.
K
e
yw
or
d:
comm
unication
system,tr
ansmission
perf
or
mance
,FPGA,
bit
synchronization,e
y
e
diag
r
am
Cop
yright
c
2017
Univer
sitas
Ahmad
Dahlan.
All
rights
reser
ved.
1.
Intr
oduction
With
the
de
v
elopment
of
comm
unication
technology
,
comm
unication
systems
are
becom-
ing
increasingly
complicated.
Accur
ate
quantitativ
e
analysis
of
the
perf
or
mance
of
an
actual
base-
band
tr
ansmission
system
is
tedious
and
complicated
or
e
v
en
impossib
le[1].
Especially
in
the
de-
b
ugging
and
maintenance
procedures
,
system
perf
or
mance
ma
y
be
v
ar
ied
in
an
y
time
,
a
simple
method
to
qualitativ
ely
monitor
ing
the
system
perf
or
mance
is
then
more
needed
[2,
3].
Comm
u-
nication
system
tr
ansmission
perf
or
mance
tester
pla
ys
an
impor
tant
role
in
this
field.
FPGA
(Field
Prog
r
ammab
le
Gata
Arr
a
y)
technology
has
f
eatures
such
as
the
fle
xib
le
architecture
and
logic
unit,
high
integ
r
ation
and
a
wide
scope
of
applicability[4,
5,
6].
Apply
it
to
the
tr
aditional
tester
,
w
e
can
achie
v
e
the
f
ollo
wing
benefits:
impro
ving
the
accur
acy
of
the
testing
e
y
e
diag
r
am.,
e
xpanding
the
analytical
bandwidth
of
the
system,
in
creasing
the
anti-interf
erence
and
impro
ving
the
efficiency
of
real-time
e
x
ecution[7].
2.
Overall
Design
As
sho
wn
in
the
Figure
1,the
system
mainly
consists
of
f
our
modules:
the
tr
ansmitter
,
the
channel,
the
noise
source
,
the
receiv
er
.
Based
on
FPGA,
the
tr
ansmitter
produces
a
le
v
el-
f
our
and
a
le
v
el-tw
elv
e
pseudo-r
andom
sequences
,
which
are
then
be
tr
ansmitted
used
to
be
inf
or
mation
source
and
channel
noise
.
In
the
channel
par
t,
there
are
three
kinds
of
LPF
(Lo
w
P
ass
Filter)
with
three
diff
erent
cutoff
frequencies
which
can
be
used
to
sim
ulate
the
channel
with
diff
erent
bandwidths[8].
At
the
receiving
end,
the
re
ceiv
ed
signal
is
applied
as
the
input
signal
of
the
oscilloscope
,
while
the
bit
synchronous
cloc
k
is
used
as
the
scanning
synchronizing
signal,
an
e
y
e
diag
r
am
is
then
obtained[9].
The
bit
synchronous
cloc
k
is
a
v
er
y
impor
tant
issue
in
digital
comm
unicat
ion
systems
.
Only
to
e
xtr
act
the
correct
timing
pulses
,
the
receiv
er
can
obtain
the
steady
e
y
e
diag
r
ams
,
then
mak
es
accur
ately
sampling
decision
and
reco
v
ers
the
digital
baseband
signals
.
It
directly
aff
ects
the
o
v
er
all
perf
or
mance
of
the
entire
digital
comm
unications
system[2,
3].
In
this
study
,
w
e
use
DPLL
method
to
e
xtr
act
bit
synchronous
cloc
k
signal.
Receiv
ed
September
7,
2016;
Re
vised
December
30,
2016;
Accepted
J
an
uar
y
14,
2017
Evaluation Warning : The document was created with Spire.PDF for Python.
TELK
OMNIKA
ISSN:
1693-6930
29
Figure
1.
Diag
r
am
of
system
design
3.
Resear
c
h
Method
3.1.
Pseudo-random
sequence
and
Manc
hester
coding
module
Based
on
FPGA,
according
to
f
or
m
ula
(1),the
circuit
of
these
tw
o
modules
is
designed
using
VHDL,
and
its
sim
ulation
results
are
sho
wn
in
Figure
2[10],
[11].
f
(
x
)
=
(1
+
x
3
+
x
4
)
(1)
Figure
2.
Results
of
pseudo-r
andom
sequence
and
Manchester
coding
module
In
the
picture:
clk
is
the
w
or
king
cloc
k;
datain
is
the
pseudo-r
andom
sequence
output;
datamout
is
the
Manchester
coding
output.
3.2.
Digital
Phase-Loc
ked
Loop
Module
This
module
is
designed
b
y
using
of
VHDL
and
its
top-le
v
el
module
is
sho
wn
in
Figure
3.
It
includes
in
total
fiv
e
sub-modules:
a
diff
erential
phase
detector
,
an
impro
v
ed
digital
filter
,
bipolar
cloc
k
source
,
controller
,
and
frequency
divider[9],
[12].
T
w
o
of
which
are
impor
tant
and
descr
ibed
belo
w
.
Figure
3.
Scheme
of
digital
PLL
top-le
v
el
module
T
r
ansmission
System
P
erf
or
mance
T
ester
(Huimin
Duan)
Evaluation Warning : The document was created with Spire.PDF for Python.
30
ISSN:
1693-6930
3.2.1.
Diff
erential
Phase
Detector
Module
Diff
erential
phase
detector
is
composed
of
diff
erential
circui
and
a
phase
compar
ator
cir-
cuit
which
consists
of
tw
o
AND
gates
,
as
sho
wn
in
Figure
4.
Figure
4.
Scheme
of
diff
erential
phase
detector
After
the
diff
erential
circuit,
the
input
digital
signal
INSIGNAL
(Manchester
code)
is
output
to
B
as
the
edge
detection
signal,
corresponding
to
the
inp
ut
signal.
Its
sim
ulation
diag
r
am
is
sho
wn
in
Figure
5.
Figure
5.
Sim
ulation
diag
r
am
of
the
edge
detection
signal
Edge
detection
signal
B
are
respectiv
ely
applied
to
tw
o
AND
gates:
the
deduction
gate
AND2
and
the
addition
gate
AND3
(in
Figure
4).
If
CLK
is
ahead
of
B,
then
AND3
is
b
loc
k
ed,
and
AND2
sents
a
leading
pulse
D,
as
sho
wn
in
Figure
6.
If
CLK
lags
behind
B,
deduction
gate
AND2
closed,
addition
gate
AND3
then
sents
a
lagging
pulse
E,
as
sho
wn
in
Figure
7.
3.2.2.
Contr
oller
Module
Implemented
b
y
CycloneIV
FPGA,
the
controller
module
consists
of
deductions
gate
and
addition
gate
.
The
opening
and
closing
of
the
gates
are
controlled
b
y
Dela
y
Flip-flops
.
The
circuit
diag
r
am
of
the
controller
module
is
sho
wn
in
Figure
8.
When
compar
ing
the
local
bit
synchronous
cloc
k
signal
CLK
to
the
edge
detection
signal
B,
the
w
or
king
status
of
the
controller
ha
v
e
f
our
diff
erent
situations:
(1)
CLK
ahead
of
B
As
sho
wn
in
Figure
9,
G
and
H
are
bi-phase
cloc
k
pulses
.
when
the
CLK
is
ahead
of
B,
leading
pulse
D
becomes
positiv
e
pulse
.
At
the
r
ising
edge
of
H,
the
le
v
el
of
the
re
v
erse
control
signal
CONTRAL
Q
changes
from
high
to
lo
w
,
making
that
the
deduction
gate
opens
a
tr
igger
cycle
and
a
pulse
is
deduct
ed
from
G,thereb
y
deducting
a
pulse
to
the
bit
synchronization
signal
I
bef
ore
the
frequency
dividing,
and
making
that
the
phase
of
CLK
is
lagging
b
y
a
per
iod
of
H.
Figure
6.
Sim
ulation
result
of
the
leading
pulse
D
Figure
7.
Sim
ulation
result
of
dela
ying
pulse
E
TELK
OMNIKA
V
ol.
15,
No
.
1,
March
2017
:
28
35
Evaluation Warning : The document was created with Spire.PDF for Python.
TELK
OMNIKA
ISSN:
1693-6930
31
Figure
8.
Sim
ulation
diag
r
am
of
the
control
module
Figure
9.
Sim
ulation
diag
r
am
when
CLK
ahead
of
B
(2)
CLK
lags
behind
B
As
sho
wn
in
Figure
10,
when
the
CLK
is
lagging
behind
”B,
lagging
pulse
E
becomes
positiv
e
pulse
.
At
the
r
ising
edge
of
”H,
the
le
v
el
of
the
re
v
erse
control
signal
CONTRAL
Q
is
unchanged,
making
that
the
addition
gate
opens
a
r
igger
cycle
and
a
pulse
is
added
to
”G,
thereb
y
adding
a
pulse
to
the
bit
synchronization
signal
I
bef
ore
the
frequency
dividing,
and
making
that
the
phase
of
CLK
is
leading
b
y
a
per
iod
of
H.
Figure
10.
Sim
ulation
diag
r
am
when
CLK
lags
behind
B
(3)
CLK
synchroniz
ed
with
B
As
sho
wn
in
Figure
11,
the
lagging
pulse
SINNAL1
an
d
the
leading
pulse
SINGLA2
achie
v
e
dynamic
equilibr
ium
at
the
second
half
of
the
sim
ulation
diag
r
am.
As
the
edge
detec-
tion
pulse
B
has
a
fix
ed
time
width,
when
compared
to
the
bit
synchronization
cloc
k
signal
CLK,
CLK’
s
jumping
edge
of
lies
in
the
middle
of
B”,
theref
ore
the
leading
pulse
and
the
lagging
pulse
are
obser
v
ed
alter
nativ
ely
.
Deducting
a
pulse
bef
ore
the
leading
pulse
is
coming
,
adding
a
pulse
bef
ore
the
lagging
pulse
is
coming,
the
whole
system
is
in
a
dynamic
equilibr
ium
status
.
This
is
the
required
bit
synchronization
status
in
this
design.
Figure
11.
Sim
ulation
diag
r
am
when
CLK
synchroniz
ed
with
B
T
r
ansmission
System
P
erf
or
mance
T
ester
(Huimin
Duan)
Evaluation Warning : The document was created with Spire.PDF for Python.
32
ISSN:
1693-6930
(4)
CLK
and
B
ha
v
e
re
v
ersed
phase
When
the
descending
edge
of
CLK
is
aligned
to
the
r
ising
edge
of
”B,
the
input
bit
signal
and
the
local
synchronization
cloc
k
ha
v
e
the
re
v
ersed
phase
.
At
this
time
,
the
leading
pulse
D
and
the
lagging
pulse
E
are
obser
v
ed
alter
nativ
ely
,
making
a
f
alse
synchronization,
the
control
module
first
deduct
a
pulse
then
add
a
pulse
,
making
phase
of
CLK
unchanged
and
not
adju
stab
le
.
T
o
fix
this
,
the
control
signal
CONTRAL
Q
is
used
here
to
a
v
oid
this
situation,
it
functions
as:
tur
n
off
the
addition
gate
if
there
is
a
”D,
so
the
control
module
is
not
ab
le
to
gener
ate
addition
pulse
and
the
phase
is
ab
le
to
be
adjusted,
theref
ore
to
solv
e
the
re
v
ersed
phase
prob
lem
of
CLK
and
B.
3.3.
Filter
The
channel
of
baseband
t
r
ansmission
system
is
equiv
alent
to
a
LPF
.
In
this
design,
w
e
used
f
our-order
Butterw
or
th
LPF
mode
to
design
three
filters
with
the
upper
cut-off
frequencies
of
100KHz,
200KHz,
500KHz,
respectiv
ely[13],
[14].
According
to
f
or
m
ula
(2)
and
(3),the
circuit
diag
r
am
of
a
lo
w-pass
filter
with
cut-off
frequency
of
100KHz
is
sho
wn
in
Figure
12.
A
(
j
!
)
=
A
0
p
1
+
(
!
=!
c
)
2
n
(2)
!
c
=
1
R
C
(3)
Figure
12.
Scheme
diag
r
am
of
a
lo
w-pass
filter
with
cut-off
frequency
of
100KHz
The
filters
with
cut-off
frequ
ency
of
200KHz
and
500KHz
are
designed
similar
ly
as
Figure
15,
b
ut
only
ha
v
e
diff
erence
in
components
par
ameters
.
3.4.
Ad
dition
module
A
direct
coupled
amplifier
is
used
in
the
addition
circuit[15].
As
the
frequency
of
noise
signal
is
10MHz,
so
w
e
used
the
THS3091
chip
which
has
a
gain-bandwidth
product
of
100MHz
.The
circuit
as
sho
wn
in
Figure
13.
3.5.
Atten
uator
A
-type
atten
uator
netw
or
k
is
used
in
this
section.
Adjustab
le
resistance
is
used
to
change
the
input
impedance
to
adjust
the
atten
uation
f
actor
.Atten
uator
circuit
as
sho
wn
in
Figure
14.
4.
Result
and
Anal
ysis
The
receiv
ed
baseband
signal
is
sent
to
Channel
X
of
the
oscilloscope
,the
bit
synchronous
cloc
k
is
sent
to
Channel
Y
.
Let
the
oscilloscope
w
or
ks
in
Channel
Y
tr
igger
,
then
an
e
y
e
diag
r
am
will
appear
on
the
screen
of
the
oscilloscope[16].
Obser
v
ation
and
analysis
of
the
e
y
e
diag
r
ams
are
as
f
ollo
ws
.
TELK
OMNIKA
V
ol.
15,
No
.
1,
March
2017
:
28
35
Evaluation Warning : The document was created with Spire.PDF for Python.
TELK
OMNIKA
ISSN:
1693-6930
33
Figure
13.
Circuit
diag
r
am
of
addition
module
Figure
14.
Circuit
diag
r
am
of
atten
uator
4.1.
Same
transmission
system
and
diff
erent
signal
sour
ce
T
esting
condition
:
As
sho
wn
in
T
ab
le
1;T
esting
results
:
As
sho
wn
in
T
ab
le
2.
T
ab
le
1.
T
esting
condition
of
same
tr
ansmission
system
and
diff
erent
signal
source
Name
condition
The
signal
source
f1=100Kbps
,
Vp-p=3.44V
Noise
signal
f2=10Mbps
,
Vp-p=100mv
LPF
cut-off
frequency
F
o=100KHz
T
ab
le
2.
Ey
e
diag
r
am
with
same
tr
ansmission
system
and
diff
erent
signal
source
Cut-off
frequency
Bef
ore
interf
erence
After
interf
erence
100KHz
According
to
the
w
a
v
ef
or
ms
sho
wn
in
T
ab
le
2,
when
the
noise
is
introduced,
the
e
y
e
dia-
g
r
am
becomes
b
lurred.
This
result
indicates
that
the
e
y
e
diag
r
am
accur
ately
reflects
the
prob
lem
dur
ing
the
signal
tr
ansmission.
4.2.
Diff
erent
transmission
system
and
same
signal
sour
ce
T
esting
condition
:
As
sho
wn
in
T
ab
le
3;
T
esting
results
:
As
sho
wn
in
T
ab
le
4.
T
ab
le
3.
T
esting
condition
of
diff
erent
tr
ansmission
system
and
same
signal
sourcel
Name
condition
The
signal
source
f1=100Kbps
,
Vp-p=3.44V
Noise
signal
f2=10Mbps
,
Vp-p=100mv
LPF
cut-off
frequency
F
o=100KHz/200KHz/500KHz
T
r
ansmission
System
P
erf
or
mance
T
ester
(Huimin
Duan)
Evaluation Warning : The document was created with Spire.PDF for Python.
34
ISSN:
1693-6930
T
ab
le
4.
Ey
e
diag
r
am
with
diff
erent
tr
ansmission
system
and
same
signal
sourcel
Cut-off
frequency
Signals
from
receiv
er
(including
noises)
Ey
e
diag
r
am
100KHz
200KHz
500KHz
By
compar
ing
each
e
y
e
diag
r
am,
it
can
be
seen
that:
the
e
y
e
diag
r
am
obtained
with
the
500KHz
LPF
has
the
widest
opening
and
the
largest
slope
of
its
h
ypoten
use;
the
e
y
e
diag
r
am
obtained
with
the
200KHz
LPF
has
the
median
opening
and
the
median
slope
o
f
its
h
ypoten
use;
while
the
e
y
e
diag
r
am
obtained
with
the
100KHz
LPF
has
the
smallest
opening
and
the
smallest
slope
of
its
h
ypoten
use
.
Theref
ore
when
the
optimal
sampling
time
is
selected
in
the
moment
that
the
e
y
e
diag
r
am
sho
w
a
largest
height
of
aper
tur
e
,
when
a
500KHz
tr
ansmission
system
is
used,
the
SNR
is
maxim
um
and
is
most
sensitiv
e
to
the
timing
error
;
while
when
a
100KHz
tr
ansmission
system
is
used,
the
SNR
is
minim
um
and
is
least
sensitiv
e
to
the
sampling
timing
error
.
Abo
v
e
test
results
sho
w
that,
the
e
y
e
diag
r
ams
obtained
through
the
designed
system,
not
only
can
tr
uthfully
reflect
the
noise
caused
interf
erence
to
the
signals
,
b
ut
also
can
accur
ately
reflect
the
perf
or
mance
diff
erence
of
diff
erent
tr
ansmission
systems[14].
Ov
er
all,
the
tr
ansmission
perf
or
mance
tester
can
reflect
the
perf
or
mance
of
the
tr
ansmission
system
objectiv
ely
.
5.
Conc
lusion
In
the
research,
the
digital
baseband
tr
ansmission
system
perf
or
mance
tester
mak
es
use
of
the
Cyclone
IV
FPGA
and
its
b
uilt-in
DPLL
to
gener
ate
and
analyz
e
the
signals
.
The
design
impro
v
es
the
tester
loc
k
speed,
the
stability
,
reliability
and
fle
xibility
,
f
acilitating
its
maintenance
and
upg
r
ades
.
The
tests
pro
v
e
that
the
e
y
e
diag
r
am
can
be
displa
y
ed
accur
ately
,
thereb
y
tr
uthfully
reflected
the
perf
or
mance
of
the
baseband
comm
unication
system.
In
addition,
through
the
e
y
e
diag
r
am,
w
e
can
easily
obtain
the
amplitude
distor
tion,
z
ero
distor
tion,
noise
toler
ance
,
time
sensitivity
and
other
perf
or
mance
indicators[1,14].The
y
can
not
only
contr
ib
ute
to
reco
v
er
y
of
the
baseband
signal,
b
ut
also
can
pro
vide
guidance
f
or
impro
v
e
the
tr
ansmission
perf
or
mance
of
the
comm
unication
system.
6.
Ac
kno
wledg
ement
This
project
w
as
suppor
ted
b
y
the
Natur
al
Science
Research
Project
of
Anhui
Pro
vin-
cial
Education
Depar
tment(KJ2015B1105908),Outstanding
Y
outh
F
oundation
of
Hef
ei
Univ
er-
sity(2016YQ09RC),K
e
y
Constr
uction
Discipline
of
Inf
or
mation
and
Comm
unication
engineer
ing
in
Hef
ei
Univ
ersit
y
(
No
.
2014xk06)
and
Natur
al
Science
F
oundation
of
Anhui
Pro
vincial
Education
Depar
tment(KJ2015A164).
TELK
OMNIKA
V
ol.
15,
No
.
1,
March
2017
:
28
35
Evaluation Warning : The document was created with Spire.PDF for Python.
TELK
OMNIKA
ISSN:
1693-6930
35
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