TELKOM
NIKA
, Vol.14, No
.2, June 20
16
, pp. 464~4
7
0
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v14i1.3675
464
Re
cei
v
ed
De
cem
ber 2
7
, 2015; Re
vi
sed
April 2, 2016;
Accept
ed Ap
ril 15, 2016
A Novel Multifunction Digital Chip Design Based on
CMOS Technology
Zi-Ang Z
hou
*
1
, Wen-Bo G
e
ng
2
1
Colle
ge of Me
chan
ical a
nd El
ectrical En
gin
e
e
rin
g
, Z
houko
u
Normal Un
iver
sit
y
,
466
00
1, Z
houk
ou, Hen
an, P. R. Chin
a
2
Colle
ge of Net
w
o
r
k Eng
i
ne
eri
ng, Z
houko
u
N
o
rmal Un
iversit
y
, 4
660
01, Z
houk
o
u
, Hena
n, P. R. China
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: zzang6
6@1
2
6
.com
1
, w
e
nbo
gen
g@1
63.co
m
2
A
b
st
r
a
ct
T
he rea
l
i
z
a
t
i
o
n
of an
ana
lo
g-to-di
g
ital-c
onve
r
sion c
h
ip
has
great si
gnific
a
n
c
e in th
e a
ppl
ic
ations
o
f
electro
n
ic pro
d
u
cts. By considerin
g
mat
u
re time
–n
u
m
ber d
i
giti
z
a
ti
on, a ne
w
multifunctio
n
digital ch
ip w
i
th a
lon
g
ti
me
de
lay
w
a
s des
ign
e
d
in th
is study
o
n
the
basis
of th
e pri
n
ci
ple
of
a
nal
og-to-ti
m
e
c
onvers
i
on
(AT
C
)
and th
e re
ali
z
a
t
ion of l
ong ti
me
de
lay. W
i
th ad
ditio
n
a
l
re
sistance, ca
pa
citance, a
nd tr
ansistors, this
chi
p
can
easi
l
y re
ali
z
e
AT
C,
mo
no
stable
trigg
e
rs, Sch
m
itt trig
ger
s, and
multiv
ibr
a
tors. T
he c
i
rc
uit co
mpositi
o
n
of
this
chi
p
w
a
s
ana
ly
z
e
d, and every mo
dul
e desi
gn
w
a
s
i
n
troduc
ed. Acco
rdin
g to the s
i
mu
lati
on res
u
lt
of
Hspice
and
CS
MC 2P2M CM
OS (Comple
m
entary Metal
O
x
ide Se
micon
d
u
ctor) process
datab
ase, the
chip
layout (1mm
2
) desi
gn w
a
s ac
complis
he
d by
usin
g CSMC
2P2M CMOS t
e
chn
o
lo
gy. F
i
n
a
lly, the
desi
g
ne
d
chip w
a
s
ap
pli
ed
in
multipr
o
j
e
ct w
a
fer flow
. T
he flow
test d
e
monstrate
d
th
at this
new
chi
p
ca
n
me
et d
e
s
i
g
n
goa
l an
d is app
licab
le to vari
o
u
s dig
i
tal int
egr
ated chi
p
des
ig
ns as an IP (intellect
ual pr
op
e
r
ty) core.
Ke
y
w
ords
:
C
M
OS technolo
g
y, multif
unctio
n
dig
i
tal chi
p
, layout des
ig
n, MPW
Copy
right
©
2016 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
The 5
55 tim
e
r i
s
a
chip
with a m
ono
stable t
r
igge
r, Schmitt trig
ger, a
nd mul
t
ivibrator.
Given its flexible and
conv
enient op
erati
on, the 555 ti
mer is
wid
e
ly used i
n
man
y
fields, su
ch
as
waveform ge
neratio
n a
nd
transfo
rmatio
n, mea
s
u
r
em
ent and
control, hou
seh
o
ld
applia
nces,
an
d
electroni
c toys. At present, the 555 time
r chi
p
s av
aila
ble in the ma
rket a
r
e bip
o
l
a
r an
d CMO
S
(Co
m
plem
ent
ary Metal Ox
ide Semi
con
ducto
r) type
s. Both types of 555 time
r chips apply
a
digital–an
alo
g
hybri
d
inte
g
r
ated
ci
rcuit, whi
c
h i
s
exp
e
n
sive. A
che
a
p
digital
chi
p
that ca
n reali
z
e
a long time d
e
lay is un
avai
lable in the m
a
rke
t. This
study use
d
CS
MC 2P2M
CMOS tech
nol
ogy
and d
e
si
gne
d a multifun
ction di
gital
chip th
at
ca
n re
alize
an
alog-to
-time
conve
r
si
on
(ATC),
mono
stable
trigge
r, Schmi
tt trigger,
an
d multivibra
to
r
with ad
ditio
nal resi
stan
ce, ca
pa
citan
c
e,
and tran
si
stors.
2. State o
f
th
e Art
Analog
-to-di
g
i
tal conve
r
si
o
n
(ADC) i
s
a
co
mmo
n int
e
rface chip i
n
elect
r
oni
c
prod
uct
s
.
Existing com
m
ercial ADC design
s
all
involv
e analog–di
gital-mi
xed chip
s. Analog devi
c
es,
inclu
d
ing ope
rational ampl
ifiers, comp
a
r
ators,
c
apa
citors, a
nd re
sisto
r
s,
are
use
d
in exi
s
ting
ADC de
sig
n
s. The accura
cy of refere
n
c
e volt
age i
s
important to
compa
r
ato
r
perform
an
ce
.
Therefore, calibratio
n
s are
difficult
to con
d
u
c
t du
ri
ng the m
a
ssi
v
e use
of co
mparators. ADC
developm
ent
unde
r
singl
e- an
d lo
w-power
con
s
u
m
ptions
sh
o
u
ld con
s
ide
r
not only ci
rcuit
stru
cture a
n
d
tech
nolo
g
ical probl
em
s but
al
so
diff
erent anal
og
de
sign
s, su
ch as
pe
riph
eral
circuit and
sign
al con
d
i
t
ioning.
T
h
e
r
efore,
rese
arch
on A
D
C ha
s
great si
gnifica
nce.
Corre
s
p
ondin
g
re
sea
r
ch h
a
s b
een
co
n
ducte
d successively in
Chin
a an
d foreig
n count
ries.
Ho
wev
e
r,
t
h
e
dire
ct
de
sig
n
s of
A
DC
re
main r
e
st
ricte
d
by digital–
a
nalog
hybrid
s. In Referen
c
e
[1], a hard
w
a
r
e de
scri
ption
langu
age
(HDL)
wa
s u
s
e
d
to de
scribe
digital–a
nalo
g
hybrid
ci
rcu
i
ts
and
reali
z
e
a
n
ADC d
e
sig
n
. Ho
weve
r, the natu
r
e
of
the digital
–an
alog hyb
r
id t
e
ch
nolo
g
y of
the
chip remai
n
s unchan
ged, and
the HDL for
anal
og
ci
rcuit still ha
s
no unifo
rm st
anda
rd a
nd h
a
s
not entere
d
the com
m
erci
al stage. The
design
ed A
DC in Refere
nce [2] empl
oyed the ran
dom
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
A Novel M
u
ltifunction
Digit
a
l Chip
De
sig
n
Based o
n
CMOS Technol
ogy (Zi-An
g Z
hou)
465
numbe
r an
d smoothi
ng m
e
thod, whi
c
h
involve simpl
e
circuits
and
has a lon
g
conversion tim
e
.
An an
alog
filter
com
p
o
s
ed
of
RC was u
s
ed
in
th
e de
sign. The
chi
p
an
d RC
filter perfo
rma
n
c
e
s
were clo
s
ely
related [2]. The ADC for 0.8
μ
m CMOS technol
o
g
y was deve
l
oped in fore
ign
cou
n
trie
s by t
he movin
g
av
erag
e filter te
chni
que. In th
is de
sig
n
, the
conve
r
ting
si
gnal
wa
s u
s
e
d
dire
ctly a
s
th
e supply
voltage
of
CMO
S
delay
gate
and
co
ndu
cts mea
s
u
r
em
e
n
ts by
utilizi
n
g the
linear rel
a
tion
ship
between
time delay
si
ze a
nd the
su
pply voltage
on the
CMOS
gate. Howev
e
r,
the appli
c
abl
e conve
r
ting
-voltage ran
g
e
for the de
si
gn is limited,
i.e., it is applicabl
e to a low-
voltage (1.8 V
to
2.0
V) CMOS sen
s
o
r
. No re
port
is
a
v
ailable yet
o
n
whethe
r
a li
near relation
ship
exists b
e
twe
en the d
e
lay
time of the
gate an
d the
sup
p
ly voltage beyo
nd th
is voltage
ra
nge.
Given that th
e digitization
of time-to-digi
tal c
onve
r
sio
n
is m
a
ture, an ADC
chip
can
be
de
sig
ned
indire
ctly by first co
nvertin
g
vo
ltage (cu
rre
nt) into the
ATC of the time sign
al an
d then digitizi
ng
this
ATC.
The rem
a
inder of this paper is organi
zed as
follows. Chapter III analyzes the pri
n
cipl
e of
ATC an
d discu
s
ses th
e theoretical im
plementati
o
n
of ATC. Ch
apter IV stu
d
ies th
e ci
rcuit
comp
ositio
n of
a
m
u
ltifun
ction digital chip
an
d
designs core,
l
e
vel-swit
chin
g, ele
c
tro
st
atic
discha
rge
(E
SD) p
r
ote
c
tive, and out
pu
t buffer ci
rcu
i
ts. Cha
p
ter
V pre
s
ent
s the pe
rform
a
nce
simulatio
n
of
a multifun
ctio
n digital
chip
unde
r diffe
re
nt tempe
r
atures
and
techn
o
logie
s
.
Cha
p
ter
VI provide
s
t
he layo
ut de
sign
of the
d
e
sig
ned
chi
p
and
the o
n
-wafer test
re
sult. Chapte
r
VII
concludes. Chapter VIII pr
ovides the acknowledgment.
3. Implementation of
ATC
The RC diffe
rential fun
c
ti
on ca
n con
s
titute con
s
tan
t
0 and 1 dif
f
erential mo
n
o
stabl
e
trigge
r circuit
s
. The differe
ntial mono
sta
b
le circuit
s
a
nd their
wave
form are sh
o
w
n in Fig
u
re
1. In
the co
nsta
nt 1 differential
mono
stabl
e trigger
circuit, the output volt
age V
OL
be
co
mes hi
gh
wh
en
the input end
Vf has a ne
gative trigge
ri
ng pul
se.
At the sam
e
time, VC becom
es hig
h
by the
cou
p
ling
effect of supply v
o
ltage
C. By contras
t, the
output V0
be
come
s l
o
w b
e
ca
use V0 i
s
the
feedba
ck to the input en
d.
V
OL
can still
maintain a
hi
gh level for
a sho
r
t time ev
en if the neg
a
t
ive triggeri
n
g
pulse of
V
f
disapp
ears, thus re
sultin
g in
the tran
sient steady st
ate of circ
uit. Ho
wever, the
VC in the RC
circuit de
crea
se
s with the
cha
r
gin
g
of supply voltage
C. When V
C
= V
TH
(V
TH
:thresh
old voltag
e),
Vo returns to
a high level, and the ci
rcui
t return
s
to a steady state.
In the con
s
ta
nt 0 differenti
a
l
mono
stable trigger
circuit, the low level
of V
OL
can be maintained f
o
r so
me time
beca
u
se of the
feedba
ck effe
ct of Vo.
With
the
ch
a
r
gin
g
of C, VC in
creases to V
TH
gradually, Vo
returns to a low
level, and the
circuit retu
rn
s to the stead
y state.
(a) Con
s
tant 1
differential mono
stable circuit
(b) Con
s
tant 0
differential mono
stable circuit
(c
) Wav
e
fo
rm
of Figure 1
(
a
)
(d)
Wav
e
fo
rm
of Figure 1
(
b
)
Figure 1. Differential m
ono
stable
circuits and their wa
veforms
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 464 – 47
0
466
Accordin
g
to
the
abov
e
analy
s
is
o
n
diffe
rential mono
stable circuit
s
,
these circuits have no
spe
c
ific
req
u
i
r
eme
n
ts o
n
input-tri
gge
rin
g
pul
se
an
d
are a
ppli
c
a
b
le to this n
e
w multifun
ct
ion
digital chip.
The con
s
tant
1 differential
circui
t can b
e
used to m
easure th
e u
n
kn
own volta
ge
within the
ra
n
ge of 0 to VT
H, wh
erea
s the con
s
tant 0
differential
ci
rcuit
ca
n be
u
s
ed to
mea
s
u
r
e
the unkno
wn
voltage within
the range of
TH
V
to
D
D
V
.
In Figure 1, the output p
u
l
s
e
width
W
T
of the consta
nt 1 differential
mono
stable t
r
igge
r
circuit is only
determin
ed
by the time for
VC on
R to decrea
s
e from the tran
si
tion to
TH
V
durin
g
the cha
r
gin
g
process of
C
in the
R
C
circuit. The dela
y
time of
the con
s
tant 0
differential
mono
stable
trigge
r
circuit
i
s
d
e
termi
ned
by the
charg
i
ng time
of
C
until
VC
in
cr
ea
se
s t
o
TH
V
. It
can b
e
used
to calcul
ate
the
W
T
approx
imately, and
W
T
can be
cal
c
ulate
d
by the followi
ng
equatio
n:
C(
)
C
(
0
)
w
C(
)
T
H
VV
TR
C
VV
(1)
Whe
r
e
(0
)
C
V
is the
initial value
of cap
a
cito
r v
o
ltage,
()
C
V
is the
end valu
e of
the ca
pa
citor
voltage, and
TH
V
is the thresho
l
d voltage of t
he po
st-g
ate
circuit. Fo
r a
spe
c
ific
circui
t,
TH
V
is fixed.
Whe
n
R
C
is determin
ed, a co
rre
sp
ondi
ng relation
ship ex
ists b
e
twe
en
W
T
and
()
C
V
(Equati
on (2
)).
This relation
ship is the ba
si
c refe
ren
c
e of
ATC implem
entation:
()
Tf
V
(2)
A numeri
c
al
conve
r
si
on
circuit is th
e
n
used to
convert it into the corre
s
pondi
ng
nume
r
ical value of
()
C
V
, thus accompli
shin
g the numeri
c
al
conversio
n
from digital co
unt N to
()
C
V
(Equatio
n (3
)).
()
()
C
VF
N
(3)
4. Multifunction Digital Chip Design
The multifun
ction di
gital chip ba
se
d on
CMOS
te
ch
nology i
s
sho
w
n in Fi
gu
re
2. This
chip m
a
inly includes
a core circuit, level
swit
chin
g ci
rcuit, output buf
fer ci
rcuit, an
d ESD(Ele
ctro-
Static Discha
rge
)
prote
c
tive circuit.
Figure 2. Multifunction di
gital chip
4.1. Core Cir
c
uit
The core
circuit is the mai
n
com
pone
nt of
the integrated ci
rcuit a
nd is respon
sible for
the main
fun
c
tions
of the
ci
rcuit. T
he
co
re ci
rcuit
can
accompli
sh
A
T
C th
rou
gh t
he exte
rnal
p
o
rt
of the integrated ci
rcuit toget
he
r with
R and
C. The core
circuit ca
n al
so easily real
ize
mono
stable triggers, multivibrato
rs, an
d
Schmitt trig
g
e
rs [1]. An ESD prote
c
ti
ve
circuit is mai
n
ly
use
d
to avoi
d the CM
OS-integrate
d
ci
rcuit dam
age
s and lat
c
h-up
cau
s
e
d
by
ESD. The le
vel-
swit
chin
g
circuit is m
a
inly
use
d
to m
a
ke
the d
e
sig
ned
chi
p
comp
atible
with tra
n
sistor–t
ran
s
i
s
tor
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
A Novel M
u
ltifunction
Digit
a
l Chip
De
sig
n
Based o
n
CMOS Technol
ogy (Zi-An
g Z
hou)
467
logic (TT
L
).
T
he output buffer
circuit i
s
m
a
inly used
to i
n
crease the drive c
apability of the
chi
p
by
increa
sing th
e output inverter chai
n.
4.2. Lev
e
l-s
w
i
t
ching
Circuit Compo
s
ed of an Imp
r
ov
ed In
v
e
rted Bu
ffe
r
Chip
com
pati
b
ility is a key probl
em that
has
to
be
consi
dered in
the design. A
CMOS
techni
cal
tap
e
-out
wa
s
e
m
ployed i
n
t
h
is
de
sign.
I
n
practi
cal
a
pplication
s
, the fro
n
t en
d
of the
chip may be
a TTL chip
with the followin
g
logic
level durin
g operation
s
:
0.4
VOL
V
and
2.
4
VO
H
V
. Con
s
id
erin
g
the influe
nce
s
of
a servi
c
e
enviro
n
ment,
wh
en the
su
pply voltage i
s
5
V, the gen
eral limits
of the outp
u
t-lev
e
l
ra
nge of
the
fro
n
t-en
d TTL chip are
ma
x
0.8
VO
L
V
and
m
2.
0
im
VOH
V
. The
s
e limit
s a
r
e
acce
ssed to th
e inp
u
t end
of
CMOS chip
directly; the
NM
OS(N-
Metal-Oxid
e-Semico
ndu
ct
or) and
PM
O
S
(
positive
chann
el Metal
Oxide Semi
con
d
u
c
tor) tu
bes
will be respectively broken down at
ma
x
VOL
and
m
im
VOH
, thus resulting in
circuit brea
kdo
w
n.
Therefore,
a l
e
vel-switchin
g ci
rcuit at th
e input
end
is nee
ded to
convert the
chi
p
input l
e
vel i
n
to
the level
ran
ge for CMO
S
chip
s to
work no
rma
lly.
However, existing le
v
e
l
-
swit
chin
g cir
c
uit
s
comp
osed of
inverted b
u
ffers
ha
s wi
dth-t
o
-len
gth ra
tio
s
of 11:1
for
NMOS a
nd P
M
OS tube
s; this
ratio den
otes powe
r
and
area
con
s
um
ption. The
level-switchi
ng
circuit com
p
o
s
ed of a CM
OS
Schmitt trigg
e
r is al
so
disadvantag
eou
s for the
la
rg
e tube con
s
u
m
ption an
d wide chi
p
area
[2]–
[5]. The level-switchi
ng
circuit u
s
ed in
the cu
rrent chip is
sho
w
n
in Figure 3.
M1 is a di
o
d
e
comp
osed
of PMOS tube
s and i
s
add
e
d
to the PM
OS
so
urce
el
ectro
de
of th
e first
-
sta
ge i
nput
inverter. O
w
i
ng to the effe
ct of the su
bstrate
bia
s
of M1, the additi
onal PMOS t
ube in
crea
se
s the
absolute valu
e of the threshold voltage
and re
du
ce
s the effective supply voltage
on the inverter
.
Therefore,
a
dding M
1
de
cre
a
ses the
threshold l
o
g
i
c level of th
e first-stag
e
input level. T
he
NMOS a
nd P
M
OS tube
s, whi
c
h have
small ele
c
tric
con
d
u
c
tion, a
r
e optio
nal a
s
the inverte
r
of
the first
-
sta
g
e
input l
e
vel. Howeve
r, an
other PM
OS
fe
edba
ck tub
e
(M4) i
s
add
ed
to the
circuit t
o
maintain th
e
high-l
e
vel pe
rforman
c
e
of the first-st
a
g
e
inverter after M1 is
used.
The
simulatio
n
test result indicate
s that the level-switch
ing ci
rcuit of the pro
p
o
s
ed
chip de
sig
n
can conve
r
t the
front-e
nd TT
L level into t
he op
eratin
g
level of the
i
nput en
d of t
h
is
chip
effectively. The circuit
use
d
occu
pie
s
a sm
all are
a
durin
g tape
-out.
Figure 3. Level-switching
circuit
Fi
gure 4. ESD prote
c
tive circuit
4.3. ESD Protec
tiv
e
Circuit
ESD ha
s to b
e
co
nsi
dered
in MOS integ
r
ated
chip
de
sign. ESD
da
mage
will cau
s
e g
a
te
breakdown inside
the
CMOS device and
latch-up i
n
si
de the
chip. T
h
e device and
circuit
will al
so
be dama
ged
upon the lo
cal chip hea
ting cau
s
e
d
by the ESD-indu
ced in
stantane
ou
s hig
h
curre
n
t. Particula
r
ly, the input and outp
u
t ends a
r
e
vulnerable to
ESD [6]–[10]. On the basi
s
of
a
comp
re
hen
si
ve con
s
id
erat
ion on
existin
g
pair diod
e
ESD protecti
ve circuit, thi
s
de
sig
n
u
s
e
s
a
pair
of PMOS
and
NM
OS tube
s to fo
rm
the input ES
D p
r
ote
c
tive
circuit. Th
e NMOS tube
ga
te is
con
n
e
c
ted to
the
gro
und,
whe
r
ea
s the
PMOS tube
gate i
s
co
nn
ected
to V
D
D. Given
that
the
MOS tube for desig
ning E
S
D prote
c
tive
circuit is
sig
n
i
ficantly large,
a pectination
MOS transi
s
tor
is used for th
e layout desi
gn. The diod
e prote
c
ti
on
of PN stru
ctu
r
e in the lea
k
i
ng so
urce re
gion
of the large M
O
S tube ca
n also b
e
used
well. The
ESD prote
c
tive circuit is
sho
w
n in Figure 4.
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ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 464 – 47
0
468
4.4. Outpu
t
Buffer
Circui
t Compo
sed
of a Fix-tape
red Bu
ffer Chain
Duri
ng
chip
desi
gn, attention should be fo
cused on the output dr
ive capabilit
y of the
chip. The
op
erating
spe
e
d
of the circu
i
t can
only b
e
guarantee
d
when the d
r
i
v
e current at
th
e
output level i
s
la
rge
en
ou
gh. The
d
r
ive current i
s
often in
cre
a
sed by in
crea
sing
the
widt
h-to-
length ratio of
the MOS (Metal Oxide Semicon
d
u
c
to
r) tube. Ho
weve
r, the priori lo
ad ca
pa
citan
c
e
and p
r
iori
del
ay time will in
cre
a
se when
the MOS tub
e
expand
s. A
s
a result, un
der the
pre
m
i
s
e
of a mini
mu
m total del
ay time of the
b
u
ffer,
an
outp
u
t buffer th
at
can
provide
approp
riate d
r
ive
curre
n
t is im
portant to
ch
ip de
sign. In
CMOS
chi
p
desi
gn, a
n
i
n
verter
ch
ain
com
p
o
s
ed
o
f
a
multilevel inv
e
rter is com
m
only u
s
ed
as th
e o
u
tpu
t
buffer [11
-
1
5
]. In this
ch
ip de
sign,
a
fix-
tapere
d
buffe
r ch
ain
comp
ose
d
of a three-level i
n
verter with a
progre
s
sive in
crea
se of 1.6
is
used as the
output buffer
to incr
ease the drive
capab
ility of the circuit. The
out
put buffer
circuit
of the chip is
sho
w
n in Fig
u
re 5.
Figure 5. Output buffer ci
rcuit
5. Performan
ce Simulation of the Mul
t
ifunction
Chi
p
A simul
a
tion t
e
st o
n
the
pe
rforma
nces of
t
he d
e
si
gne
d
multifunctio
n
chi
p
u
nde
r di
fferent
con
d
ition
s
was con
d
u
c
te
d
usi
ng
th
e Hspice
software and
th
e CSMC 2P2M
0.6
µm CM
OS
p
r
oc
es
s
da
tab
a
s
e
(
0
6mixdd
c
t
0
2
v
24
)
.
5.1. Simulation Test u
n
d
e
r Differen
t
Process F
e
e
t
The simul
a
tio
n
results of the multifunctio
n
ch
ip un
der
different pro
c
ess co
rne
r
s (FF, FS,
SF, and SS) are p
r
e
s
ente
d
in Figure 6.
Figure 6. Simulation re
sult
s of the chip
unde
r
differe
nt process
co
rne
r
s (FF, FS, SF, and SS).
Figure 6 indi
cate
s that th
e chi
p
pe
rformanc
e
s
c
h
a
n
g
e
co
ns
id
er
ab
ly w
h
en
th
e p
r
oc
es
s
corne
r
va
ries within
the
a
c
ceptabl
e
ran
ge
(the m
a
ximum
cha
nge
in the
ri
se
time d
e
lay of t
h
e
c
i
rc
uit (from FF to SS) is
4.72 ns
,
an
d the fall time delay is 3.63 ns).
5.2. Simulation Test u
n
d
e
r Differen
t
Tempera
t
ure
s
The pe
rforma
nce
simul
a
tio
n
of the
chi
p
unde
r differe
nt temperatures (
−
2
5
, 0, 2
5
, 50, 80,
and 12
0 °C) is sh
own in Figure 7.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
A Novel M
u
ltifunction
Digit
a
l Chip
De
sig
n
Based o
n
CMOS Technol
ogy (Zi-An
g Z
hou)
469
In Figure 7, the chi
p
perfo
rmances u
nde
r different te
mperature
s
(
−
25, 0, 25, 5
0
, 80, and
120
°C)
cha
n
ge in
sig
n
ifica
n
tly. The ma
ximum ri
se
time del
ay an
d fall time
de
lay of the
ci
rcuit
were 0.836 a
nd 3.79 n
s
, within the acce
ptable ra
nge,
respe
c
tively.
Figure 7. Performa
nce sim
u
lation of t
he chip u
nde
r different tempe
r
ature
s
.
6. Chip La
y
o
ut De
sign an
d Test
Resul
t
Analy
s
is
The enti
r
e
system layout
wa
s de
sig
n
e
d
and ve
rifie
d
on the
Jiut
ian layout e
d
itor and
layout verification enviro
n
m
ent (ZeniP
D
T&Ze
niVERI).
The layout of the multifu
n
ction di
gital chip
and the phy
si
cal map of th
e encap
sulat
ed chi
p
are
shown in Figu
re 8.
(a) L
a
y
out
(b) Phy
s
ical
map
Figure 8. Chi
p
layout
Figures 9
(
a
)
and (b)
sho
w
the tape-out test
waveform
s und
er diffe
rent inputs. A
c
cording
to the test result, the propo
sed
chip
can
reali
z
e vari
ou
s logi
c functio
n
s.
(a) T
e
st w
a
v
e
form
(b) T
e
st w
a
v
e
form
Figure 9. Chi
p
test re
sults
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 2, June 20
16 : 464 – 47
0
470
7. Conclusio
n
This study prop
oses a
new
m
u
ltifunctio
n
digit
a
l chi
p
de
si
gn ba
se
d o
n
CMOS
techn
o
logy. T
he chi
p
layou
t
design
and
verifica
tion
are impleme
n
te
d on the ba
si
s of the CSM
C
2P2M COMS
techn
o
logy. The p
r
opo
se
d chi
p
cove
rs an a
r
e
a
of
1 mm
2
, has a simpl
e
ci
rcuit
config
uratio
n, and
i
s
e
a
sy
to be
inte
grat
ed.
With a
ddi
tional d
e
vice
s, the
chip
can
re
alize va
rio
u
s
function
s, incl
uding AT
C, mono
stabl
e triggers, multivibrato
rs, an
d Schmitt trigge
rs. The
chi
p
ca
n
also
chan
ge t
he tran
sient
state of
the circuit
by cha
n
g
ing
th
e cont
rol
l
e
vel con
n
ected
to port 5
while reali
z
in
g a mono
stab
le trigge
r, thus ena
bling
a
delay time five times hig
h
e
r
than that of the
traditional
55
5 timer.
The
on-wafe
r a
n
d
en
cap
s
ul
ate
d
test
re
sult
s after ta
pe
-o
ut sh
ow that
the
chip
re
alizes pre
s
et
fun
c
tions an
d i
s
widely
used
in vario
u
s p
opula
r
inte
grated
circuit
chip
des
igns
as
an IP c
o
re.
Ackn
o
w
l
e
dg
ements
This
study was supp
orted
by the Hena
n Sc
ien
c
e a
n
d
Technolo
g
y Resea
r
ch Project in
2014 (No. 14
2102
1101
76
).
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ces
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ong
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han
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