TELK OMNIKA , V ol. 13, No . 1, March 2015, pp . 364 372 ISSN: 1693-6930, accredited A b y DIKTI, Decree No: 58/DIKTI/K ep/2013 DOI: 10.12928/telk omnika.v13.i1.1122 364 Over vie w of Custom Micr ocontr oller using Xilinx Zynq XC7Z020 FPGA Ba yu Kanigor o* , Ric ky Efr aim Lie , and M. Fitra Kacamar ga Computer Science Prog r am, School of Computer Science , Bina Nusantar a Univ ersity J akar ta, 11480, Indonesia *Corresponding author , e-mail: bkanigoro@bin us .edu Abstract This paper presents an o v er vie w of customizab le microcontroller using a Xilinx Zynq XC7Z020 FPGA as an alter nativ e to increase its perf or mance as user need. This alter nativ e ar ises due to man y of the systems , which de v eloped mostly b y using microcontroller are not g iving an y room f or customization to increase its perf or mance or I/O por ts . There is an y possibility that the system designed to be used b y using gener al processor such as PC to increase its perf or mance b ut it will giv e another prob lem such as interf ace difficulty f or high speed I/O , real time processing, increases comple xity , and man y more . Customization is introduced b y combining hard IP processor and FPGA in one chip instead of pr acticing tw o separ ate de vices , processor and FPGA, which is commonly use in high perf or mance embedded design. This approach allo ws seamless design de v elopment and de v elopment time reduction f or customization. K e yw or ds: FPGA, microcontroller , embedded system, system-on-chip , customization 1. Intr oduction The adv ancement of semiconductor technology has been reaching in nanometer scale which sho wn b y Intel that h as achie v ed 22nm process technology in 2011 f or their processor products line [1]. This adv ancement has been giving an oppor tunity to put man y functions on a chip beside main function such as a processor and their per ipher als can be placed on a single chip . This de v elopment is r ising some technics and methodologies f or designing a silicon chip into a full functionality integ r ated circuit. One of the methods is Full Custom Design. In this method, an engineer designs some or all of the logic cells , circuits , or la y out specifically f or one design [2]. The other de v elopment of this adv ancement is possibility of customizing logic circuit on semiconductor without f ollo wing e xpensiv e semiconductor f abr ication processing technology due to all pr imitiv e gates ha v e been implemented on it then users or de v elopers only need to route interconnection betw een gates to create digital circuit and system. This technology is kno wn as Field Prog r ammab le Gate Arr a y or FPGA. Giving that ability of FPGA technology creates a concept of soft processor . Soft proces- sor is a processor , implemented in FPGA, which can be customiz ed to meet application needs [3]. Xilinx and Alter a ha v e been de v eloping Micro Blaz e and NIOS II respectfully f or their soft processor . MicroBlaz e [4] is RISC Pipelined Big-Endian 32-bit processor de v eloped b y Xilinx in 2002. It has 32 32-bit gen er al pur pose registers and special regi s t ers such as Prog r am Counter register . Microb laz e has three and fiv e pipeline stages which can be configured in de v elopment stage depending on area optimization which requires bigger area when using fiv e stages pipeline . The limitations of soft processor compared to hard processor , which is implemented per- manently on the chip , are on area siz e , perf or mance , and po w er consumpt ion b ut soft processor has adv antage b y customization such as fle xibility and special instr uction f or special application [3]. Soft processor has been used f or man y application. F or e xample , w or m robot [5], automotiv e application [6], increasing chiper ing algor it hm perf or mance [7], increasing application e x ecution b y mo ving par t of the application usually e x ecute d b y microprocessor into FPGA [8], increas- ing floating point perf or mance in soft processor [ 9], FPGA based Prog r ammab le Logic Controller (PLC) [10, 11], and man y more . Recently in la te 2011, Xilin x de v eloped Zynq R –7000 All P rog r ammab le SoCs [13]. This is the ans w er from Xilinx to include tw o application g r ade ARM R processors and FPGA on single Receiv ed No v ember 21, 2014; Re vised J an uar y 9, 2015; Accepted J an uar y 30, 2015 Evaluation Warning : The document was created with Spire.PDF for Python.
TELK OMNIKA ISSN: 1693-6930 365 chip thus increasing computing perf or mance than soft processor and, from designer perspectiv e , maximizing precious FPGA resources only f or custom design. The dr a wbac k of this approach is the architecture of the processor is per manently etched on chip hence giving no possibilities to customiz e its architecture as opposite of soft processor approach. This method will be called as System-on-Chip (SoC) approach in this paper as per definition all aspects of a digital system: processing, high-speed logic , interf acing, memor y , and so on can be combined on same chip [14]. The pur pose of this paper is giving a demonstr ation to de v elop custom microcontroller b y using System-on-Chip (SoC) approach. As it is kno wn that the architecture of a microcontroller in the mar k et such as PIC Microchip [15, 16, 17], Inte l MCS–51 [18, 19], and Atmel A VR Microcon- troller [20, 21, 22] are per manently etched on a silicon. Consequently closing an y possibilities to alter or enhance their str ucture . Those microcontrollers ha v e an adv antage in pr ice point of vie w due to v er y lo w pr ice which is around 36 cent US dollars and satisfy f or less comple x requirement [23]. When the requirements and need of fle xibility of the systems are r aising, such as video processing [24, 25], then those microcontrollers , due to their limitations , are not capab le to tac kle the demands [26]. 2. The Ar c hitecture In gener al the architecture of System-on-Chip or SoC is combination of Processing Sys- tem, in this case ARM based processor , and prog r ammab le logic depicted in figure 1. The pro- cessing system has some interf aces to inter act with outside en vironment which are Processing System I/O and DDR Memor y Controller . Processing System I/O consists on se v er al common interf aces t hat usually appears on small computer such as laptop or tab let PC . On Zynq plat- f or m, it has tw o USB por ts , tw o Ether net controller , SD controller , Gener al Pur pose I/O , and ser ial interf ace . Its DDR memor y controller suppor ts DDR3, DDR3L, DDR2, and LPDDR2 on Zynq platf or m hence Processing System can directly comm unicate to memor y . There are interf aces to comm unicate betw een Processing System and Prog r ammab le Logic , which named Processor- Prog r ammab le Logic Interf aces sho w ed in figure 1. F or this , Xilinx uses AXI Interconnect f or the interf aces [27]. P roce s s i ng Sy s t e m P rogr a mmabl L ogi c P r oce s s i ng   S y s t e m   I / O D D R   M e m or y   C ont r ol l e r P r oce s s or     P r ogr a m m a bl e   Log i I n t e r f a ce s P r oc e s s or     P r ogr a m m a bl e   Log i I n t e r f a ce s Hi g h   S p eed   P r o g r a m m a b l L o g i c   I / O Figure 1. System-on-Chip architecture [14] Figure 2 sho ws the architecture of the demonstr ation system. It consist of f our main b loc ks and tw o suppor ting b loc ks . The main b loc ks are ARM Processing System with DDR Mem- or y Controller , Interconnection b loc k, Timer and Gener al Pur pose Input Output (GPIO). The sup- por ting b loc ks are Reset Control System and Cloc k Multiplier . ARM Processing System with DDR Memor y Controller is hard implemented on the chip consequently their logic are per manent. Theref ore , this b loc ks is placed and named as Processing System. The rest of b loc ks is placed on prog r ammab le logic. Betw een Processing System and Prog r ammab le Logic in figure 2 is a b loc k named In- terconnection Bloc k that connect them. The b loc k is used to f acilitate data tr ansf er and com- m unication betw een processor and the de vices attached to them. In this design, the b loc k uses Ov er vie w of Custom Microcontroller using Xilinx Zynq FPGA (Ba yu Kanigoro) Evaluation Warning : The document was created with Spire.PDF for Python.
366 ISSN: 1693-6930 A R M   P r o c e s s i n g   Sy s t e m In t e r c o n n e c t i o n   B l o c k Re s e t   C o n t r o l Sy s t e m Ti m e r GP I O DDR SDR A M DDR Me m o r y   C o n t r o l l e r Cl o c k  M u l t i p l i e r L E Ds DI P   S W I T C H s Ex te r n a l   P o r ts P r o c es s i n g   S y s t em   I / O S er i a l T er m i n a l T i m er   In t er r u p t Figure 2. System architecture of custom microcontroller master-sla v e approach f or them hence the processor becomes the master and the rest of de vices , timer and GPIO , become sla v e . The design emplo ys tw o de vices which are timer de vice with interr upt and Gener al Pur- pose Input Output (GPIO). Timer is intended to demonstr ate ho w processor in Processing System responds with int err upt request from timer de vice and GPIO becomes an interf ace from the sys- tem to e xter nal por t which is connected to LEDs and s witches . The other de vices are ser ial ter minal which is connected to Processing System I/O and DDR3 SDRAM which is connected to DDR Memor y Controller . This tw o de vices , Processing System I/O and DDR Memor y Controller , are not implemented in Prog r ammab le Logic which is in FPGA b ut instead is implemented directly on the chip . T w o suppor ting de vices in the design are cloc k m ultiplier and reset control system. Cloc k m ultiplier is required to supply processor and all the de vices including memor y with required cloc k signal from relativ ely lo w frequency input from cloc k gener ator . This usually can be implemented b y using Phase Loc k ed Loop [28]. The other role of cloc k m ultiplier is supplying cloc k f or DDR SDRAM that requires 90 lead from main cloc k. Reset control system is required to synchronise reset all de vices in the system from uncer t ainty states to initial state . Listing 1 sho ws por t map of top le v el design of the system in VHDL. b e g i n s y s t e m _ 1 _ i : s y s t e m _ 1 p o r t m a p ( L E D s _ 8 B i t s _ T R I _ I O = > L E D s _ 8 B i t s _ T R I _ I O , p r o c e s s i n g _ s y s t e m 7 _ 0 _ M I O = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ M I O , p r o c e s s i n g _ s y s t e m 7 _ 0 _ P S _ C L K = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ P S _ C L K , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C l k = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C l k , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C l k _ n = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C l k _ n , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C K E = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C K E , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C S _ n = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C S _ n , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ R A S _ n = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ R A S _ n , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C A S _ n = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ C A S _ n , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ W E B _ p i n = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ W E B _ p i n , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ B a n k A d d r = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ B a n k A d d r , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ A d d r = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ A d d r , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ O D T = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ O D T , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D R S T B = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D R S T B , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D Q = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D Q , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D M = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D M , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D Q S = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D Q S , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D Q S _ n = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ D Q S _ n , TELK OMNIKA V ol. 13, No . 1, March 2015 : 364 372 Evaluation Warning : The document was created with Spire.PDF for Python.
TELK OMNIKA ISSN: 1693-6930 367 p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ V R N = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ V R N , p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ V R P = > p r o c e s s i n g _ s y s t e m 7 _ 0 _ D D R _ V R P ) ; e n d a r c h i t e c t u r e S T R U C T U R E ; Listing 1. T op le v el por t map of the system 3. Software Model The softw are of this system is directly coded to the processor . This means , it does not need an y oper ating system f or r unnin g an application which is using the system. T o access the de vices or per ipher als , it uses memor y mapped I/O . Hence , the applicat ion can directly control it b y accessing the address f or the corresponding de vices and sending the necessar y v alues to it. This has some dr a wbac ks that only one process can be e x ecuted b y the processor at a time . By using memor y mapped I/O f or accessing the de vices then the address of the de vices is consecutiv e to memor y address which sho wn in figure 3. Giving an memor y mapped I/O of the system in figure 3 sho ws a division of main memor y and its corresponding de vices . Main memor y star ts from address 0x00000000 to 0x1FFFFFF which gets 512 MB . This is where application softw are will be stored and e x ecuted b y the system. Consequently , reset v ector of the processor m ust be addressed to lo w address of the main mem- or y which is 0x00000000. The other de vices , GPIO , is addressed at 0x41200000 to 0x4120FFFF which gets 64KB and Timer is addressed at 0x42800000 to 0x4280FFFF , which gets same as GPIO , 64KB . The memor y is divided b y tw o sections , PS-Section and PL-Section. PS-Sect ion is par t of Processing System then all de vices in the PS-Section is fix ed then it can not changed its str ucture . The other section is PL-Section which is par t of Prog r ammab le Logic. PS−SECTION    Main 0x00000000 0x41200000 0x4120FFFF 0x1FFFFFFF 0x42800000 0xE0001FFF 0x4280FFFF TIMER GPIO 0xE0001000 PS−UART PS−USB 0xE0002000 0xE0002FFF 0xE000A000 0xE000AFFF PS−GPIO 0xE000B000 0xE0100FFF 0xE000BFFF PS−ENET PS−SDIO 0xF8001000 0xE0100000 0xF8001FFF PS−TTC PL−SECTION Memory Figure 3. Memor y Map of the system. Accessing the GPIO can be fulfilled b y using function that directly instr uct it through mem- or y . F or e xample , to wr ite AXI GPIO made f or Xilinx, the instr uction [29, 30] is , XGpio _ DiscreteWrite( * gpioAddress, channel, state); and to read AXI GPIO is , XGpio _ DiscreteWrite( * gpioAddress, channel); These functions use tw o par ameters in common. First par ameter is gpioAddress which point to the address of GPIO de vice and second par ameter is channel of the GPIO . All of these functions are included in xgpio.h . Ov er vie w of Custom Microcontroller using Xilinx Zynq FPGA (Ba yu Kanigoro) Evaluation Warning : The document was created with Spire.PDF for Python.
368 ISSN: 1693-6930 The other de vice , Timer , is treated as same as GPIO which is directly configured b y using direct memor y instr uction. In this system, Timer is using interr upt to notice the processor that counting process in the Timer has been ended. When the interr upt is asser ted then prog r am counter in the processor mo v es to special region in memor y which named is interr upt or e xcep- tion region. The region will be filled with functions to respond what beha viour of the processor to e xpect. After the functions are finished e x ecuted then prog r am count er will mo v e to or iginal location where main prog r am is placed. Such e xample is from Xilinx, which uses AXI Timer [31] as implementation of this de vice . AXI timer uses f our functions to control it [30]. First function to control the de vice is , void XTmrCtr _ Start(XTmrCtr * InstancePtr, u8 TmrCtrNumber) This function is required to star t the specified timer counter of the de vice such that it star ts r unning. The timer counter is reset bef ore it is star ted and the reset v alue is loaded into the timer counter [30]. The par ameters of the function are InstancePtr which point to XTmrCtr instance to be w or k ed on and TmrCtrNumber is the timer counter in the system to be w or k ed on [30]. Second function to control it is , void XTmrCtr _ Stop(XTmrCtr * InstancePtr, Xuint8 TmrCtrNumber) This function is required to stop the Timer from counting. The par ameters of the function are InstancePtr which point to XTmrCtr instance and TmrCtrNumber is the timer counter in the system to be w or k ed on [30]. Third function is , void XTmrCtr _ Reset( XTmrCtr * InstancePtr, Xuint8 TmrCtrNumber) which required to reset the Timer . And the last required function is , void XTmrCtr _ SetResetValue( XTmrCtr * InstancePtr, Xuint8 TmrCtrNumber, Xuint32 ResetValue ) This function is to set the reset v alue f or the specified timer counter . The v alue is loaded into the timer counter when it is reset and also loaded when the timer counter is star ted. The par ameters of the function are InstancePtr which point to XTmrCtr instance , and TmrCtrNumber is the timer counter of the de vice to oper ate on, and ResetValue contains the v alue to be used to reset the timer counter [30]. The v alue can be achie v ed b y using this equation, t tmr = 1 f cl k i< 32 X i =0 ( n 2 i ) (1) When the Timer uses interr upt then se v er al functions is required to ser vice the request from it. Listing 2 depicts the functions to handle interr upt request from Timer de vice . v o i d T i m e r _ I n t e r r u p t H a n d l e r ( v o i d d a t a , u 8 T m r C t r N u m b e r ) { p r i n t ( " I n s i d e T i m e r I S R \ r \ n " ) ; X T m r C t r _ S t o p ( d a t a , T m r C t r N u m b e r ) ; X T m r C t r _ R e s e t ( d a t a , T m r C t r N u m b e r ) ; p r i n t ( " O u t s i d e T i m e r I S R \ r \ n " ) ; p r i n t ( " \ r \ n " ) ; I n t e r r u p t F l a g = 1 ; } i n t S e t U p I n t e r r u p t S y s t e m ( X S c u G i c X S c u G i c I n s t a n c e P o i n t e r ) { X i l _ E x c e p t i o n R e g i s t e r H a n d l e r ( X I L _ E X C E P T I O N _ I D _ I N T , TELK OMNIKA V ol. 13, No . 1, March 2015 : 364 372 Evaluation Warning : The document was created with Spire.PDF for Python.
TELK OMNIKA ISSN: 1693-6930 369 ( X i l _ E x c e p t i o n H a n d l e r ) X S c u G i c _ I n t e r r u p t H a n d l e r , X S c u G i c I n s t a n c e P o i n t e r ) ; X i l _ E x c e p t i o n E n a b l e ( ) ; r e t u r n X S T _ S U C C E S S ; } i n t S c u G i c I n t e r r u p t _ I n i t ( u 1 6 D e v i c e I d , X T m r C t r T i m e I n s t a n c e P t r ) { i n t s t a t u s ; G i c C o n f i g = X S c u G i c _ L o o k u p C o n f i g ( D e v i c e I d ) ; X S c u G i c _ C f g I n i t i a l i z e ( & I n t e r r u p t C o n t r o l l e r , G i c C o n f i g , G i c C o n f i g > C p u B a s e A d d r e s s ) ; S e t U p I n t e r r u p t y s t e m ( & I n t e r r u p t C o n t r o l l e r ) ; X S c u G i c _ C o n n e c t ( & I n t e r r u p t C o n t r o l l e r , X P A R _ F A B R I C _ A X I _ T I M E R _ 0 _ I N T E R R U P T _ I N T R , ( X i l _ E x c e p t i o n H a n d l e r ) X T m r C t r _ I n t e r r u p t H a n d l e r , ( v o i d ) T i m e I n s t a n c e P t r ) ; X S c u G i c _ E n a b l e ( & I n t e r r u p t C o n t r o l l e r , X P A R _ F A B R I C _ A X I _ T I M E R _ 0 _ I N T E R R U P T _ I N T R ) ; r e t u r n X S T _ S U C C E S S ; } i n t m a i n ( ) { . . . X T m r C t r _ S t a r t ( & T i m e r I n s t a n c e P t r , 0 ) ; p r i n t ( " W a i t T i m e r t o t r i g g e r I n t e r r u p t \ r \ n " ) ; w h i l e ( I n t e r r u p t F l a g ! = 1 ) ; I n t e r r u p t F l a g = 0 ; r e t u r n 0 ; } Listing 2. Interr upt Handler functions 4. Result and Discussion The system w as implemented at Xilinx Zynq-7000 All Prog r ammab le SoC XC7Z020- CLG484-1 on ZedBoard de v elopment board [32] and Xilinx ISE 14.7 EDK as design tool. The de v elopment board is sho wn in figure 4c. T ab le 1 presents the utilization of register resource in XC7Z020-CLG484-1 gets around 0.13%, Look up T ab les (LUT) which constitute logic resource of the FPGA get around 0.45%. Cloc k b uff er gets around 3.125%, and I/O gets around 41.81%. The maxim um frequency of this system is 216.973 MHz f or -1 speed g r ade . This resources represents the architecture sho wn in figure 2 which implemented on prog r ammab le logic. T ab le 1. Resource utilization of the system. Resources Utilization Registers 418 of 319200 LUT 728 of 159600 Cloc k Buff er 1 of 32 I/O 138 of 330 T o demonstr ate the system, the softw are w as de v eloped to sho w timer interr upt and GPIO capability . The action of the softw are w as responding interr upt request when the timer has been reaching z ero b y tur ning on or off LEDs (LD 0 LD 7 ), which connected to GPIO , as sho wn in figure 4c and sho wing some messages on ter minal through ser ial por t. The softw are used LD 0 to LD 3 Ov er vie w of Custom Microcontroller using Xilinx Zynq FPGA (Ba yu Kanigoro) Evaluation Warning : The document was created with Spire.PDF for Python.
370 ISSN: 1693-6930 (a) (b) (c) Figure 4. ZedBoard de v elopment board of the implemented system (figure 4c) and LEDs appear ance of interr upt e x ecution (figure 4a) and (figure 4b). to sho w that the request has been e x ecuted which w ere initially 0x04 , which LD 2 w as tur ned on and the others w e re tur ned off (figure 4b) and 0x0A , which LD 3 and LD 1 w ere tur ned on and the rest w ere tur ned off sho wing that it has been e x ecuted successfully (figure 4a). The C statement that wr ites the GPIO into the v alue is , XGpio _ DiscreteWrite(&gpio,LED _ CHANNEL, 0x04); f or initial status and this statement, XGpio _ DiscreteWrite(&gpio,LED _ CHANNEL, 0x0A); is e x ecuted when the request has been e x ecuted. The GPIO w as initializ ed b y using f ollo wing statements sho wn in listing 3, # d e f i n e G P I O _ L E D _ D E V I C E _ I D X P A R _ L E D S _ 8 B I T S _ D E V I C E _ I D # d e f i n e L E D _ C H A N N E L 1 X G p i o g p i o ; . . . i n t m a i n ( ) { . . . x S t a t u s = X G p i o _ I n i t i a l i z e ( & g p i o , G P I O _ L E D _ D E V I C E _ I D ) ; i f ( x S t a t u s ! = X S T _ S U C C E S S ) { p r i n t ( " G P I O I n i t F a i l e d \ n " ) ; r e t u r n 1 ; } . . . } Listing 3. GPIO initialization which XPAR _ LEDS _ 8BITS _ DEVICE _ ID points to GPIO ID which has address of 0x41200000 . As discussed bef ore that changing LD’ s v alues from 0x04 to 0x0A w ere based on inter- r upt request, which e x ecuted when the timer reaches z ero . This w as achie v ed b y implement- ing interr upt handler from listing 2. Listing 2 sho ws that InterruptFlag v ar iab le sta ys on 0 until Timer _ InterruptHandler function is requested b y Timer de vice b y stating that the v alue TELK OMNIKA V ol. 13, No . 1, March 2015 : 364 372 Evaluation Warning : The document was created with Spire.PDF for Python.
TELK OMNIKA ISSN: 1693-6930 371 has been reaching z ero then e x ecute the function b y sending interr upt signal to processor and changes the InterruptFlag v ar iab le to 1 f ollo w ed b y , XGpio _ DiscreteWrite(&gpio,LED _ CHANNEL, 0x0A) statement. The timer itself w as configured b y using XTmrCtr _ SetResetValue function f ollo w ed b y 0xf0000000 as its par ameter . The par ameter took around 40.3 seconds f or timer , which supplied b y 100 MHz cloc k signal to reach z ero . Compar ing the approach de v eloped b y Y ang et.al [12] which combining tw o separ ate de vices , ARM processor and FPGA, on a PCB , t his approach giv es less PCB f ootpr int, simplified PCB design and giv es better signal integ r ity . 5. Conc lusion FPGA combined b y hard core processor giv es a better customization f or microcontroller to increase its perf or mance . Hence , this model giv es an alter nativ e from con v entional micro- controller . Sometimes , due to higher cost of FPGA compar ing to con v entional microcontroller , it becomes not so competitiv e hence a designer should w eigh up which requirement needs f or this model compar ing to con v entional microcontroller to get tr ade of f betw een perf or mance and product cost. F or the system, it only use around one percent resource of XC7Z020-CLG484-1 to implement it, and the maxim um frequency which can be used is 216.973 MHz. Ac kno wledg ement This mater iel is based on w or k suppor ted b y Bina Nusantar a Univ ersity under g r ant Hibah Bersaing Bin us 015.A/VR.R TT/IV/2014 and Xilinx Univ ersity Prog r am. Ref erences [1] M. Bohr and K. Mistr y , “Intel’ s re v olutionar y 22 nm tr ansistor technology , Intel w ebsite , 2011. [2] M. J . Smith, “Application-specific integ r ated circuits , 1997. [3] P . Y iannacour as , J . G. Steff an, and J . Rose , “Application-specific customization of soft pro- cessor microar chitecture , in Proceedings of the 2006 A CM/SIGD A 14th inter national sym- posium on Field prog r ammab le gate arr a ys . A CM, 2006, pp . 201–210. [4] Xilinx, “Microb laz e processor ref erence guide v13. 4, ref erence man ual , 2011. [5] J . González-G ómez, E. Agua y o , and E. Boemo , “Locomotion of a modular w or m-lik e robot using a fpga-based embedded m icrob laz e soft-processor , in Climbing and W alking Robots . Spr inger , 2005, pp . 869–878. [6] M. Hubner , K. P aulsson, and J . Bec k er , “P ar allel and fle xib le m ultiprocessor system-on-chip f or adaptiv e aut omotiv e applications based on xilinx microb laz e soft-cores , in P ar allel and Distr ib uted Processing Symposium, 2005. Proceedings . 19th IEEE Inter nation al . IEEE, 2005, pp . 149a–149a. [7] I. Gonzalez and F . Gomez-Arr ibas , “Cipher ing algor ithms in microb laz e-based embedded systems , in Computers and Digital T echniques , IEE Proceedings- , v ol. 153, no . 2. IET , 2006, pp . 87–92. [8] R. L ysec ky and F . V ahid, “Design and implementat ion of a microb laz e-based w ar p processor , A CM T r ans . Embed. Comput. Syst. , v ol. 8, no . 3, pp . 22:1–22:22, Apr . 2009. [Online]. A v ailab le: http://doi.acm.org/10.1145/1509288.1509294 [9] J . Kadlec , R. Bar tosinski, and M. Danek, “Acceler ating microb laz e floating point oper ations , in Field Prog r ammab le Logic and Applications , 2007. FPL 2007. Inter national Conf erence on . IEEE, 2007, pp . 621–624. [10] Q. W ei, Q. Cai, and C . Xie , “Research and implementation of plc editor system, TELK OM- NIKA Indonesian Jour nal of Electr ical Engineer ing , v ol. 12, no . 3, pp . 2133–2137, 2014. [11] Z. Huabing, L. Benlei, D . Bolin, and F . Xiao , “Research on fpga-based prog r ammab le logic controller’ s technology , TELK OMNIKA Indonesian Jour nal of Electr ical Engineer ing , v ol. 11, no . 12, pp . 7655–7663, 2013. Ov er vie w of Custom Microcontroller using Xilinx Zynq FPGA (Ba yu Kanigoro) Evaluation Warning : The document was created with Spire.PDF for Python.
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