TELKOM
NIKA
, Vol. 13, No. 4, Dece
mb
er 201
5, pp. 1153
~1
161
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v13i4.1787
1153
Re
cei
v
ed Ma
rch 2
4
, 2015;
Re
vised Sept
em
ber
30, 20
15; Accepted
Octob
e
r 14, 2
015
Image Encryption using Simple Algorithm on FPGA
Barlian Henr
y
r
anu Prasetio
1
, Eko Seti
a
w
an
2,
Adhar
u
l Muttaqin
3
1,2
Computer S
y
stem and Ro
bo
tics Lab, F
a
cu
lt
y of Com
puter
Scienc
e, Unive
r
sit
y
of Bra
w
i
j
a
y
a, Jl. Vetera
n
Mala
ng, Ph. F
a
x: +
623
41-5
7
7
911
3
Computer S
y
s
t
em and Ro
boti
cs Lab, F
a
cu
lt
y of Engine
eri
n
g
,
Universit
y
of Bra
w
ij
a
y
a, Jl. Veteran Ma
la
n
g
,
Ph. F
a
x: +
6234
1-57
791
1
e-mail: b
a
rli
a
n
@
ub.ac.i
d
1
, ekosetia
w
a
n
@
u
b
.
ac.id
3
, adhar
ul
@ub.ac.i
d
3
A
b
st
r
a
ct
Data sec
u
rity b
e
co
mes
on
e of
the thi
ngs t
hat
nee
d to
be c
o
nsid
ered. T
h
e
Sum of Pro
duc
t (SOP)
Encryption is
one
of simple
algorithm
. The S
O
P encryption
is not a p
ublic-
k
ey system
to
enc
rypt data. it
is
al
most unbr
ea
kabl
e
thro
ug
h brute
forc
e me
thod an
d
vu
ln
e
r
abl
e to
attack
bec
ause
the
encrypti
on
mo
dels
have
a fix
e
d
p
a
ttern. How
e
ve
r, this dr
aw
bac
k can
be
av
oid
ed thr
o
u
gh th
e
compressi
on
p
r
ocess to
re
mo
v
e
the patter
n
file.
SOP encrypti
on a
l
g
o
rith
m c
an us
e a
Boo
l
e
an a
l
g
ebra c
o
mb
in
ation f
unc
tions suc
h
as
AN
D
gate a
nd OR
gate. Simpl
e
algor
ith
m
in
hardw
ar
e l
a
n
g
uag
e VHSIC
Hardw
a
re D
e
s
c
riptio
n La
ngu
age
(VHDL) is on d
a
ta bits leve
l. The pur
pose of this rese
arch is imple
m
entati
o
n
of
imag
e encr
y
ption a
l
gor
it
h
m
to prod
uce a
quick i
m
ag
e encrypti
on sys
tem. F
r
om
r
e
sult test, the imag
e proc
es
sing ti
me w
i
th
out
encrypti
on av
e
r
age 4.9
9
9
n
s/p
x
and 13.
51ns/
p
x w
i
th encryption.
Ke
y
w
ords
: En
cryption, Imag
e, Simple Al
gor
ithm, VHD
L
Copy
right
©
2015 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
Embedd
ed
system is
on
e that emp
hasi
z
e
s
the
appli
c
ation
of se
cu
rity in dat
a
comm
uni
cati
on [1]. Base
d on the Fi
e
l
d Prog
ramm
able G
a
te Array (FPGA
)
se
curity sy
st
em
architectu
re,
a se
cu
rity attack ca
n be
categori
z
e
d
in
to two in an
attack o
n
the
hard
w
a
r
e an
d
softwa
r
e [2].
In ge
neral, the e
n
cryp
tion process co
ndu
cted
by u
s
ing
softwa
r
e th
a
t
is
prog
ram
m
ed
in compute
r
.
Practi
ce, o
n
ly a fe
w
ap
plications re
quiri
ng throug
hpu
t while flexibl
e
solutio
n
s a
n
d
low co
st en
cryption / decryption is
nee
ded to protect the dat
a that make
s se
nse,
esp
e
ci
ally for embe
dde
d h
a
rd
wa
re a
ppl
ication
s
[3].
The e
n
crypti
on ima
ge
ca
n be
moved
into
comp
uter by
the softwa
r
e
before
p
a
ssin
g it to
anoth
e
r
d
e
vice.
The
use
of comp
uters a
s
med
i
a
encryption
on sm
all devices
such as
surveillanc
e cameras is less appropriat
ely. Some
small
device
s
su
ch
as FP
GA hav
e bee
n pote
n
t
ial to be a
ppl
ied to repla
c
e
the compute
r
a
s
a m
ediu
m
for image en
cryption. Th
e
FPGA spee
d to data
pro
c
e
ssi
ng can comp
en
sate for the percei
v
ed
performance
of the co
mputer. The dat
a encryption system
will
be optimized with the to be
implemented
into the FPGA because it has
adv
antages which include
flexibilit
y, developm
ent
co
st and cost
s low p
e
r-unit
,
high spe
ed
and ha
s a go
od level of se
curity [4].
Variou
s
kind
s of encryption
method
s can
be
u
s
ed to
secu
re the
dat
a. Each m
e
th
od ha
s
advantag
es
a
nd di
sadva
n
tage
s. The m
a
in pro
b
le
m i
s
how to
kn
ow
and u
nde
rsta
nd the
workin
gs
of the encryp
t
ion method
algorith
m
. Wi
th Modula
r
M
u
ltiplication B
a
se
d (MMB
)
Encryptio
n
using
128-bit plai
ntext iterative
algorith
m
s which
con
s
ist
s
the li
nea
r
steps an
d the
four m
a
jo
r n
on-
linear
sub
s
titutions pa
rall
e
l
applicatio
n can b
e
reversed. Thi
s
su
bstitution is
determi
ned b
y
a
multiplicatio
n
modulo
232
-1 with a
con
s
tant fact
o
r
, whi
c
h ha
s a
highe
r level
of se
curity when
comp
ared
with the m
e
thod
of the Inte
rn
ational
Data
Encryptio
n
Al
gorithm
(IDE
A) that o
n
ly u
s
e
s
multiplicatio
n
modulo
216
+ 1. MMB u
s
ing 32
-bit su
b blo
ck text (x0, x1, x2 and x3) an
d 32
-bit
sub
blo
c
k ke
y (k0,
k1,
k2,
k3
). Thi
s
m
a
ke
s the
algo
ri
thm is ve
ry suitable to i
m
p
l
ement o
n
3
2
-
bit
proc
es
sors
[5].
Simple image encryption u
s
ing XOR technique bet
we
en the pixels
of plain-imag
e with a
key encryption method is not secure
against kn
o
w
n-plaintext
attack. Howe
ver, the simple
encryption method can ha
ve time
for encryption and de
cryption process is relati
vely
fast, it is
due
to the efficiency that occurs at
a key plant so that it can be can
be u
s
ed in real-ti
m
e systems such
as digital phone lines.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No
. 4, Decem
b
e
r
2015 : 115
3 – 1161
1154
Known-plainttext attacks can guess the encry
ption key by comparing the number of
plain-image (the original image) with t
he ciphe
r-im
age
(image e
n
crypted) correspon
ding.
This
variants known-plaintext a
t
tack is
called
selective plaintext attack.
In his research, Munir provides
an analysis of the selective-plaintext atta
ck again
s
t a proposed
ch
aos-ba
s
ed im
age encryption
algorithm. The algorithm combines the technique
s of permutations (using Arnold
Cat Map) an
d
substitution technique
s (u
si
ng XOR
operation). Base
d
on a
se
ries
o
f
experiments that have be
en
performed ca
n be conclud
ed that scrambles the
pixels before the XOR opera
t
ion can make the
algorithm secure against selective-plaintext a
ttack [6].
Almost all existing techniq
ues
req
u
ire
a lo
t of data encryption a
r
ithmetic a
n
d
logica
l
cal
c
ulatio
ns,
thus the
em
bedd
ed devi
c
e
s
ma
ke
s
difficult to a
pply [7]. But with the si
mple
algorith
m
wo
uld be ea
sy.
One form of Boolean al
g
e
b
ra eq
uation
s
use
d
almo
st throug
hout
in
digital d
e
vice
is Sum
of P
r
o
duct
(SOP
).
SOP ha
s
bee
n pote
n
tial to
be
sele
cted
a
s
the
e
n
cryption
algorith
m
on
a small d
e
vice whe
n
time factor
be
come
s an imp
o
rtan
t. In addition, SOP algorith
m
can d
o
the de
cryption p
r
o
c
ess so it able
to resto
r
e the
original d
a
ta.
Based
o
n
th
e conditio
n
,
we
re
se
arch
imag
e e
n
cryption on
Xili
nx Sparta
n
3
E
FPGA
module
by applying the
SOP algorith
m
. This pa
p
e
r is a
n
initi
a
l step p
r
o
c
ess of imag
es
encryption o
n
small
devi
c
e
s
such a
s
FPGA. The
purp
o
se of
this pa
per i
s
that it can
be a
referen
c
e for
future wo
rk such a
s
ma
kin
g
the
equipm
ent that origi
nally
did not have a se
cu
ri
ty
netwo
rk by a
dding thi
s
de
vice ha
s a se
cure.
Operators Exclu
s
ive-O
R
(XOR) i
s
simp
le in
pri
n
ci
ple
the sam
e
a
s
Vigene
re
cip
her
key
usin
g pie
c
e
s
are repe
ated
periodi
cally throu
gho
ut
the plain-text [8]. Vigenere
table co
nsi
s
t
s
of
pairs ea
ch
letter plain
-
text, key an
d ci
ph
er-text resu
lts. In prin
ciple,
every bit plai
n-text XOR
with
each bit of th
e key to
the
ciph
er-text produ
ced
bits. Comm
ercial prog
ram
s
are
DOS
-
ba
sed
or
Ma
c
i
n
t
os
h usin
g
a s
i
mp
le
XO
R
a
l
g
o
r
i
thm [9
]. SO
P en
c
r
yp
tion
a
l
go
r
i
th
ms
c
a
n be
pr
e
p
a
r
e
d
us
in
g
the basi
c
Boo
l
ean XOR o
p
e
rato
r.
SOP Encrypti
on is not a p
ublic-key syst
em
to encryp
t
data. Encryption ca
n be
solved
throug
h
brute
force
metho
d
. It is vulne
r
able to
atta
ck
be
cau
s
e the
encryption m
odel
s have been
fixed pattern.
Ho
weve
r, this d
r
a
w
ba
ck
can
be
avoi
d
ed through
the comp
re
ssion p
r
ocess t
o
remove th
e p
a
ttern file. S
O
P en
cryptio
n
algo
rithm
can u
s
ed
a
co
mbination
of
Boolean
alge
bra
function
s
su
ch as A
ND
a
nd O
R
. In a
ddition,
the desi
gne
rs of
comp
uter systems are usin
g
advantages of Xilinx Spart
an-3E
FPGA.
The Xili
nx
FPGA families
carry mi
croblaze
processors
[10], type of gene
ration th
at can
be a
p
p
lied to a va
riety of use
r
a
pplication
s
, it has
adju
s
tm
ent
interface an
d data stan
da
rd
s, and it
ca
n disting
u
ish function
ality with minimal de
sign time. It can
be allows
a low cost im
age encry
ption f
o
r embedded
system
s whil
e still pr
ovidi
n
g a good trade-
off betwe
en
p
e
rform
a
n
c
e
a
nd h
a
rdwa
re
resou
r
ces [11
]. Author
emp
hasi
z
e
s
th
e S
u
m of P
r
od
uct
(SOP) blo
ck arithmeti
c
alg
o
rithm
s
to co
llecti
on
of ca
scade
d blo
cks p
e
rfo
r
ming
unit ope
ratio
n
s
[12-15].
2. Rese
arch
Metho
d
The overall system de
sign
includ
es a
n
encry
ption al
gorithm
conv
ersi
on into h
a
rd
wa
re
architectu
re, softwa
r
e
in
stallation su
pp
ort,
config
u
r
a
t
ion, and
de
sign of
reli
abil
i
ty system. T
h
e
overall p
r
o
c
e
ss of en
cryption and d
e
cryption is sho
w
ed in Figu
re 1
.
SOP algo
rith
m wo
rks
by gene
rating
a
ran
dom
key
.
The
pe
rformance comp
arison of
ciph
er text sh
ows that over t
he normal text, cipher te
xt is very difficult, and time
con
s
umi
ng t
o
cra
c
k [16, 17]
.
In the FPGA module, on
e colo
r pixel fro
m
plai
n-im
ag
e is rep
r
e
s
en
ted in 3 bits data. An
image
con
s
i
s
ts of 3 bit
s
of
data that ma
ke up the
ov
erall pixel color
plain-i
m
age. I
f
3 bits of d
a
ta
in a
singl
e pi
xel is
rep
r
e
s
e
n
ted by A
mn
variabl
e, with
m indi
cating
the n
u
mbe
r
of
ro
ws an
d n
i
s
the numb
e
r o
f
column
s of
pixels of an i
m
age, so a p
l
ain-im
age
ca
n be de
scrib
e
d
in matrix form
as de
scrib
ed
in Figure 2.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Im
age Encryption usi
ng Sim
p
le Algorithm
on FPGA
(Barlian Hen
r
yranu
Prasetio
)
1155
Figure 1. The illustration of
plain image
A
00
A
01
A
02
A
03
A
10
A
11
A
12
A
13
A
20
A
21
A
22
A
23
A
30
A
31
A
32
A
33
Figure 2. The
matrix of plain image
The gen
eral form of SOP is given by :
̅
(
1
)
x and y
are v
a
riabl
es that
make
up
a
fu
nction. x'
is
a
negatio
n form
of x. Fo
rm of
neg
ation i
s
t
r
ue
of all the variable
s
that make the eq
ua
tion.
The impl
ementation o
f
SOP are easy and stan
d
in
level bit, so make the e
n
cryption pro
c
e
ss faster.
Equation of e
n
cryptio
n
and
decryptio
n proce
s
se
s are
descri
bed a
s
follow :
Ci =
E(Pi,Ki)
Pi = D(
Ci,Ki)
whe
r
e:
Ci : Chipp
e
r
Pi : Plain
Ki : Key
In
th
e
en
cr
yptio
n
pr
oc
e
s
s
,
a
c
i
p
h
e
r
o
f
da
ta
(C
) ca
n be
d
e
t
er
mine
d b
y
pr
oc
es
s
i
ng
in
the
data plain
(P) and en
crypti
on key
(K) by
using th
e
SO
P. The encry
ption process is pe
rform
ed
on
each pixel compo
s
ing th
e plain
-
imag
e. Ciphe
r dat
a from certai
n colu
mn
s a
nd ro
ws of p
i
xels
obtaine
d thro
ugh SOP b
e
twee
n plain
pi
xel data in th
e sam
e
po
siti
on with the
e
n
cryptio
n
key.
Illustration S
O
P operation
on each pixe
l is des
cri
bed
by the followi
ng matrix as f
o
llows:
(
2
)
The re
sult
s o
f
pixels cip
h
e
r
will be
re
-constr
ucte
d a
c
cordantly wit
h
the po
sitio
n
of the
rows an
d col
u
mns of pixe
ls plain. Illust
ration
of the placement of
each pixel cipher in
ciph
er-
image is d
e
scribed in Fi
gure 3.
C
00
C
01
C
02
C
03
C
10
C
11
C
12
C
13
C
20
C
21
C
22
C
23
C
30
C
31
C
32
C
33
Figure 3. The illustration of
chipper
En
cryp
t
ion
SO
P
Decr
yp
tion
SOP
to
3
-
b
it im
ag
e (p
l
a
in
)
3
b
it Im
ag
e (p
lain
)
Key
Transfe
r
FPGA
3 bi
t
Im
a
g
e
(
chi
p
er
)
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No
. 4, Decem
b
e
r
2015 : 115
3 – 1161
1156
Pseud
o co
de
from en
crypti
on method by
using SOP is describ
ed by
:
for (i=0;i<
m
;i++
){
for
(j=0;j<
n
;j++
){
if
(k==8){
k=
0;
}
else
{
k=
k
+
1;
}
C[i][j]=
( A[i][j
] AND NOT K
[
k
]
) OR (
NOT A [i]
[
j] AND K[k
]
);
}
}
3. Results a
nd Discu
ssi
on
In this se
ctio
n, testing wa
s co
ndu
cted
by c
onn
ectin
g
the monitor to the VGA
port LEDs
contai
ned in
the FPGA module. T
he n
e
xt step of th
e test is to enter and run
into the prog
ram
module
s
. Fig
u
re
4 is
sh
owed FPGA m
o
dule
con
d
itio
n that the m
o
nitor
cabl
e is
con
n
e
c
ted to
the
LED.
Figure 4. Xilinx Spartan 3E FPGA modul
e is co
nne
cte
d
to monitor
RTL Schemat
ics
Diag
ram o
f
the system can b
e
se
en
on figure 5.
Figure 5.
RTL
Schemati
cs
Diag
ram
Figure 5
sho
w
ed th
at the
system im
pl
em
ented
usi
ng RTL Sch
e
matics. The
system
c
o
ns
is
ts
of c
l
ock
divider, buffers
, memory, encry
ption
,
mux, rea
der and
VGA
co
ntrolle
r. The
RT
L
Schem
atics De
scription
showed in tabl
e 1.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Im
age Encryption usi
ng Sim
p
le Algorithm
on FPGA
(Barlian Hen
r
yranu
Prasetio
)
1157
Table 1.
The RTL
Schemat
ics De
scriptio
n
Main S
y
st
em
Inpu
ts:
•
clk – Clock
signa
l, port A8 of the
F
P
GA.
•
reset – Push butt
on 0 (BT
N
0)
•
U – 3-bit user inp
u
t passw
o
r
d.
Bit 0 – BTN1.
Bit 1 – BTN2.
Bit 2 – BTN3.
Ou
tpu
t
s:
•
hsync – Horizont
al sy
nch
r
onism of the VGA.
Port R6 of th
e F
P
GA.
•
vsy
nc – Ve
rtical sy
nch
r
onism of t
he VGA. Por
t
R7.
•
VGA_out_
r
ed –
Red signal to the
FPGA.
Bit 0: P16.
Bit 1: P15.
Bit 2: T7.
Bit 3: R5.
•
VGA_out_g
reen
– Gre
en signal.
Bit 0: N15.
Bit 1: J16.
Bit 2: K16.
Bit 3: K15.
•
VGA_out_blue –
Blue signal.
Bit 0: L15.
Bit 1: M16.
Bit 2: M15.
Bit 3: N16.
Com
p
o
n
en
t: e
n
cr
y
p
ti
on
Inpu
ts:
• U
U of
the s
y
st
em.
• P
signal datare
ad.
Ou
tpu
t
:
• O
signal datae
ncr
y
p.
Com
p
o
n
en
t: mu
x
Inpu
ts:
• clk
clk of the sy
st
em.
• ennormal
sign
al enormal.
• enencr
y
p
sign
al eencr
y
p.
• data_norm
a
l
signal dataread
.
• data_encr
y
p
si
gnal dataencr
y
p.
Ou
tpu
t
:
• dataout
signal colors.
Com
p
o
n
en
t:
v
g
a_con
t
roller
Inpu
ts:
clk
clk of the sy
st
em.
res
e
t
r
e
set of t
he s
y
stem.
VGA_in_red
(0)
signal colors(2). The bits 1
and 2 of V
G
A_in_red have to b
e
connected to a
constant ‘0’.
VGA_in_gree
n(0
)
signal color
s
(1). The
bits
1 and 2 of V
G
A_in_green have
to be
connected to a constant ‘0’.
VGA_in_blue(0
)
signal colors(0). The
bits 1
and 2 of V
G
A_in_bluehave to be
connected to
a constant ‘0’.
Ou
tpu
t
s:
• col
signal cols.
• r
o
w
signal ro
w
s
.
• VGA_out_
r
ed
VGA_out_
r
ed
of the
s
y
stem.
• VGA_out_g
reen
VGA_
out_gr
e
en of the
sy
stem.
• VGA_out_blue
VGA_
out_blu
e
of the s
y
stem.
• hsy
n
c
hs
ync of the s
y
stem.
• vsy
nc
vs
ync of the s
y
stem.
Mappi
ng declar
ation
of the
v
g
a
_con
t
roller:
m
y
vga: vga_cont
roller
por
t map
(
clk => clk,
reset => reset,
VGA_i
n_red
(0)
=> c
o
l
o
rs
(2),
VGA_in_red
(3
do
w
n
to 1
)
=> "00
0
",
VGA_in_gre
e
n
(
0) => colors(1),
VGA_in_gre
e
n
(
3 do
w
n
t
o
1) => "
000",
VGA_in_blue(0
)
=> colors(0),
VGA_in_blue(3
do
w
n
to 1
)
=> "0
00",
col => cols,
ro
w
=> ro
w
s
,
VGA_out_
r
ed
=> VGA_out_r
ed
,
VGA_out_g
ree
n
=> VGA_out_g
reen,
VGA_out_blue
=> VGA_out_blu
e
,
hsync => hs
y
n
c,
vsy
nc => vs
y
n
c
);
Testing i
s
do
ne by applyin
g
encryption
on seve
ra
l dif
f
erent pie
c
e
s
of plain imag
e. Some
image
s of Plain-im
age an
d ciph
er
-imag
e
is sh
owed i
n
Figure 6.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No
. 4, Decem
b
e
r
2015 : 115
3 – 1161
1158
Figure 6.
The
image en
cry
p
tion pro
c
e
ss Testing
Spartan 3E F
P
GA module
can b
e
displ
a
ying
every
pixel of rep
r
e
s
entatio
n ima
ge in 3-
bit. The comb
ination with i
m
age di
splay
ed bits are sh
owe
d
in Tabl
e 2.
Table 2.
The
3-bit data an
d
color FP
GA combi
nation [
18]
VG
A Red
VG
A Green
VG
A Blue
Resulting Color
0 0
0
Black
0 0
1
Blue
0 1
0
G
r
e
en
0 1
1
Cy
a
n
1 0
0
Red
1 0
1
Magenta
1 1
0
Y
e
llow
1 1
1
White
Key encrypti
on i
s
u
s
e
d
o
n
the te
st i
s
'
101 '.
In first
test sho
w
n i
n
Figu
re
6A, the pl
ain-
image
that i
s
use
d
i
s
red
with data
re
pre
s
entatio
n '
1
0
0
'
on
all pixe
ls. SOP
en
cryption alg
o
rit
h
m
will
cal
c
ulate every
bit plain-image
and key
by
using the followi
ng equat
ion to get the
cipher-
image.
001
1
0
.
0
1
.
1
0
1
.
0
0
.
1
0
0
.
1
1
.
0
101
100
0
0
0
0
0
1
1
1
1
1
2
2
2
2
2
C
K
P
K
P
C
K
P
K
P
C
K
P
K
P
C
K
P
B
A
C
D
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Im
age Encryption usi
ng Sim
p
le Algorithm
on FPGA
(Barlian Hen
r
yranu
Prasetio
)
1159
Based
o
n
tab
l
e 2,
ciph
er-i
mage
with
a
bit value
of "
001"
will
sh
o
w
a
blu
e
colo
r o
n
the
LED screen.
This test explain
s
that the FP
GA module ca
n en
crypt variou
s plain-i
m
age i
n
to
ciph
er-imag
e
corre
s
po
ndi
ng to the given ke
y. Encrypte
d image
s have
different color
combi
nation
s
with the origi
nal image.
Test
s we
re al
so pe
rform
e
d
on some of the co
l
o
r com
b
ination
s
that
can be ge
ne
rated by
the mod
u
le F
P
GA. In Figure 6B, plain
-
i
m
age
used
wa
s '
101
'. Sa
me a
s
the
ke
y used
previo
usly
so that cip
her-imag
e
as foll
ows:
P
101
K
101
C
2
P
2
K
2
P
2
K
2
0.1
1.0
0
C
1
P
1
K
1
P
1
K
1
1.0
0.1
0
C
0
P
0
K
0
P
0
K
0
0.1
1.0
0
C
000
Ciph
er-gen
erated image i
s
a blac
k acco
rdan
ce
with table 2. In testing usin
g dat
a plain-
image '1
10 'a
s sh
own in Figure 6
C
, will
prod
uce cip
h
e
r-im
age the
data belo
w
:
P
11
0
K
10
1
C
2
P
2
K
2
P
2
K
2
0.
1
1.0
0
C
1
P
1
K
1
P
1
K
1
0.0
1.1
1
C
0
P
0
K
0
P
0
K
0
1.1
0.0
1
C
01
1
Ciph
er code
-gene
rated im
age is '0
11 ',
repr
esented
by the cyan color in a
ccorda
n
ce
with Table 2.
In Figure 6
D
, testing is
done by
inse
rting the plai
n-ima
ge pixel
s
'111 '. Ci
p
her-
image pixel
s
are ge
ne
rate
d from the en
cryption p
r
o
c
ess is obtai
ne
d as follo
ws:
P
11
1
K
10
1
C
2
P
2
K
2
P
2
K
2
0.1
1.0
0
C
1
P
1
K
1
P
1
K
1
0.0
1.
1
1
C
0
P
0
K
0
P
0
K
0
0.1
1.0
0
C
01
0
Ciph
er-gen
erated image i
s
'010
' whi
c
h
is r
epresent
ed by the col
o
r green. Th
ese te
sts
indicate that
the
en
cryp
tion meth
od
co
uld
have
bee
n im
ple
m
ented
into
ha
rd
ware-le
v
el
prog
ram
m
ing
langua
ge an
d is able to produ
ce differe
nt color
cod
e
s with the dat
a plain-i
m
age
.
System testi
ng is
emph
a
s
ized at the
image
exe
c
u
t
ion time. Th
e system
wa
s teste
d
usin
g seve
ral
picture si
ze
s and
cal
c
ul
ate time
encryption. The
image te
st result
s with a
n
d
without en
cry
p
tion ba
sed o
n
image si
ze
can b
e
se
en i
n
Table 3.
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No
. 4, Decem
b
e
r
2015 : 115
3 – 1161
1160
Table 3. Imag
e Processin
g
Time Com
p
a
r
ison
b
e
twe
e
n
without and
with en
cryptio
n
based on
image si
ze
Image size
(px
)
Without
encr
y
ption
(ns
)
With
encr
y
ption
(ns
)
1x1
5.001
13.514
10x1
50.003
135.150
10x5
250.035
675.700
10x10
500.002
1351.500
20x50
5000.006
13514.200
20x80
8000.001
21624.000
40x90
18000.024
48650.400
40x100
20000.864
54056.000
50x100
25001.359
67570.089
50x150
37500.997
101362.500
75x150
56251.000
152032.500
75x200
75000.056
202734.080
100x20
0
100000.845
270280.100
100x25
0
125000.126
337825.005
150x30
0
225000.221
608130.013
Table
3
sh
ows that
time e
n
cryptio
n
i
s
v
e
ry
fa
st in
na
nosecond
s. E
nhan
ce
d ima
ge
size
of each 1
0
-fol
d. Encryption
each time the image si
ze in
cre
a
sed an a
v
erage 1
3
.5n
s
.
4. Conclusio
n
Based o
n
the
test result
s it is con
c
lu
ded
t
hat the encryption metho
d
in image en
cryption
sop
can
be
i
m
pleme
n
ted i
n
to the
FPG
A
modul
e. Si
mple m
e
thod
ca
n
en
crypt
the o
r
igin
al i
m
age
(the plai
n-im
age) i
n
to th
e en
crypted
image (cip
her-imag
e
) i
s
differe
nt. The en
cryption
impleme
n
tion
metho
d
into
fPGA mod
u
l
e is do
ne
with the first
set of inp
u
t o
u
tput mo
dule
s
according to t
he ha
rd
ware
config
uratio
n
use
d
.
The ssucce
ss im
ple
m
entation i
s
the sta
r
ting po
int
of the applica
t
ion of encryp
t
ion image
s o
n
small devi
c
es.
Xilinx Sparta
n-3E FP
GA modul
e dat
ash
eet
expla
i
ned that it
can
only h
andle
a
maximum of 3 bits of ima
ge data [18].
The u
s
e
of F
P
GA device
s
is ca
pabl
e o
f
handling la
rger
bits images, will be able to encrypt im
ages with lot
s
of color
choi
ces.
From
res
u
lt tes
t, the image proc
ess
i
ng
time without
encryption average
4.999ns
and
13.51n
s with
encryption.
Referen
ces
[1]
Adib El S, Raissaoni N. AES
Encr
y
p
t
i
on A
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Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Im
age Encryption usi
ng Sim
p
le Algorithm
on FPGA
(Barlian Hen
r
yranu
Prasetio
)
1161
[1
3
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