TELKOM
NIKA
, Vol.13, No
.1, March 2
0
1
5
, pp. 55~6
4
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v13i1.1299
55
Re
cei
v
ed O
c
t
ober 2
6
, 201
4; Revi
se
d Novem
b
e
r
24, 2014; Accept
ed De
cem
b
e
r
28, 2014
Design and Simulation of Quadrature Phase Detection
in Electrical Capacitan
ce Volume Tomography
Imamul Muttakin*, Arbai
Yusuf, Roh
m
adi, Wah
y
u Widada, Warsito P. Tar
uno
CT
ECH Labs Ed
w
a
r T
e
chnol
og
y
Jl. Jalur Sutera
Kav. Spektra 23 BC No. 10-
12 Alam Suter
a
,
T
angera
ng,
Banten, Ind
o
n
e
sia
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: imuttakin@c-
techla
bs.com
A
b
st
r
a
ct
Capac
itanc
e me
asur
e
m
ent
accuracy is a
ffect
ed by ph
ase conf
ormity betw
een si
gna
l an
d
referenc
e. T
h
is
w
o
rk describe
s
phase
detect
i
on sch
e
m
e w
h
ich is
necess
a
ry for phas
e
synchro
ni
z
a
ti
o
n
in
tomo
gra
phy
ap
plicati
on. C
o
re
process
i
ng f
o
r calcu
l
atin
g p
h
a
se a
nd
a
m
pl
itude
of the d
e
tected si
gn
al w
a
s
built o
n
F
P
GA
(F
ield-Pro
gra
m
ma
bl
e Gate-Array) platfor
m
. Phase sh
ift de
mo
du
latio
n
al
g
o
rith
m e
m
p
l
oy
s IP
core pr
ovid
ed
by Xil
i
nx F
P
GA. Direct di
git
a
l synth
es
i
z
er
(DDS), multi
p
lier,
acc
u
mul
a
tor, and
CORD
I
C
(coordi
nate rot
a
tion d
i
gita
l co
mp
uter) mod
u
l
e
s w
e
re us
ed
as excitatio
n
-r
eferenc
e sig
n
a
l
gen
erator, sig
nal
mu
ltipl
i
cati
on, accu
mu
latio
n
, and co
nversi
on
to polar
coor
di
nate in or
der to
conduc
t trigo
n
ometric op
erati
o
n
respectiv
e
ly.
Hardw
a
re
des
ign w
a
s e
m
ul
ated o
n
MAT
L
AB-Xili
nx Sy
stem Gen
e
rat
o
r to obs
erve
its
perfor
m
a
n
ce.
Phase
det
ectio
n
ran
g
e
0-1
14.
58
o
a
nd mean
abso
l
ute error 0.58
o
h
a
ve be
en achi
eve
d
.
D
a
ta
process
i
ng
rat
e
sol
e
ly
at di
git
a
l si
gn
al sta
ge
w
a
s appr
oxi
m
a
t
ely 10
0d
ata/s
suitab
le for
32-
chan
nel
el
ectri
c
al
capac
itanc
e vo
lu
me to
mo
grap
hy (ECVT) system.
Ke
y
w
ords
: quadratur
e demodul
ation, phase detection, system
generator,
FPGA, ECVT
1. Introduc
tion
Phase
d
e
tect
ion i
s
o
n
e
of
the m
o
st
im
portant
featu
r
e i
n
d
a
ta a
c
quisitio
n
syst
em for
electri
c
al
ca
pacita
n
ce vo
lume tom
o
g
r
aphy
(E
CVT
)
. ECVT
is
a volum
e
tric (real
-time
3
D
)
tomography techni
que ba
sed on
cap
a
citan
c
e me
asu
r
em
ent which ha
s re
placed cla
s
si
ca
l
system i
n
two
-
dime
nsi
onal
slici
ng for to
mography
im
aging [1]. Th
e forme
r
el
ectrical
ca
pacit
ance
tomography (ECT) meth
od
basically utilize
s
sen
s
itiv
ity of certain capa
citive sen
s
or
config
urat
ion
to map p
e
rmi
ttivity distribut
ion in th
e obj
ect
sp
a
c
e. It i
s
a
non
-radia
t
ion, non
-inva
s
ive, and
lo
w-
co
st
sy
stem whi
c
h ha
s
b
e
en widely used
in
pet
ro-c
hemical p
r
o
c
ess in
du
stry
as
well
a
s
m
edical
appli
c
ation
s
[2]. However, this m
odali
t
y come
s
wi
th ill-po
se
d i
n
verse p
r
o
b
l
e
m a
s
n
a
tural
cha
r
a
c
teri
stic of similar
soft-field to
mography
e.
g. optical m
o
lecular ima
g
ing [3] he
nce
advan
ceme
nt in image re
constructio
n
al
gorit
hm a
nd h
a
rd
wa
re de
si
gn are
signifi
cant.
Data a
c
q
u
isiti
on sy
stem
collect
s data
obtaine
d fro
m
se
nsor to
be form
ed
a
nd sent to
comp
uter
whi
c
h ma
nipulat
es the data
pattern in
to i
m
age u
s
ing
spe
c
ific al
gorithm. In the
well-
kno
w
n
ci
rcuitry for
cap
a
cit
ance to volta
ge (C-V
)
con
v
ersio
n
, mea
s
ureme
n
t accura
cy is
affected
by pha
se con
f
ormity betwe
en outp
u
t C-V signal
and
referen
c
e sig
nal.
This ci
rcumstan
ce ma
ke
s
phase tracking necessary
for sy
stem’s
reliability to reduce
phase error [4]-[5
]. Figure
1 shows a
lock-in m
e
ch
anism in front
of C-V circuit
to ex
tract informatio
n fro
m
measure
d
cap
a
cita
nce.
Figure 1. Cap
a
citan
c
e to voltage ci
rcuitry with lock-in
mech
ani
sm
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 1, March 2
015 : 55 – 64
56
Acco
rdi
ng to
Figure 1, if both
V
ref
and
V
2
signals
have identi
c
a
l
phase,
V
o
will
only
related
to a
m
plitude
of input si
gnal
s.
Ho
weve
r, pr
actically two
sign
als
add
e
d
into lo
ck-in
will
gene
rate
ad
ditional pha
se differe
nce
which
d
e
c
re
ases o
u
tput am
plitud
e an
d
cau
s
es
measurement
erro
r. The a
dditional ph
a
s
e differe
nc
e
is relevant towa
rd stray cap
a
cita
nce, and
different
stra
y cap
a
citan
c
e bri
n
g
s
diff
erent
pha
se
angle. T
here
f
ore, ph
ase
shift will i
m
p
o
se
certai
n erro
r. By using coh
e
rent d
e
mod
u
lation to
det
ect the si
gnal
with pha
se trace
r
ci
rcuit, this
kind of probl
em can be
well add
ressed. Consequent
ly, multiplie
r output will reach m
a
ximum,
circuit is stra
y-immune, in
the same tim
e
sen
s
itivity a
nd stability of t
he system can be improved
[4].
Perform
a
nce improvement will be achieved by
implementing m
o
st functionality into
digital h
a
rd
ware
rath
er th
an a
nalo
g
. Fi
eld-Prog
ram
m
able
Gate
-Array
(FPGA
)
i
s
e
m
ploye
d
a
s
control p
r
o
c
e
ssi
ng
core, e
x
citation si
gn
al gene
ratio
n
,
and sig
nal
demod
ulation
.
The mod
u
lar
desi
gn of FPGA prod
uces minima
l hardwa
r
e overh
ead, is flexible, fast, and stable in orde
r to
facilitate further development
of measurement system.
2. Capaci
tan
ce Meas
ure
m
ent
The ac-b
ased
capa
citan
c
e
measurement
ci
rcuit schem
atic is sho
w
n
in Figure 2.
Figure 2. Sch
e
matic of a
c
-based
capa
ci
tance me
asurement ci
rcuit
From the
circuit, absolute
cap
a
cita
nc
e value can be o
b
tained u
s
in
g
equation,
(1)
whe
r
e
C
x
is
measured ca
pacita
n
ce,
C
f
is ch
arg
e
-a
m
p
lif
ier f
eedb
a
ck
cap
a
cit
a
nc
e,
R
1
and
R
2
are
feedba
ck gai
n, and
k
i
s
multiplication factor. For the im
ple
m
entation, chi
p
Di
re
ct Dig
i
tal
Synthesizer (DDS
) A
D
985
0 was u
s
ed
as
wavefo
rm
gen
erator
controlle
d by
Arduin
o
to
set
sinu
soi
dal sig
nal of certai
n freque
ncy. Capa
ci
tan
c
e m
easure
m
ent circuit an
d gai
n AD817
(gre
en
box), multipli
er A
D
633
(ye
llow b
o
x), an
d low-p
a
ss
filter L
T
C1
062
(red
box)
alon
g with
re
spe
c
tive
output sig
nal
s are d
epi
cte
d
in Figure 3 belo
w
.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
9
30
De
sign a
nd Sim
u
lation of
Quad
ratu
re Phase Dete
ctio
n in Electri
c
al
.... (Im
a
m
u
l
Muttakin
)
57
Figure 3. Analog DDS wav
e
form ge
nera
t
or (left)
; c
apa
c
i
ta
nc
e
meas
u
r
e
m
en
t c
i
rcu
i
t (
c
e
n
ter
)
;
output sig
nal
s (ri
ght)
Experiment result
s we
re o
b
se
rved on o
scill
osco
pe to analyze outp
u
t of each st
age for
the given m
e
asu
r
ed
capa
citance val
ue.
Referrin
g
to t
he Fig
u
re
3
(right), yello
w
trace
si
gnal i
s
DDS
wavefo
rm, blue tra
c
e
is outp
u
t of
C-V
conve
r
te
r plu
s
inve
rtin
g gain,
red trace i
s
m
u
ltiplier’s
output, an
d
gree
n trace
is f
iltered output sign
al.
Final DC
voltage wa
s
co
nverted
i
n
to
cap
a
cita
nce value u
s
ing
(1) and co
mpa
r
ed with real capa
citan
c
e te
st value from
1pF-13pF
as
in
Table 1 an
d p
l
otted in Figure 4.
Table 1. Mea
s
ureme
n
t Re
sult
Vo (V)
C real (p
F)
C meas
(p
F)
0.356
1
3.916
0.465
2
5.115
0.627
3
6.897
0.751
4
8.261
1 5
11
1.1 6
12.1
1.24 7
13.64
1.44 8
15.84
1.56 9
17.16
1.82 10
20.02
2.04 11
22.44
2.16 12
23.76
2.36 13
25.96
Figure 4. Measu
r
ed
cap
a
citance vs
real
capa
citan
c
e
value
It can be se
e
n
in Table 1,
there a
r
e differen
c
e
s
bet
ween mea
s
u
r
e
d
cap
a
cita
nce values
and real cap
a
citan
c
e valu
es. Neve
rthel
ess, Figu
re 4
sho
w
s m
e
a
s
urem
ent’s lin
ear tre
nd
with R-
squ
a
re
0.995
and level
of confid
en
ce
95%. The
a
c
curacy
pro
b
l
e
m o
c
curs b
e
ca
use of ph
ase
inco
nformity betwe
en ac measur
ement
output
si
gn
al an
d m
u
ltiplicato
r
refe
rence
sign
al.
So,
pha
se syn
c
h
r
onization of signal
s sh
ould
be con
d
u
c
te
d in ord
e
r to
obtain a
c
cura
te capa
citan
c
e
measurement
value. As in
itial step, ph
ase
dete
c
tion
mech
ani
s
m
is ne
ce
ssary.
The follo
win
g
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 1, March 2
015 : 55 – 64
58
se
ction
s
will
explain ha
rd
ware de
sign f
o
r qua
drature
phase dete
c
tion algo
rithm
whi
c
h ha
s be
en
pres
ented in [6].
3. Quadra
tur
e
Demodula
t
ion
Modulatio
n a
nd demo
dula
t
ion techniq
u
e
s re
ga
rding
signal’
s
ph
ase info
rmati
on are
comm
only found in com
m
unication the
o
ry. Variou
s modulatio
n p
r
inci
ple with i
t
s perfo
rman
ce
analysi
s
and
algorith
m
for digital pha
se
modulatio
n are descri
bed i
n
[7] and [8]
respe
c
tively.
In
pha
se dete
c
t
i
on, sine
sig
nal nee
ds to
be demo
d
u
l
ated with m
easure
d
pa
rameter. Di
gital
demod
ulation
make
s use
of referen
c
e sign
al
ge
nerate
d
from
DDS to digitally modul
ate
measured si
g
nal to obtai
n i
t
s amplitude
and ph
ase.
s
i
n
;
s
i
n
;
cos
∑
∙
∑
sin
∙
s
i
n
cos
∑
∙
∑
cos
∙
s
i
n
sin
√
;
t
an
(2)
This syn
c
ron
ous mo
dulati
on a
n
d
dem
odulatio
n (P
SD, al
so
known a
s
ph
ase
shift
demod
ulation
)
ha
s hig
h
preci
s
ion a
nd a
daptation
lev
e
l based o
n
matche
d filter theory which
is
linear time-i
n
v
ariant
by ma
ximizing
sig
n
a
l-to-noi
se
rat
i
o (S
NR).
Co
nsid
eratio
ns i
n
PSD
are: in
put
sign
al frequ
e
n
cy and ph
a
s
e mu
st be simila
r, refe
rence sign
al sho
u
ld be
ju
stified accu
ra
tely,
anticip
ate ph
ase
shift be
cause of
stray
cap
a
cita
nce
and
re
sista
n
ce chan
nel, an
d de
gra
datio
n of
SNR du
e to freque
ncy diffe
ren
c
e bet
wee
n
driving si
gn
al and refe
re
nce
sign
al.
Demo
dulatio
n is accompli
she
d
throu
g
h
several ste
p
s
. First, pha
se differen
c
e betwe
en
digitize
d reference si
gnal
a
nd me
asure
d
sign
al i
s
ide
n
tified. Seco
n
d
, delay the
referen
c
e
si
gn
al
with spe
c
ific
numbe
r from
sam
p
ling
pe
riod a
c
co
rdin
g to pha
se
di
fference valu
e obtain
ed from
pre
c
edi
ng ste
p
to
mat
c
h re
feren
c
e sig
n
a
l’s
p
hase with
mea
s
u
r
ed
sign
al’s pha
se.
La
st,
multiply
the measure
d
sign
al with adju
s
ted referen
c
e
sig
nal in one
sine
wave p
e
riod a
nd th
en
acc
u
mulate the res
u
lts
acc
o
rdingly [9].
Integration of
DDS an
d PSD modul
e into si
ngl
e FPGA hard
w
a
r
e
improve
s
sy
stemati
c
SNR d
an
sim
p
lifies pe
rip
h
e
ral
circuit
s
. For real
-t
ime
pro
c
e
ssi
ng, l
a
rge
amou
nt of data on fro
n
t-
end with
hig
h
-spee
d an
d
relatively si
mple pre-
pro
c
e
ssi
ng a
r
chi
t
ecture
are
suitable for F
P
GA
impleme
n
tation [10].
4. Hard
w
a
re
Design M
e
th
od
As an altern
ative to popular ap
proa
ches to
wa
rd
FPGA prog
ra
mming [11], this wo
rk
r
e
lies
on
h
a
rd
w
a
r
e
-
s
o
ftw
ar
e
c
o
-d
es
ig
n s
t
r
a
teg
y
. Phase dete
c
ti
on alg
o
rithm
i.e. pha
se
shift
demodulation is built
usi
ng
Xilinx FPGA I
P
core.
DDS, multiplier, accumu
l
a
tor,
and CORDIC are
function
ed
a
s
ex
citation-referen
c
e
si
g
nal g
ene
ratio
n
, sig
nal m
u
l
t
iplication,
accumul
a
tion,
and
conve
r
si
on to
polar coo
r
din
a
te in orde
r to con
d
u
c
t trigonomet
ric o
p
e
ration
re
spe
c
tively.
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
De
sign a
nd Sim
u
lation of
Quad
ratu
re Phase Dete
ctio
n in Electri
c
al
.... (Im
a
m
u
l
Muttakin
)
59
Figure 5. Qua
d
ratu
re ph
ase detectio
n
schem
e
Block
diag
ra
m in Figu
re 5
rep
r
e
s
ent
s si
gnal flow
(co
n
tains
pha
se
shift) with
qu
adratu
r
e
demodulation mechani
sm,
where
accumulation
results will be
brought to i
n
verse tangen
t
cal
c
ulatio
n to
obtain p
h
a
s
e output valu
e. Equati
on i
dentity of mu
ltiplication
be
tween
sin
e
with
sine a
nd si
ne
with co
sine a
l
so divisi
on si
ne-co
sine i
s
elabo
rated in
(3).
s
i
n
s
i
n
cos
cos
s
i
n
cos
sin
sin
tan
(3)
Therefore,
ph
ase
can b
e
e
x
trac
ted if th
e
dete
c
ted
sig
nal is
multipli
ed
with refere
nce
si
ne
and co
sin
e
si
gnal,
b
o
th of
whi
c
h
h
a
ve identical
freq
uen
cy. Sum f
r
equ
en
cy
co
mpone
nt i
s
t
hen
eliminated by
accumulatin
g
multiplicati
on re
sul
t. As been kno
w
n
,
accu
mulatio
n
of symmetrical
sign
al with zero offset wil
l
produ
ce
ze
ro mea
n
value so that th
e sum fre
q
u
ency compo
n
ent
sign
al will vanish fro
m
eq
uation. In the end, wi
th division op
eratio
n tangent ph
ase a
ngle will
be
obtaine
d and
then the in
verse i
s
ph
a
s
e value. Th
ose divi
sion
and inve
rse mech
ani
sm
are
con
d
u
c
ted after co
nversio
n
into polar do
main usi
ng CORDIC op
era
t
ion.
Implementati
on of the mechani
sm on Xil
i
nx Syst
em Generator i
s
de
scribe
d in Fig
u
re 6.
Figure 6. Xilinx System Generato
r
core
block
whe
r
ea
s, sig
nal flow is d
e
p
icted in Fig
u
r
e 7 belo
w
.
O
u
t
p
u
t
(p
h
a
s
e
)
1
ar
c
t
a
n
at
a
n
2
Si
n
e
M
u
lt
i
p
lie
r
1
M
u
lt
i
p
lie
r
Co
s
i
n
e
Ac
c
u
m
u
l
a
t
o
r
1
Ac
c
u
m
u
l
a
t
o
r
I
n
p
u
t (s
i
g
n
a
l
)
1
Ou
2
Ou
1
Mu
l
t
1
a
b
a
b
z
-3
Mu
l
t
a
b
a
b
z
-3
Ga
te
w
a
y
Ou
t1
Ou
t
Ga
t
e
w
a
y
Ou
t
Ou
t
G
a
te
w
a
y
In
In
DD
S
Co
m
p
il
e
r
4
.
0
si
n
e
co
s
i
n
e
CO
RDI
C
A
T
A
N
z
-1
0
x
y
ma
g
at
a
n
Ac
cu
m
u
l
a
t
o
r
1
b
+=b
Ac
c
u
m
u
l
a
t
o
r
b
+=b
Sy
s
t
em
Ge
n
e
ra
t
o
r
In
1
1
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TELKOM
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Vol. 13, No. 1, March 2
015 : 55 – 64
60
Figure 7. Qua
d
ratu
re ph
ase detectio
n
si
gnal flow
Synchrono
us sin
e
a
n
d
co
sine
si
gnal
p
r
odu
ce
d
by
DDS IP
core i
m
pleme
n
ted i
n
FPGA
are
directly
use
d
in
digit
a
l dom
ain fo
r de
mod
u
lati
on. Compa
r
e
d
with
conv
entional
anal
og
demod
ulation
,
the method can elimin
ate the
possibility of
frequen
cy mism
atch and p
h
a
se
variation bet
wee
n
signal
s.
Com
putation
pro
c
e
s
s
i
s
condu
cted
in dedi
cated mo
dule
s
(multipl
ier-
accumul
a
tor) and
avoi
ding
data
buffer
so that
digital
demod
ulation
ca
n
be
pe
rfo
r
med
onli
ne i
n
orde
r to
maxi
mize
a
c
qui
siti
on
rate.
Con
s
quently, it
will
intro
d
u
c
e
a
relatively sim
p
le sy
stem
with
better reliability [12].
5. Simulation Resul
t
Hardware-sof
tware co
-sim
ulation
u
s
ing MA
TLAB-Xilinx System Generator all
o
ws to
desi
gn an
d o
b
se
rve the ch
ara
c
teri
stics
of har
d
w
a
r
e; on the other
hand ma
nipul
ate the input
sign
al and p
r
oce
s
s the out
put sign
al by softwa
r
e. Fixed-p
o
int num
ber will b
e
used to maintai
n
con
s
i
s
ten
c
y with pra
c
tical runni
ng p
r
o
c
e
ss in di
gital d
e
vice [13].
5.1. MATLAB Xilinx
S
y
st
em Generator
The devel
op
ment issue
s
i
n
hardware
d
e
si
g
n
usi
ng
MATLAB Xilinx System Generator
comp
ri
se
s: 1) determinin
g
desig
n spe
c
ificatio
n,
2) desig
ning a
system in
Simulink utili
zing
System Gen
e
rato
r blo
c
ks, 3)
simula
ting the de
sign, 4) ge
ne
rating h
a
rd
ware d
e
scri
ption
langu
age
(HDL)
co
de, 5)
impleme
n
ting
HDL co
de in
to target ha
rdwa
re [14]. Step 1 thro
ugh
3
were appli
ed
to foresee sy
stem’s
perfo
rmanc
e and
capability for furthe
r ECVT
developm
ent.
x
x
=
=
Σ
Σ
÷
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
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ISSN:
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930
De
sign a
nd Sim
u
lation of
Quad
ratu
re Phase Dete
ctio
n in Electri
c
al
.... (Im
a
m
u
l
Muttakin
)
61
Figure 8. Implementation of
Xilinx IP core
for quad
rature demod
ulati
o
n
Implementati
on re
sult of Xilinx IP Core
multiplie
r and accum
u
lator for qu
adratu
r
e
demod
ulation
calcul
ation i
s
sho
w
n in Fi
gure 8.
In the system, inp
u
t sine sig
nal
50kHz (cho
sen
operation fre
quen
cy) i
s
ap
plied with
ph
ase
shift
1 ra
dian. Ha
rd
wa
re multiplie
r then multiply th
e
sign
al with e
a
ch
of refere
nce
sine
and
co
sine
sign
a
l
whe
r
e the freque
ncy is
set simila
r to the
input si
gnal.
Each m
u
ltipli
cation
re
sult i
s
b
r
ou
ght int
o
ha
rd
ware a
c
cumulato
r to
be a
c
cumul
a
ted
thus hig
h
fre
quen
cy com
pone
nt will b
e
elimi
nated
and accu
m
u
lation of ph
ase fun
c
tion
will
remai
n
. Trigronomet
ric op
eration
ata
n
2
(two-in
put in
verse tan
gen
t) is applied
usin
g MATL
AB
function. On t
he display, phase value (i
n radia
n
) i
s
shown.
5.2. Sy
stem
Ov
er
v
i
e
w
Overview
of the system f
o
r ph
ase shif
t demodul
ation implem
en
ted on Xilinx System
Gene
rato
r is
sho
w
n a
s
foll
owin
g Figu
re
9.
T
r
ig
o
nom
et
r
i
c
Fu
n
c
ti
o
n
at
a
n
2
Si
n
e
Wa
v
e
2
Si
n
e
Wa
v
e
1
Si
n
e
Wa
v
e
Sc
o
p
e
6
S
c
o
pe3
Sc
o
p
e
1
Mu
l
t
1
a
b
a
b
z
-1
Mu
l
t
a
b
a
b
z
-1
G
a
te
w
a
y
O
u
t3
Ou
t
G
a
te
w
a
y
O
u
t2
Ou
t
G
a
te
w
a
y
O
u
t1
Ou
t
Ga
t
e
w
a
y
O
u
t
Ou
t
G
a
te
w
a
y
In
3
In
G
a
te
w
a
y
In
2
In
G
a
te
w
a
y
In
1
In
G
a
te
w
a
y
In
In
Di
s
p
l
a
y
1.
0
3
3
Ac
c
u
m
u
l
a
t
o
r
1
b
+=
b
Ac
c
u
m
u
l
a
t
o
r
b
+=
b
Sy
s
t
e
m
G
e
ner
at
o
r
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 1, March 2
015 : 55 – 64
62
Figure 9. Qua
d
ratu
re ph
ase detectio
n
system overvi
ew
From the d
e
si
gn, system
specifi
c
ation th
at
can be p
r
o
v
ided is form
ulated in Tabl
e 2.
Table 2. System Specifi
c
at
ion
Opera
t
io
nal Fre
quen
c
y
50kHz
Phase De
tecti
o
n Ran
g
e
0-114.58
o
/ -5
7.2
9
o
~57.29
o
Res=8-bit;
Clk=100MHz;
MAE=0.8529
o
Res=16-bit;
Clk=100MHz;
MAE=0.5794
o
Res=8-bit;
Clk=200MHz;
MAE=3.6494
o
Res=16-bit;
Clk=200MHz;
MAE=3.9960
o
Data Proc.
Rate
1785 data/s
(8Ch)
416 data/s
(16Ch
)
100 data/s
(32Ch
)
Equation
(4
)
and
(5
)
we
re
used
to d
e
ri
ve data
rate
and
mea
n
a
b
so
ulte e
r
ror
(MAE)
r
e
spec
tively,
(4)
∑|
|
(5)
whe
r
e
f
clk
=ha
r
dw
ar
e
c
l
oc
k
;
f
ADC
=
A
DC s
a
mpling
rate;
f
op
=o
peratio
nal freque
ncy;
N
period
=numb
e
r
of signal
perio
d;
n
=m
easure
m
ent cha
nnel;
N
=numbe
r of d
a
ta;
f
i
=theo
re
tical
value;
c
i
=m
ea
sured value.
St
e
p
Si
n
e
W
a
v
e
2
Si
n
e
W
a
v
e
1
Si
n
e
W
a
v
e
Sc
o
p
S
c
o
pe3
S
c
o
pe2
S
c
o
pe1
R
e
i
n
t
e
rp
re
t
1
re
i
n
t
e
r
p
r
e
t
Re
in
t
e
r
p
r
e
t
re
i
n
t
e
r
p
r
e
t
Mu
l
t
1
a
b
a
b
z
-1
Mu
l
t
a
b
a
b
z
-1
Ga
te
w
a
y
Ou
t
7
Ou
t
Ga
te
w
a
y
Ou
t
6
Ou
t
Ga
te
w
a
y
Ou
t
5
Ou
t
Ga
te
w
a
y
Ou
t
4
Ou
t
Ga
te
w
a
y
Ou
t
3
Ou
t
Ga
te
w
a
y
Ou
t
2
Ou
t
Ga
te
w
a
y
Ou
t
1
Ou
t
Ga
te
w
a
y
I
n
4
In
Ga
te
w
a
y
I
n
3
In
Ga
te
w
a
y
I
n
2
In
Ga
te
w
a
y
I
n
1
In
Ga
te
w
a
y
I
n
In
Di
s
p
lay
-0
.
9
6
8
8
DD
S
Com
p
il
e
r
4.
0
si
n
e
co
si
n
e
CO
R
D
I
C
4.
0
x_
i
n
y_
i
n
p
h
a
s
e
_o
ut
Ac
cu
m
u
l
a
t
o
r
1
b
rs
t
+=
b
Ac
cu
m
u
l
a
t
o
r
b
rs
t
+=
b
Sy
st
e
m
G
e
ner
at
o
r
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
De
sign a
nd Sim
u
lation of
Quad
ratu
re Phase Dete
ctio
n in Electri
c
al
.... (Im
a
m
u
l
Muttakin
)
63
Figure 10. Measure
m
ent e
rro
r plot
Measurement
error i
s
plott
ed in Fig
u
re
10 sh
o
w
ing t
he mo
st linea
r re
sult at 1
6
-bit data
and 10
0MHz
clo
ck freque
n
c
y.
6. Conclusio
n
Core p
r
ocessing fo
r calculating ph
ase
and a
m
plit
ude of the
detecte
d si
g
nal wa
s
desi
gned on FPGA platf
o
rm.
Ha
rdware-software co-si
m
ulatio
n
using MATLAB-Xilinx System
Gene
rato
r all
o
ws to desi
g
n and ob
se
rve the char
a
c
teri
stics of hard
w
a
r
e; on
the other h
and
manipul
ate th
e input
sign
al
and p
r
o
c
e
s
s
the output
sig
nal by softwa
r
e. To
perfo
rm hardware
test
with real in
pu
t and output, the desi
gn ne
eds to be do
wnlo
aded o
n
to FPGA and con
n
e
c
ted wi
th
external blo
c
ks.
The o
p
timu
m system
d
e
sig
n
, adju
s
t
ed to 16
-bit
data resolu
tion and
clo
ck
sp
eed
100M
Hz, gives pha
se
det
ection
ra
nge
0-11
4.58
o
(or
±5
7.29
o
)
an
d mea
n
a
b
so
lute erro
r 0.5
8
o
.
Data processing rate
solel
y
at digital signal
sta
ge is approxim
atel
y 1785dat
a/
s (for 8-ch
ann
el),
416d
ata/s (fo
r
16-ch
ann
el), and
100d
ata
/
s (for 32
-cha
nnel).
Ackn
o
w
l
e
dg
ment
Authors wo
ul
d like to tha
n
k re
se
arch
e
r
s
of CTE
C
H Laboratori
e
s, Edwar Te
chnolo
g
y
(www.
c-te
chl
abs.
c
om
) wh
o have helpe
d in experime
n
t. Our app
re
ciation al
so g
oes to revie
w
ers,
committee
a
nd p
aneli
s
ts
in the Inte
rn
ational
Confe
r
en
ce
on El
e
c
tri
c
al En
gin
eerin
g, Com
puter
Scien
c
e and Informatics 2
014 (EECSI 2014
)
for
the
i
r
valua
b
le comment
s
an
d
sugge
stion
s
to
improve thi
s
pape
r.
Referen
ces
[1]
W
a
rsito W
,
Marash
deh
Q, F
an LS. El
ectrical C
a
p
a
cita
nce Vo
lume
T
o
mogr
aph
y.
IE
EE Sensor
s
Journ
a
l
. 20
07; 7(4): 525-
53
5.
[2]
Jian
g P, F
a
n
S, Xi
ong T
,
Hua
ng H. In
vestigat
i
on
on
the Sens
itivit
y D
i
stributi
on in
El
ectrical
Cap
a
citanc
e T
o
mogr
aph
y S
ystem.
T
E
LKOMNIKA Indon
esia
n Journ
a
l
of Electrical
Engi
neer
in
g
.
201
3; 11(1
2
): 7088-
709
3.
[3]
Alali
A. Aut
o
matic S
egm
entatio
n F
r
a
m
e
w
ork
of
Buil
din
g
An
at
omical
Mo
us
e Mo
del
for
Biol
umin
escen
c
e T
o
mograph
y.
T
E
LKOMNIKA Indon
esia
n
Journa
l of El
ectrical En
gin
e
e
rin
g
. 201
3;
11(9): 49
97-
50
04.
[4]
Z
hang H, R
e
n D, Du LM.
A ne
w
im
pro
v
ed d
a
ta
acq
u
isitio
n s
y
ste
m
for electric
al cap
a
cita
nce
to
mo
g
r
ap
hy
.
Advanc
ed Mater
i
als Res
earc
h
. 201
3; 756-
759:
1527-
15
31.
[5]
Z
hang
X, W
ang H.
Digit
al phas
e-sens
itiv
e de
mo
dul
atio
n in
el
ectrical
capacita
n
ce
tomo
gra
p
h
y
system
. 7th W
o
rld C
ongr
ess on Intell
ig
ent C
ontrol
a
nd Auto
mation (W
CIC
A
). 2008: 67
30
-673
3.
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ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 13, No. 1, March 2
015 : 55 – 64
64
[6]
Muttakin I, Yu
suf A, Ro
hma
d
i, W
i
da
da
W
,
T
a
runo W
P
.
Hardware
Des
i
gn f
o
r Quadr
a
ture P
has
e
Detectio
n Alg
o
rith
m in EC
VT
. Proceedin
g
of the 201
4 Internat
io
na
l
Confere
n
ce
on Electric
a
l
Engi
neer
in
g, Computer Sci
e
n
c
e and Info
rm
a
t
ics (EECSI). 2
014: 23
2-2
35.
[7]
Guo-Hu
i W
,
Ji-Yang
D, Ba
o-Jun C. T
he R
e
s
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e
le
metr
y
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odu
lati
on S
y
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K
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esi
an Jou
r
nal of Electric
al Eng
i
ne
eri
n
g
.
2013; 1
1
(5): 2
342-
235
0.
[8]
Jun-Su
o Q. A Algorithm of
F
a
st Digit
al
Phase Mo
du
la
tion Sig
nal
R
e
cog
n
itio
n.
TELKOMNIKA
Indon
esi
an Jou
r
nal of Electric
al Eng
i
ne
eri
n
g
.
2012; 1
0
(8): 2
330-
233
5.
[9]
Z
hou
H,
Xu
L,
Ca
o Z
,
Xu
C.
An
altern
ative
di
gital
multi
p
li
cation
de
mod
u
l
atio
n
meth
od
for e
l
ectrica
l
capac
itanc
e tomogr
aphy
. I
EEE Internati
ona
l Instrume
nt
ation and Measur
ement
T
e
chnol
og
y
Confer
ence (I2
M
T
C
). 2012: 1
204-
120
9.
[10]
Z
hang
X, W
a
ng H, Cu
i Z
,
T
ang L.
A Novel ECT
System B
a
se
d on
F
P
GA and DSP
. Second
Internatio
na
l C
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