TELKOM
NIKA
, Vol.14, No
.4, Dece
mbe
r
2016, pp. 12
92~129
8
ISSN: 1693-6
930,
accredited
A
by DIKTI, De
cree No: 58/DIK
T
I/Kep/2013
DOI
:
10.12928/TELKOMNIKA.v14i4.3230
1292
Re
cei
v
ed
De
cem
ber 9, 20
15; Re
vised
A
ugust 9, 20
16; Accepted
August 22, 2
016
Implementation and Analysis of Reversible logic Based
Arithmetic Logic Unit
Sha
v
eta Tha
k
ral*
1
, Dipali
Bansal
2
, S.K.Chakarv
a
rti
3
1,2
Dep
a
rtme
nt
of
El
ectro
n
i
cs a
nd C
o
mm
un
ic
a
t
ion
En
gi
ne
er
in
g,
F
a
c
u
lt
y of
E
n
g
i
n
e
e
r
i
ng an
d T
e
chno
lo
g
y
,
Ma
na
v Ra
ch
na In
te
rna
t
io
nal
Un
i
v
e
r
si
ty
, F
a
rida
ba
d
,
Ind
i
a
3
EX-M
a
nav Ra
chn
a
Int
e
rn
ati
o
na
l
U
n
iv
ers
i
t
y
, F
a
ri
da
ba
d, Ind
i
a
*C
orre
sp
on
di
n
g
a
u
th
or, e
m
a
i
l
:
shav
eta.fet
@
mriu.
ed
u.i
n
A
b
st
r
a
ct
T
here is a tre
m
e
n
d
ous gr
ow
th in fabric
atio
n fr
om s
m
all
scale i
n
tegr
ati
on (SSI) to gi
ant scal
e
integr
ation (G
SI). It how
ever raises
a qu
es
tion of sust
ain
abil
i
ty of Moor
e'
s law
due t
o
al
most i
n
toler
abl
e
levels
of pow
e
r
consu
m
pti
on.
Researc
hers
have i
n
ve
nted
a lot of met
h
o
d
s to reduc
e p
o
w
e
r consu
m
p
t
ion
and r
e
ce
nt tec
hno
log
i
es
are s
w
itching to r
e
v
e
rsibl
e
l
o
g
i
c. R
e
versi
b
le
lo
gic
has var
i
o
u
s a
p
p
licati
ons
in fi
el
ds
of co
mputer
g
r
aph
ics, optic
a
l
in
for
m
ation
p
r
ocessi
ng, q
u
a
n
tum co
mp
uti
ng, DNA c
o
mputin
g, ultra
low
pow
er CMOS desi
gn an
d co
mmu
n
icati
on.
ALU is cons
id
e
r
ed to be the b
a
sic bu
ild
ing
bl
ock of a CPU in the
computi
ng env
iron
me
nt
a
nd portab
ilit
y i
n
c
o
mputi
ng syst
em hi
ghly
de
mands r
e
versi
b
l
e
lo
gic
base
d
ALU.
Moder
n proc
es
sors usu
a
lly
h
a
ve a w
o
rd
le
ngth of
32 or
64 b
i
ts. Divid
e
and c
o
n
quer
appr
oach
pri
n
c
i
pl
e
cascad
e
s
n n
u
m
b
e
r
of 1
bit
ALU to
i
m
ple
m
ent n
b
i
t AL
U.
Severa
l res
ear
chers
hav
e pr
opos
ed
1-b
i
t A
L
U
desi
gn usi
n
g
various rev
e
rsible l
o
g
i
c g
a
tes. T
h
is pa
per ai
ms at
categor
i
z
i
n
g v
a
rio
u
s w
a
ys of
imple
m
entati
o
n
in
VHD
L
us
in
g Xi
linx
ISE d
e
s
ign
suit
14.2
tool
an
d c
o
mpa
r
ative
ana
lysis of
existi
ng 1 bi
t
ALU d
e
si
gns i
n
ter
m
s of o
p
t
imi
z
at
io
n
metr
ics lik
e p
o
w
e
r consu
m
ptio
n, nu
mb
er
of g
a
tes,
nu
mber of
constant
in
puts
,
nu
mb
er of
gar
bag
e o
u
tputs
a
nd
qua
ntu
m
c
o
st .ALU r
eal
i
z
e
d
us
ing
carry s
a
ve
add
er
bloc
k
is found to b
e
most o
p
timu
m
desi
gn in
ter
m
s
of gate count
and q
u
a
n
tu
m cost.
Ke
y
w
ords
:
Reversible logic, ALU, GSI, Qu
a
n
tum c
o
st, optimi
z
at
io
n metric
s
Copy
right
©
2016 Un
ive
r
sita
s Ah
mad
Dah
l
an
. All rig
h
t
s r
ese
rved
.
1. Introduc
tion
In this p
ape
r it is p
r
opo
sed to
simulat
e
re
sult
s of
variou
s AL
U desi
g
n
s
an
d
give a
comp
arative analysi
s
of desi
g
n
s
in term
s of
various pa
ram
e
ters li
ke po
wer co
nsumpti
on,
numbe
r of g
a
t
es, qua
ntum
co
st, logic
op
eration
s
a
nd
garb
age
outp
u
ts. Main ta
rg
et is to find o
u
t
ALU de
sig
n
with lea
s
t qu
antum
co
st a
nd ide
n
ti
fy whether divide
and
con
que
r approa
ch fit
s
to
ca
scade
n
nu
mber of 1
bit
ALU to
config
ure
n bi
t
ALU. Backgroun
d
on
Reve
rsi
b
l
e
logi
c, vari
o
u
s
reversibl
e
log
i
c gate
s
use
d
in exi
s
ting
ALU d
e
si
gn
s and
brief
de
scription
ab
o
u
t existing A
L
U
desi
g
n
s
are f
u
rthe
r discu
s
sed in
se
ction
1.1 and 1.2.
1.1. Backg
ro
und on Rev
e
rsible Logic
In 1961, Lan
daue
r [1] stated that “am
ount of
energy dissi
pated
for every bit erasure
durin
g a
n
irre
versibl
e
o
peration i
s
given
by KTl
n2 j
oul
es
wh
ere
K is Boltzma
nn’
s
con
s
tant, a
n
d
T
is the
o
perating tem
peratu
r
e”. In
1
973
Bennett [2] p
r
opo
sed
the
solution to
La
n
daue
r
statem
ent
and
sho
w
ed
that KTln2
energy dissi
pation
woul
d
not occu
r, if computatio
n is d
one in
a
reversibl
e
ma
nner
sin
c
e a
m
ount of ene
rgy dissi
pate
d
in a system
depen
ds di
rectly on num
bers
of bits erase
d
duri
ng
com
putat
ion. Cla
ssi
cal g
a
tes li
ke two
input
AND, O
R
, NAND, NOR,
XOR
and XNO
R
a
r
e irreversibl
e
as inp
u
t states can’
t be
uniquely re
constructe
d from output st
ates.
Here two-bit input state is
mappe
d to one-bit out
p
u
t state lead
s to the erasure
of one bit a
nd
con
s
e
que
ntly loss of ene
rg
y. This energ
y
loss ca
n
be
avoided by mappin
g
n bit input states to n
bit output
sta
t
es
so
that in
put state
s
ca
n be
uni
quel
y re
covered f
r
om
output
st
ates
and
un
d
e
r
su
ch
circum
stance
s
, a gat
e is said to b
e
reversib
l
e
. The optimi
z
at
ion metri
cs
of reversible l
o
gic
circuits a
r
e q
uantum cost,
ancill
ary input
, garbag
e out
put etc.
The
qua
ntum
co
st
of a
rev
e
rsi
b
le
gate
i
s
to
tal
num
b
e
r of
1x1 and
2x2 reve
rsibl
e
gate
s
requi
re
d in th
e de
sign. Th
e
quantum
co
sts of all re
versible
1x1, as
well a
s
2x2
g
a
tes, a
r
e ta
ke
n
as on
e. Since every reve
rsible g
a
te co
nsi
s
ts
of vari
ous 1 x 1 o
r
2 x 2 quantu
m
gates a
r
e t
a
ke
n
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Im
plem
entation and Anal
ysis of Reversi
b
le logi
c Based ALU (S
h
a
ve
t
a
T
h
a
k
ra
l
)
1293
from NCV ga
te library co
ntaining combi
nation
s
of NOT, CNO
T a
nd controlled
V and contro
lled
V+ gate
s
, therefo
r
e the q
uantum
co
st of a reve
rsibl
e
gate can b
e
cal
c
ulate
d
by countin
g the
numbe
rs of NOT, Controlle
d-V,
Cont
rolle
d-V+ a
nd CNOT gate
s
.
To achi
eve
reversi
b
ility, It is must to
map
n
bit i
n
put states to bit n output
states
and
sometim
e
s e
v
ery gate output is nor u
s
ed as inp
u
t
to some oth
e
r gates no
r acting as a use
f
ul
desi
r
ed
outp
u
t. These
un
desi
r
ed
or u
n
u
se
d outp
u
ts that are d
e
li
berately o
b
tai
ned to mai
n
tain
reversibility criterion of a reversi
b
le gat
e (or ci
rcuit)
are known as Ga
rbage Outputs. Garbage
outputs fo
r an
y reversi
b
le l
ogic
circuit sh
ould be a
s
lo
w as p
o
ssibl
e
.
To achieve reversi
b
ility,
It is
must
to m
ap n bit input
st
ates to
n bi
t output
states. These
con
s
tant inp
u
ts 0 or 1 which a
r
e deli
berately ap
pl
ied to maintain reversibili
ty criterion of a
reversibl
e
gat
e (or
circuit
)
are
kno
w
n a
s
Ancillary
Inp
u
ts. Ancilla
ry inputs fo
r any
reversible l
o
gic
circuit
sho
u
ld
be
as lo
w a
s
p
o
ssibl
e
. Reversi
b
le l
ogi
c g
a
tes u
s
ed
in exi
s
ting A
L
U
de
sign
s
a
r
e
further di
scu
s
sed.
It is very important to kn
o
w
that out of f
our 1*1 o
n
e
-
qubit gate
s
; only two are reversi
b
le
i.e. trivial gate and n
o
t the
gate. Similarly out
of 256 possibl
e 2*2
two-q
ubit gat
es; only 24
a
r
e
reversibl
e
. There exi
s
t 167772
16 different 3*3 th
ree
-
qubit gate
s
however num
ber of reversi
b
l
e
3*3 g
a
tes i
s
much small
e
r i.e.40
320.
Some p
opul
ar reversibl
e
logic gate
s
that are
use
d
in
prop
osed de
sign
s of ALU are given in
Table 1 wi
t
h
their sp
ecif
ication,
expre
ssi
on, qua
ntu
m
co
st, feature
s
and qua
ntum
implementati
on.
Table 1. Pop
u
lar reversibl
e
logic g
a
tes
use
d
in existi
ng ALU de
sig
n
s
Reversible Lo
gi
c
Gat
e
Specifica
tio
n
Expressio
n
Qua
n
t
u
m C
o
st
Q
u
an
tu
m
Im
p
l
em
e
n
t
a
t
i
o
n
NOT gat
e
1*1
P
A
1
CNOT Gate
2*2
P=A
Q=
A
B
1
Tof
foli/
CCN
OT Gate
3*3
5
1.2. ALU
Bac
k
ground a
n
d
Existing AL
U De
signs
ALU is a dat
a pro
c
e
ssi
ng
unit, which i
s
an impo
rta
n
t part in CPU. Different
kind
s of
comp
uters ha
ve different ALUs. In logica
l operatio
n
s
, there
are
NO
T, OR, AND,
XOR, etc. wh
ile
in arithmeti
c
operation
s
th
ere a
r
e a
ddition, subt
ra
ction, etc. For
gene
rating a
reversibl
e
AL
U,
each of these gene
ral ele
m
ents, a
s
sh
own in Fig
u
re
1, is buildu
p
with the he
lp of reversib
le
logic. The
se
veral su
b-m
o
dule
s
in the d
e
sig
n
are
a
d
d
e
r/Subtra
cto
r
, Multiplier, an
d a logical uni
t.
All the o
perations a
r
e
d
one
sim
u
ltan
eou
sl
y. De
p
endin
g
o
n
t
he
cont
rol
si
gnal, the
need
ed re
sult
is offered at the output.
After a d
e
tail
ed a
nalysi
s
o
f
the vari
ou
s
desi
g
n
s
of AL
U, It ha
s b
e
e
n
con
c
lud
ed t
hat ea
ch
ALU co
uld b
e
divided ba
sed on d
edi
cated desi
gn
and co
ntrol u
n
it with adde
r. In the similar
fashio
n the
s
e
ALUs
ca
n al
so furth
e
r
be
divided into t
w
o
categ
o
rie
s
, name
d
a
s
: Single line
ou
tput
or Multi line o
u
tput. So all the po
ssi
ble ALU de
sig
n
s
category wi
se
are summa
ri
zed in Table 2.
Table 2. Cate
gorie
s of Vari
ous AL
U De
si
gns
Design Structure
/
Number of
Out
p
ut Lines
Single Line Outp
ut
Multi Lines Output
Dedicated Design
Paper [16], [1
7]
Paper [19]
Control Circuit b
a
sed Design
Paper [18]
Not Existing
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 16
93-6
930
TELKOM
NIKA
Vol. 14, No. 4, Dece
mb
er 201
6 : 1292 – 129
8
1294
Figure 1. ALU block
diagram
After an extensive lite
r
at
ure
survey
work
i
s
divided into three cate
go
rie
s
. Brief
descri
p
tion
a
bout existin
g
ALU d
e
si
gn
s
with the
s
e
three
cate
gories a
r
e
given
in this se
cti
on.
Their
simulati
on and
comp
arative analy
s
is i
s
given
in se
ction 2 a
nd co
ncl
u
sio
n
is discu
s
se
d in
se
ction 3.
a) T
y
pe 1: Dedicated De
sign
w
i
th Single Outp
ut
1) Pape
r [16]: Desi
gn of a
Novel Reversib
le ALU u
s
in
g an Enha
nced Ca
rry L
o
o
k
-Ah
e
a
d
Adder.
Here auth
o
rs have propo
sed
a novel
5*5 re
ve
rsib
le logic
gate
popula
r
a
s
MG i.e.
Morri
so
n gate
that is u
s
ed i
n
de
signi
ng o
f
a novel
reve
rsibl
e
AL
U al
ong
with HNG gate [16]. T
h
i
s
desi
gn i
s
veri
fied usi
ng Xili
nx 14 a
s
sho
w
n in Fi
gure
2. Reversibl
e
ALU de
sig
n
ed with M
G
a
n
d
HNG
gate
s
perfo
rms
arit
hmetic ope
rations su
ch
as
a
ddition
and subt
ra
ction
an
d
lo
gi
cal
operation
s
a
s
AND, O
R
,
NAND, NOR,
XOR, a
nd
b
u
ffer. After th
at, the comp
arison
hea
di
ng
towards the
flowing fa
cto
r
s
su
ch a
s
th
e rip
p
le-ca
rry
, carry-sele
ct
, logged
sto
ne
carry-a
h
e
a
d
adde
rs i
s
bei
ng ob
serve
d
. Figure 2 sh
o
w
s h
e
re
with prop
osed met
hodol
ogy.
Figure 2. Rev
e
rsi
b
le AL
U with MG and
HNG
gates
Figure 3. Rev
e
rsi
b
le AL
U b
a
se
d on control
cir
c
uit
2) Pape
r [17]: Desi
gn1 a
n
d
Desi
gn 2: Re
versibl
e
Arith
m
etic Logi
c Unit
Here autho
rs have pro
p
o
s
e
d
two app
ro
a
c
he
s of
ALU
desi
gn i.e. co
ntrol structu
r
e based
reversibl
e
on
e-bit AL
U a
n
d
mult
iplexe
r ba
sed
reve
rsible
one
-bit
ALU
with fu
rther t
w
o type
s.
Type 1
reversible
one
-bit
ALU d
e
si
gni
ng is don
e b
y
using
Pere
s gate, F
e
yn
man G
a
te, a
nd
Fred
kin
gate
and Type
2 reversi
b
le o
n
e
-
bit ALU
de
si
gning i
s
d
o
n
e
by Feynma
n gate, Fred
kin
gate, Pere
s gate, DPG g
a
te and YAG
gate. Cont
rol stru
cture based reve
rsible one
-bit
ALU
desi
gning i
s
done
by combinatio
ns
of Toffoli, Feynman, an
d
Fred
kin
gat
es. It has
b
een
con
c
lu
ded th
at multiplexer based d
e
si
g
n
s of ALU pr
oce
s
s paralle
l. This lead
s to simplicity in
desi
gn and v
e
rificatio
n
, fast in operatio
n but wi
th a limitation of large logi
c width and m
o
re
numbe
r of co
nstant
i
nput
s while
control
stru
cture b
a
sed AL
U
ha
s
been
foun
d t
o
be
compl
e
x to
desi
gn due
to various control
s
a
nd slo
w
in
operatio
n becau
se of
large
r
logi
c depth
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
1693-6
930
Im
plem
entation and Anal
ysis of Reversi
b
le logi
c Based ALU (S
h
a
ve
t
a
T
h
a
k
ra
l
)
1295
simultan
eou
sl
y with benefits of smalle
r logic wi
dth
an
d less numb
e
r
of con
s
tant inputs. Figu
re
4
sho
w
s here with propo
se
d methodol
ogy.
b) T
y
pe 2: Control Circ
uit base
d Single Outpu
t
Paper [18]:
An Arithmetic L
ogic
Unit De
sign Base
d on
Reversibl
e
Lo
gic Gate
s.
Here is thi
s
pape
r, ALU
desi
gn
con
s
i
s
ts of two
main pa
rts i.
e. reversibl
e
function
gene
rato
r as
control unit a
nd reve
rsi
b
le
mode sel
e
cti
on unit. These two part
s
a
r
e ca
scad
ed
by
combi
nation
s
of Toffoli and NOT gate
s
. Arithmetic
an
d logical ope
rations p
e
rfo
r
med by this ALU
are a
ddition,
subtractio
n, inversi
on,
N
O
R, NA
ND,
XOR, XNO
R
,
AND, OR,
Buffer.
Figure 3
sho
w
s here with propo
se
d methodol
ogy.
Figure 4. Multiplexer ba
s
ed r
e
ve
rs
ib
le
one
-
b
it
ALU
Figure 5. Ded
i
cated d
e
si
gn
with Multi output
c) T
y
pe 3: Dedicated De
sign
w
i
th Mu
lti Outpu
t
Paper [19]:
Efficient de
sign
of ALU usin
g reversibl
e
log
i
c gate
s
.
In this
pape
r ALU i
s
reali
z
ed
with t
he
help
of a
ca
rry save
ad
de
r blo
c
k
whi
c
h
are
not
based on
p
r
opag
ation
of
ca
rry bits. This app
ro
a
c
h re
sult
s in
improve
d
of
20% an
d 1
7
%
rega
rdi
ng the
gate count a
nd qu
antum
co
st re
spe
c
ti
vely, while co
mpari
ng
with earlie
r
works
in
reversibl
e
AL
U de
sig
n
s. T
h
is d
e
si
gn h
a
s a
de
dicat
ed unit fo
r t
he logi
cal
an
d the a
r
ithm
etic
operation
s
, which
is a
co
mbination
of
Carry
save
a
dder,
Fred
kin
,
Toffoli an
d
CNOT
reve
rsible
logic gate
s
. B
u
t having
the
multiple o
u
tp
uts, to m
a
ke t
h
is AL
U fun
c
tional m
o
re g
a
t
es n
eed
to b
e
adde
d so th
a
t
it can be im
plemente
d
lo
gically. Fi
gu
re 5 given a
b
o
ve sh
ows h
e
re
with prop
ose
d
methodol
ogy.
2. Simulation Resul
t
s an
d Analy
s
is
All proposed
desi
g
ns are v
e
rified using
Xilinx 14
with simulation resu
lts
shown i
n
Figure
6 to Figure 1
0
.
a) T
y
pe 1: Dedicated De
sign
w
i
th Single Outp
ut
1) Pape
r [16]: Desi
gn of a
Novel Reversib
le ALU u
s
in
g an Enha
nced Ca
rry L
o
o
k
-Ah
e
a
d
Adder.
Function tabl
e of proposed desi
gn as per pap
er [16]
is verified usi
ng Xilinx 14 as shown
in Figure 6.
Figure 6. Rev
e
rsi
b
le AL
U with MG and
HNG gate
s
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2) Pape
r [17]: Desi
gn1 a
n
d
Desi
gn 2: Re
versibl
e
Arith
m
etic Logi
c Unit
Function tabl
es
of proposed design 1 and 2
as per paper [17] are verified using
Xilinx 14
as sho
w
n in
Figure 7 and
Figure 8 re
sp
ectively.
Figure 7. Con
t
rol stru
ctu
r
e
based reve
rsi
b
le
One-bit ALU
Figure 8. Multiplexer ba
s
ed r
e
ve
rs
ib
le
one
-
b
it
ALU
b) T
y
pe 2: Control Circ
uit base
d Single Outpu
t
Paper [18]:
An Arithmetic L
ogic
Unit De
sign Base
d on
Reversibl
e
Lo
gic Gate
s.
The function t
able of
proposed
design
as per pape
r [
18] is verified using Xilinx
as
shown in
Figure 9.
Figure 9. Con
t
rol circuit ba
sed
singl
e ou
tput
ALU
Figure 10. Dedicated de
si
gn with Multi Output
one-bit ALU
c) T
y
pe 3: Dedicated De
sign
w
i
th Mu
lti Outpu
t
Paper [19]:
Efficient de
sign
of ALU usin
g reversibl
e
log
i
c gate
s
.
The fu
nction
t
able
of p
r
opo
sed
de
sig
n
of
ALU
a
s
p
e
r
pape
r [19]
is
verified in
Xili
nx 14
as
sho
w
n a
bove
in Figure 1
0
.
This p
ape
r studied vari
ou
s propo
se
d desi
g
n
s
of ALU. The
s
e
d
e
sig
n
s a
r
e b
a
se
d o
n
reversibl
e
log
i
c gate
s
like
NOT gate, F
e
ynman
gate,
Fred
kin gate
,
Toffoli gate, HNG gate,
MG
gate, Pere
s g
a
te, doubl
e Pere
s gate. Im
plementat
io
n
and verifi
cati
on of the
s
e d
e
sig
n
s i
s
d
o
n
e
usin
g Xilinx 1
4
. After stu
d
y and i
m
plem
e
n
tation of
va
ri
ous availabl
e
de
sign
s fo
r
ALU, they h
a
v
e
been
cl
assifi
ed into
three
cate
go
rie
s
.
Comp
ari
s
o
n
of vario
u
s ALU
de
sign
s i
n
term
s of p
o
we
r
con
s
um
ption
is di
scussed i
n
Table
3. Co
mpari
s
o
n
ba
sed on o
p
timization metri
c
s like
Numb
er
of
gates, Q
uant
um Co
st, L
ogic
Ope
r
ati
ons, G
a
rb
ag
e Output
s, Con
s
tant Inp
u
ts, numb
e
r of
operation
s
a
nd Va
riou
s ty
pes of g
a
tes
use
d
in
de
sig
n
ing
of the
s
e
ALUs i
s
di
scussed
in T
a
b
l
e
4.Comp
arative analysi
s
in term
s
of vario
u
s optimi
z
atio
n metrics
of variou
s p
r
op
osed ALU de
sig
n
is sh
own in Figure 1
1
.
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TELKOM
NIKA
ISSN:
1693-6
930
Im
plem
entation and Anal
ysis of Reversi
b
le logi
c Based ALU (S
h
a
ve
t
a
T
h
a
k
ra
l
)
1297
Table 3. Power co
nsumpti
on of variou
s ALU De
sig
n
s
Power consumpti
on(m
w
) P
a
ramet
e
r
Paper [16]
Paper
[17]D
e
sign1
Paper [17]D
e
sign2
Paper [18]
Paper [19]
Logic
0.19
0.02
0.01
0.16
0.06
Signals 0.47
0.07
0.04
0.36
0.18
IOS
34.36
6.95
4.67
57.99
28.49
Total 35.01
7.04
4.72
58.52
28.73
Table 4. Opti
mization m
e
trics
comp
ari
s
o
n
of various A
L
U de
sig
n
s
ALU DESIGNS/Papers
Paper [16]
Paper
[17]Design1
Paper
[17]Design2
Paper [18]
Paper [19]
No. of Gates
8
9
9
14
5
Quantum Cost
35
41
34
55
24
Logic operations
9
5
4
29
8
Garb
age O/Ps
6
6
9
8
3
Constant I/Ps
2
1
5
8
2
Number of
opera
t
ions
9
5
4
29
8
N bit ALU(Divide &
conquer app
roac
h)
Not possible
Not possible
Not possible
Possible
Not possible
T
y
pe
of Gates U
s
ed
HNG, M
G
,
Fe
y
n
m
an, F
r
edkin
Fe
y
n
m
an,
Fredkin, Toffoli
Fe
y
n
m
an,
Fredkin, Peres
CNOT,
Toffoli
CSA, Toffoli,
Fredkin,
CNOT
Figure 11. Co
mparative an
alys
is
o
f
va
r
i
ou
s
AL
U
de
s
i
gn
s
3. Conclusio
n
This p
ape
r ai
ms at critical
review in te
rms of cate
go
rizin
g
vario
u
s ways of de
signing,
impleme
n
tation an
d com
parative a
nal
ysis of
exi
s
ting 1 bit AL
U de
sig
n
s
u
s
ing
optimiza
t
ion
metrics like
power con
s
u
m
ption, num
ber of gat
e
s
, number of
con
s
tant inputs, numb
e
r
of
garb
age o
u
tp
uts and q
uan
tum co
st usin
g Xilinx
ISE
desi
gn suit 14.2 tool. Divide and
con
q
uer
approa
ch p
r
i
n
cipl
e casca
des
n num
be
r of 1 bit AL
U to imple
m
e
n
t n bit ALU
whi
c
h i
s
late
st in
demand of all advanced processors .It i
s
only pos
sibl
e in paper [18] yet quantum cost obtai
ned
is very high. ALU reali
z
e
d
usin
g ca
rry save adde
r blo
ck in de
sig
n
3 is found to be most opti
m
um
desi
gn i
n
terms of
gate
count, ga
rba
g
e
outp
u
t an
d
qua
ntum
co
st. Optimi
zati
on al
gorith
m
like
ACO
and
p
a
rity preservi
ng fo
r fault
toleran
c
e
a
r
e future p
r
o
s
pe
ctive
wou
l
d prove to
be
signifi
cant in i
m
provin
g perf
o
rma
n
ce of smart ALU for
crypto p
r
o
c
e
s
sor.
Referen
ces
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da
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ilit
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e
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g
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