Inter national J our nal of Electrical and Computer Engineering (IJECE) V ol. 8, No. 1, February 2018, pp. 412 420 ISSN: 2088-8708 412       I ns t it u t e  o f  A d v a nce d  Eng ine e r i ng  a nd  S cie nce   w     w     w       i                       l       c       m     A Unified A ppr oach f or P erf ormance Degradation Analysis fr om T ransistor to Gate Le v el Izhar Hussain, Mar co V acca, F abrizio Riente, and Mariagrazia Graziano Department of Electronics and T elecommunications , Politecnico di T orino, Italy Article Inf o Article history: Recei v ed: Jul 25, 2017 Re vised: No v 9, 2017 Accepted: Dec 1, 2017 K eyw ord: Scaling Process Emer ging T echnologies W eb-based Services Education Fifth k e yw ord ABSTRA CT In this paper , we present an e xtensi v e analysis of the performance de gradation in MOS- FET based circuits. The ph ysical ef fects that we consider are the random dopant fluctua- tion (RDF), the oxide thickness fluctuation (O TF) and the Hot-carri er -Instability (HCI). The w ork that we propose is based on tw o main k e y points: First, the performance de gradation is studie d considering B ULK, Silicon-On-Insulator (SOI) and Double Gate (DG) MOSFET technologies. The analysis considers technology nodes from 45nm t o 11nm. F or the HCI ef- fect we consider also the time-dependent e v olution of the parameters of the circuit. Second, the analysis is performed from transistor le v el to g ate le v el. Models are used to e v aluate the v ariation of transistors k e y para meters, and ho w these v ariation af fects performance at g ate le v el as well.The w ork here presented w as obtained using T AMT AMS W eb, an open and publicly a v ailabl e frame w ork for analysis of circuits based on transistors. The use of T AM- T AMS W eb grea tly increases the v alue of this w ork, gi v en that the analysis can be easily e xtended and impro v ed in both comple xity and depth. Copyright c 2018 Institute of Advanced Engineering and Science . All rights r eserved. Corresponding A uthor: Izhar Hussain Department of Electronics and T elecommunications , Politecnico di T orino, Italy ihussain899@gmail.com 1. INTR ODUCTION The MOSFET transistor has pro v en to be a v ery rob ust de vice. As testified by the ITRS Roadmap [1], its size has been reduced from micrometers to nanometers o v er the course of the last four decades. The e xtraordinary de v elopment of electronics is due mainly to this continuous ph ysical scaling. No w adays commercial de vices emplo ys transistors that ha v e a size of fe w tenth of nanometers [2]. A single chip can house billions of transistors [3]. Scaling at such a f ast pace e v entually leads to increased v ariability and reliability issues, that pose a unique challenge for circuit lifetime estimation [4]. 1.1. State of the art analysis V ariations can be cate gorized into tw o main types, depending on their source of origin; process- induced v ariation and intrinsic fluctuations [5]. Intrinsic v ariability and reliability such as Oxide Thickness Fluctuation (O TF) and Random Dopant Fluctuation (RDF), are induced by char ges and geometrical fluctuations at atomic sc ale le v el. These v ariations and reliability issues are unique to de vice structure and their ef fects may be dif ferent for dif ferent CMOS de vices. On the other hand, process-induced v ariations are caused by defects during silicon f abrication, which may be particular to a process in a foundry . In addition, transistor performance not only depends upon static process v ariations, b ut transistors parameters also start to de grade o v er time. This indi vidual de vice de gradat ion, named aging, af fects the circuit performance metrics o v er a period of time. These ef fects are, as an e xample, Ne g ati v e Bias T emper - ature Instability (NBTI), Hot-carrier -Instability (HCI) and T ime Dependent Dielectric Breakdo wn (TDDB) [6][7][8]. Such performance limiting mechanisms are being in v estig ated since three decades, b ut the y are more pronounced in the nano-scale re gime no w and are ine vitable for design consideration as the equi v alent oxide thickness scales do wn as l o w as 5 Angstrom in the future [9]. These intrinsic v ariations and aging parameters are limited by fundamental J ournal Homepage: http://iaescor e .com/journals/inde x.php/IJECE       I ns t it u t e  o f  A d v a nce d  Eng ine e r i ng  a nd  S cie nce   w     w     w       i                       l       c       m     DOI:  10.11591/ijece.v8i1.pp412-420 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 413 de vice ph ysics, making it one of the ultimate bottleneck for CMOS design process and continual technology scaling. As the de vice size approaches to atomic dimensions,the intrinsic v ariability and reliability considerations ha v e become inte gral part of CMOS circuit design by the technologis ts. The most notable change that these ef fects ha v e on a tran- sistor is a shift in the v alue of threshold v oltage (V th ) and mobility ( ). As a consequence, reliability issues leads to performance de gradation and e v entually to the f ailure of de vices. While the ef fects of v ariations on a single transistor are well kno wn and studied, it is more dif ficult to understand their impact at logic g ate le v el. In [10] a reliability analysis w as performed on a static RAM memory . T ransistor with planar and simpler structures ha v e been e xtensi v ely studied o v er the past decades. Reliability analysis of comple x structures and adv ances de vices has also been presented in literature. F or e xample, the w ork presented in [11] focuses on junctionless Fet transistors, while in [12] authors analyze sub-20 nm asymmetric DG de vices. In [13] Shashi Kant Dar g ar performed de gradation analysis of GaN Based Thin Film T ransistors. Finally , gi v en that man y technologies are currently studied as pos sible MOSFET replacement, reliability analysis has been conducted also on emer ging technologies. F or e xample in [14] authors studies ef fect of de vice v ariables on surf ace potential and threshold v oltage in Double g ate graphene FET (DG-GNRFET). Instead in [15] authors focus on carbon nanotube FETs. 1.2. Moti v ation of the w ork The aim of this paper is to analyze in a coherent w ay the impact of reliability on the transistor’ s performance. P articularly , we are interested to analyze the performance de gradation due to the Oxide Thickness Fluctuation (O TF), Random Dopant Fluctuation (RDF) and Hot-carrier -Instability (HCI). The no v el ty of our approach is that we consider and e v aluate the ef fect of these issues starting from the transistor le v el up to g ate le v el together . The E. Maricau [7] and Y u C ao [4][9] models are used for the Oxide Thi ckness Fluctuation (O TF), Random Dopant Fluctuation (RDF) and Hot-carrier -Instability (HCI), to e v aluate the v ariation of threshold v oltage (V th ) and mobility ( ). The consequent change in the dri v e current (I on ) are e v aluated. The v ariation of V th , and I on has been analyzed considering three dif ferent types of MOSFETs: B ULK, Silicon-On-Insulator (SOI) and Double Gate (DG) considering the t echnology scaling. T echnology nodes from 45nm to 11nm are studied. F or the HCI ef fect [7][9], both the trend with technology scaling and the time-dependent e v olution are studied. A model to esti mate the performance of standard logic g ates, both in terms of timing and dynamic po wer , w as de v eloped. The model tak es into account the v ariation of the parameters of transistors, therefore it is possible to e v aluate the impact of reliability at logic g ate le v el. Using a N AND g ate as a testbench, the v ariation of timing and dynamic po wer considering both the technology scaling and the time dependent analysis (for the HCI ef fect) are carried on. The analysis is repeated for all the three types of transistors. 2. SIMULA TION T OOL Among the performance estimation tools, MAST AR is the best-kno wn [16]. It is used by the International Roadmap for Semiconductors [1] to forecast future transistors perform ance. Unfortunately , MAST AR limits the anal- ysis at the de vice le v el. T o e xplore system le v el parameters, another tool nam ed B A CP A C [17] can be used. It includes a lar ge set of analytical models to estimate and predict the performance of future VLSI circuits. Ho we v er , both these tools present some limitations. The y are restricted to one abstraction le v el, that can be the de vice, the g ate or system le v el. Moreo v er , the y are focused on MOSFET technology and do not consider emer ging de vices. T o o v ercome these limitations and enable the performance estimation of electronic circuits from de vice to system le v el, we de v eloped T AMT AMS (T orino Assessment of Mos T echnology and Adv anced perforMance of System Calculator). T AMT AMS is a web-based tool, presented in [18], that combines the de vice le v el analysis a v ailable in MAST AR with the system le v el analysis pro vided by B A CP A C. T AMT AMS is de v eloped by the VLSI group at Politecnico di T orino and it is constantly e v olving. Currently , it is used as teaching tool in the master le v el course Inte grated System T echnology for the Electronics Engineering Master de gree held at Politecnico di T orino. T AMT AMS includes man y models and technologies. Its fle xibility and modularity eases the e xtension of ne w modules and ne w technologies. At the time of writing, CMOS technology is fully supported. It includes B ULK, SOI and double g ate (DG) de vices. W ithin digital electronic circuits, three abstraction le v el can be identified: i) de vice le v el, ii) g ate le v el, iii) system le v el. The T AMT AMS structure is summarized in Fig. 1. It is b uilt considering this three-layered A Unified Appr oac h for P erformance De gr adation Analysis fr om ... (Izhar Hussain) Evaluation Warning : The document was created with Spire.PDF for Python.
414 ISSN: 2088-8708 Figure 1. T AMT AMS analysis flo w . Three kind of anal y s is are possible: de vice le v el, g ate le v el and system le v el. De vice and system le v el parameters are used according to the kind of in v estig ation selected by the user . Computed results are reported in a te xtual or graphical form. structure. In the lo west le v el of abstraction, de vice le v el models can be found. T o this cate gory belong threshold v oltage, mobility and current models. Implemented models are specific for the selected technology (B ULK, SOI, DG). The ph ysical characteristics of a transistor , such as g ate length, the g ate oxide thickness, etc.., are grouped in the de vice parameters . Mo ving to a higher le v el of abstract ion, a g ate le v el analysis can be e x ecuted. Here N AND/AND, Flip-Flop models are a v ailable. The analysis starts from de vice le v el modules, whose results are used by g ate le v el models. System le v el analysis is base d on a set of t echnology independent parameters. The y can be the total number of tran- sistors, the percentage of memory and logic within a digital circuit. Another important feature is that T AMT AMS automatically solv es and k eep track of all the module dependencies. According to the analysis selected by the user , the dependenc y tree is analyzed and the proper models are solv ed. Computed results are reported in a te xtual or graph- ical form. Thus, data can also be post-processed by using e xternal tools. In addition, T AMT AMS supports parametric analysis, i.e. de vice or system le v el parameters can be v aried to under - stand their impact at dif ferent abstraction le v els. Indeed, this approach has been e xploited in paper to analyze the ef fect of threshold v oltage de gradation with time. 3. TRANSIST OR PERFORMANCE DEGRAD A TION 3.1. Description of Models This w ork focuses on the prediction of performance de gradation as the technology scales do wn, both at transistor le v el as well at circ uit le v el. Predicti v e technology models for reliability a w are transistor to circuit design analysis were considered. The models are scalable with wide range of technologies and process v ariations [7][4][9]. V ariation in threshold v oltage V th and carrier mobility at de vice le v el pro vides the basis for the performance de gra- dation analysis at circuit le v el. In the ne xt sections, static and time-dependent models are described before presenting the obtained results. 3.1.1. Static v ariability model The primary intrinsic v ariations are Random Dopant Fluctuation (RDF) and Oxide Thickness Fluctuation (O TF). The RDF phenomena arises due to v ariation of impurity concentration during ion implantation process. RDF is more pronounced in smaller transistors as the technology scales do wn. Because of lo wer doping concentration, addition or deletion of a fe w im purity atoms can significantly change transistor properties, especially the V th . The ph ysics based model, as stated in [4] is gi v en by: V th ( R D F ) = q C I N V r N ch W dep 3 W L 1 : 2 (1) where W ; L; N ch ; W dep are the channel width, channel length, channel doping and depletion width, res pecti v ely . A more e xplicit e xpression is obtained by e xpanding the W dep term and ignoring other second order terms. Equation 1 IJECE V ol. 8, No. 1, February 2018: 412 420 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 415 becomes: V th ( R D F ) = C 1 q p 3 W L t oxe " ox   2 " S i N ch q ! 1 = 4 (2) where C 1 is a fitting parameter accounting for surf ace pot ential. The other parameters, t oxe ; " S i ; " ox and q are the equi v alent oxide thickness, permitti vity of silicon, permitti vity of the oxide layer , and elementary char ge, respecti v ely . The abo v e equation suggests that RDF induced v ariation is directly proportional to t oxe and N ch 0 : 25 . The O TF phenomena arises due to surf ace roughness between silicon and g ate oxide interf ace at atomistic le v el. As V th is directly proportional to g ate oxide thickness T ox , an y fluctuation in oxide thickness leads to change in V th . This ef fect is e v en more highlighted when the g ate oxide thickness approaches atomic dimensions [4]. The threshold v oltage v ariation due to oxide thickness fluctuation can be e xpressed as: V th ( O T F ) = C 4 p q N ch " S i q " ox p 2 W L H ; (3) where C 4 is the only fitting parameter . H represents the minimum possible magnitude of O TF , that is the height of one silicon atom layer which is equal to 2.71 ˚ A. The correlation length of O TF typically ranges between 1-3nm, as reported in [4]. 3.1.2. T ime-dependent r eliability model As mentioned, man y ef fects can de grade the de vice performance o v er time. In the follo wing, the Hot-Carrier - Instability (HCI) aging mechanism and its corresponding model are described. HCI manifests itself as an increase in the threshold v oltage V th and carrier mobility , especially for the NMOS transistor [9][6][7]. The HCI model is based on the classical Reaction-Dif fusion (R-D) model [6]. HCI mechanism can be ph ysically described as generation of char ges at the S i S iO 2 interf ace. HCI model sho ws po wer la w dependence with time t . As reported in [7][9], analytical model for shift in V th and as a function of stress, operating condition and de vice parameters can be e xpressed as: V th ( H C I ) = A [( V g s V th ) K v ] n x +1 =n x ( n x t L ) 1 1+ n x ; (4) where K v = exp ( E ox E o ) exp ( t q E m )( E a K T ) ; E m = V ds V dsat l ; l = 0 : 2( T ox ) 0 : 33 ( X j ) 0 : 5 ; V dsat = L ef f E sat ( V g s V th ) L ef f E sat + ( V g s V th ) ; E ox = V g s V th T ox ; C ox = " ox T ox ; V t = K T q : The increase i n concentration of interf ace char ge N it also result in increase of mobility . The mobility de gradation is gi v en by: = e f f (1 + N it ) m ; = 5 ; m = 1 : 6 ; (5) Def ault v alues of the technology independent model coef ficients as stated in [7][9] are sho wn in T able 1. T able 1. HCI Model parameters A 1.5e-5 vsat (m/s) 1e5 n x 1.21 t (eV) 3.7 q (C) 1.6e-19 E 0 (V/m) 0.71e8 ( m ) 7.8e-9 (V) 0.95 E a - 0.06 K (J/k) 1.38e-23 where n x , E 0 , E a and A are process parameters, it is the critical electron ener gy for generating an interf ace trap, E m is maximum channel electric field which occurs at the drain end of the channel, l is the pinch of f length, is hot electrons mean free path, E ox is electrical field across oxide, V t is the thermal v oltage at room temperat ure and t is stress time gi v en in seconds [7] [9]. These performance de gradation models ha v e been inte grated in T AMT AMS. A Unified Appr oac h for P erformance De gr adation Analysis fr om ... (Izhar Hussain) Evaluation Warning : The document was created with Spire.PDF for Python.
416 ISSN: 2088-8708 ! " # ! # " $ ! $ " % " & ' ( ) * & ' ( & ) $ & ' ( & $ + & ' ( & $ " & ' ( $ $ & ' ( , - . / & 0 1 2 3 4 5 ' 6 & 7 8 & - . / & 6 5 9 4 : 6 : . ; 7 ' & ; ' & < = > ? & @ 5 A ; B 5 & C B : > ; ' 9 & & D E F G 3 H I @ H E 7 ( J ; ' 5 6 ! " # $ % & ' ( ) * # ! + , - + " ) + , - + " ' + , - " % + , - " $ + , - . / 0 1 + 2 3 4 5 6 7 , 8 + 9 : + / 0 1 + 8 7 ; 6 < 8 < 0 = 9 , + = , + > ? @ + A 7 B = C 7 + > C < D = , ; + + E F @ ? 5 G H A G F 9 - I = , 7 8 ! " # $ % & ' ( ) * " ! # ! + , - " ) + , - + " ' + , - + " % + , - " $ + , - " " + , - . / 0 1 + 2 3 4 5 6 7 , 8 + 9 : + / 0 1 + + 8 7 ; 6 < 8 < 0 = 9 , + = , + > ? + > 7 @ = A 7 + B A < C = , ; + + D E F G 5 H I > H E 9 - J = , 7 8 ! " # $ % & ' ( % & ) * + $ ( ) * + ) $ # ) * + ) # , ) * + ) # & ) * + # # ) * + - . ) / 0 1 2 3 4 * 5 ) 6 7 ) . ) 5 4 8 3 9 5 9 : ; 6 * ) ; * ) < = > ? ) @ 4 A ; B 4 ) C B 9 > ; * 8 ) ) D E F G 2 H I @ H E 6 + J ; * 4 5 ! " # $ % & ' # ! ( ) * ( " + ( ) * ( " ' ( ) * " % ( ) * " $ ( ) * , - ( . / 0 1 2 3 ) 4 ( 5 6 ( - ( 4 3 7 2 8 4 8 9 : 5 ) ( : ) ( ; < = ( > 3 ? : @ 3 ( ; @ 8 A : ) 7 ( ( B C = < 1 D E > D C 5 * F : ) 3 4 ! " # $ % & ! & " & # & $ " ! ' ( ) & % ' ( ) ' & $ ' ( ) ' & # ' ( ) & * ' ( ) & & ' ( ) + , ' - . / 0 1 2 ( 3 ' 4 5 ' , ' 3 2 6 1 7 3 7 8 9 4 ( ' 9 ( ' : ; ' : 2 < 9 = 2 ' > = 7 ? 9 ( 6 ' ' @ A B C 0 D E : D A 4 ) F 9 ( 2 3 ! " # $ % & ! & " & # & $ & % # ' ( ) * + , ( ) * ( + " ( ) * ( " % ( ) * ( " ' ( ) * " " ( ) * - . / ) ( 0 1 2 3 4 5 ) 6 ( / 7 ( . / ) ( 6 5 8 4 9 6 9 : ; / ) ( ; ) ( < = > ? ( @ 5 A ; B 5 ( C B 9 > ; ) 8 ( ( D E . F 3 G H @ G E / * I ; ) 5 6 ! " # $ % & ' ( ) * # ! + , - + " ) + , - + " ' + , - " % + , - " $ + , - . / 0 , + 1 2 3 4 5 6 , 7 + 0 8 + / 0 , + 7 6 9 5 : 7 : ; < 0 , + < , + = > / + ? 6 @ < A 6 + = A : B < , 9 + + C D / > 4 E F ? E D 0 - G < , 6 7 ! " # $ % & ! & " & # & $ " ! ' ( ) & % ' ( ) ' & $ ' ( ) ' & # ' ( ) & * ' ( ) & & ' ( ) + , - ( ' . / 0 1 2 3 ( 4 ' - 5 ' , - ( ' 4 3 6 2 7 4 7 8 9 - ( ' 9 ( ' : ; ' : 3 < 9 = 3 ' > = 7 ? 9 ( 6 ' ' @ A , B 1 C D : C A - ) E 9 ( 3 4 A ) B) C ) D ) E) F ) G ) H ) I ) Figure 2. T rend of V th , and I on de gradation on B ULK, SOI and DG de vice scaling. A) Thresold v oltage, D) Mobility and G) Dri v e current percentage de gradation for B ULK technology . B) Thresold v oltage, E) Mobility and H) Dri v e current percentage de gradation for SOI technology . C) Thresold v oltage, F) Mobility and I) Dri v e current percentage de gradation for DG technology . F or each case, the v ariation considering HCI, O TF and RDF are reported alongside to the combined ef fect of all these contrib utions together . Figure 3. a)First Ro w: HCI induced performance de gradation vs stress time for LOP 20 nm node for 3 dif ferent technologies. A) Threshold v oltage, B) Mobility and C) Dri v e current per centage de gradation. 3. b) Second Ro w: N AND2 g ate time delay and dynamic po wer percentage de gradation as a function of stress time t’ for LOP 20 nm B ULK, SOI and DG technologies. A) Delay v ariation. B) Dynamic po wer v ariation. IJECE V ol. 8, No. 1, February 2018: 412 420 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 417 3.2. Results (De vice le v el) In this section we discuss and analyze the performance de gradation at de vice le v el relating to three dif ferent types of technologies, i.e. B ULK, SOI and DG. The choice of dif ferent technologies not only contrib ute to dif ferent structures b ut also follo w their scaling trend, e.g. the first node of LOP B ULK technology analyzed is 45 nm and last node of LOP DG technology scales do wn to 11 nm. T w o kind of analysis are cons idered: First analysis considers technology scaling across multiple types of transistors and nodes. Second one is a parametric analysis that focuses on one technology node and studies the v ariation in transistor’ s parameters lik e V th , and I on with time. Fig. 2 sho ws the scaling trend for O TF , RDF and HCI induced de gradation for Lo w operating Po wer (LOP) B ULK, SOI and DG transistor technologies. It is to be no t ed that both static and dynamic models are analyzed together , because according to Alam [19] spatial and dynamic v ariations should be considered within the same frame w ork. In Fig. 2, technologies are listed column-wise with B ULK technology in Fig. 2.A-D-G, SOI in Fig. 2.B-E-H and DG in Fig. 2.C-F-I. The shift in V th , and I on are plotted in ro ws with V th in the first ro w , in the second ro w and I on third ro w . All v ariations are sho wn in relati v e units (%) and represent ho w much each quantity ( V th , and I on ) v aries comparing to their nominal v alues. F or each cas e, the v ariation considering HCI, O TF and RDF are reported alongside the combined ef fect of all these contrib utions together . The lar ger picture bring in some interesting observ ations. Relati v e v ariations are maximum for B ULK technology nodes. As e xpected, the scaling trend increases within the frame w ork of same technology for all the three types of de vices. Considering static models, RDF remains the major source of V th , and I on v ariability , as indicated by [4], with maximum V th relati v e increase recorded as 12% for first node , i.e. LOP B ULK 45 nm node (Fig. 2A), and maximum relati v e decrease in and I on recorded as 9% for the last node, i.e. LOP 11nm DG technology node (Fig. 2F and 2I). Considering time-dependent model,it is interesting to note that HCI induced de gradation is lar ger for SOI de vices than DG. The reason is, in DG case the carriers flo w close to the center of the de vice where the potential fluctuations introduced by the trapped char ges are relati v ely small, resulting in a lo wer v ariability compared the SOI de vice where the transport occurs close to the top interf ace and de vice is more af fected by potential fluctuations [20]. Fig. 3.a) depicts the v ariations of V th , and I on at room temperature with increasing time. Fig. 3.a) sho ws HCI induced time-dependent v ariations V th , and I on remains belo w 1% for all the nodes under consideration, for a period of 10 3 stress seconds. It can be seen in Fig. 3.a) that as the de vices are e xposed to longer period of stress time t s , from 10 3 to 10 5 the de gradation becomes more se v ere. Fig. 3.a) sho ws the performance de gradation as function of stress time t s , considering LOP 20 nm as reference node for all the three technologies. B ULK de vices are more af fected as compare to the other tw o. F or B ULK, de gradation in V th is 0.5% at t s = 10 3 , it increases to 2% at t s = 10 4 , and it reaches 6.35% at t s = 10 5 (Fig. 3a.A). Simil arly , maximum de gradation in V th of 6.04% and 4.63% are recorded for SOI and DG technology respecti v ely at t s = 10 5 (Fig. 3a.A). According to Alam [19], time-induced v ariation can be lar ger than the nominal de gradation by more than 34% in 3 years lifetime. It has been observ ed that nominal shift remains near constant throughout dif ferent technologies. This is mainly due to relax ed oxide scaling b ut relati v e magnitude of V th v ariation increases with technology scaling. 4. FR OM DEVICE LEVEL T O GA TE LEVEL After detailed analysis of de gradation of performance metrics at de vice le v el arising from intrinsic fluctuation and char ge trapping, we ha v e observ ed ho w the primary performance parameters lik e V th and are af fected. In the follo wing, we consider their impact at g ate le v el. 4.1. Description of N AND gate model Reliability a w are g ate le v el analysis is interesting in a w ay that N AND g ate is considered as uni v ersal b uilding block for all high le v el CMOS ci rcuits. Since the threshold v oltage directly af fects the delay of a digital g ate, the operating frequenc y of the g ate de grades, which in-turn af fect the dynami c po wer consumption [21]. Mathematically putting: = f ( V th ) ; F r eq uency ; F = 1 = ; D y namic P ow er ; P dy n = f ( F ) : The delay analysis of the N AND g ate is implemented e xploiting the Elmore Delay model [22], considering its easy implementation and optimistic results. Here, the shift in V th is translated into an increase in resistance that af fects the time delay . On the other hand, the dynamic po wer consumption for N AND2 g ate is estimated considering the probabilistic model that can be e xpressed as: D y namic P ow er ; P dy n = 1 2 f C V 2 dd [ W ] ; A Unified Appr oac h for P erformance De gr adation Analysis fr om ... (Izhar Hussain) Evaluation Warning : The document was created with Spire.PDF for Python.
418 ISSN: 2088-8708 ! " # $ % & ! & " & # & $ & % # ' ( ) * + , ( ) * ( + " ( ) * ( " % ( ) * ( " ' ( ) * " " ( ) * - . / 0 1 2 3 4 ( 5 6 5 7 " ( 7 8 ) 9 * : ; ( < = > ? @ ( A B C ( B ; 9 D : ) E ( ( F G H I J K L 7 K G = * M : ) ? N ! " # $ % & ! & " & # & $ & % " ! # ' ( ) * + , ( ) * ( + " ( ) * ( " % ( ) * ( " ' ( ) * " " ( ) * - . / 0 1 2 3 4 ( 5 6 5 7 " ( 7 8 9 : ; ( < = > ( = ? : 9 @ ) A ( ( B C D E F G H 7 G C I * J @ ) 8 K ! " # $ % & ! & " & # " ! ' ( ) ' & % ' ( ) ' & $ ' ( ) & # ' ( ) & * ' ( ) + , - . / 0 1 ' 2 3 2 4 " ' 4 5 6 7 8 ' 9 : ; ' : < 7 6 = ( > ' ' ? @ 0 / A B C 4 B @ D ) E = ( 5 F ! " # $ % & ! & " & # & $ " ! ' ( ) & % ' ( ) ' & $ ' ( ) ' & # ' ( ) & * ' ( ) & & ' ( ) + , - . / 0 ' 1 2 1 . " ' . 3 4 5 6 ' 7 8 9 ' 8 : 5 4 ; ( < ' ' = > ? @ A B C . B > D ) E ; ( 3 F ! " # $ % & ! & " " ! ' ( ) ' & % ' ( ) ' & $ ' ( ) & # ' ( ) & * ' ( ) + , - . / 0 1 ' 2 3 2 4 " ' 4 5 ( 6 ) 7 8 ' 9 : ; < = ' > ? @ ' ' ? 8 6 A 7 ( B ' ' C D 0 / E F G 4 F D : ) H 7 ( < I ! " # $ % & ! & " & # & $ " ! ' ( ) & % ' ( ) ' & $ ' ( ) ' & # ' ( ) & * ' ( ) & & ' ( ) + , - . / 0 ' 1 2 1 . " ' . 3 ( 4 ) 5 6 ' 7 8 9 : ; ' < = > ' ' = 6 4 ? 5 ( @ ' ' A B C D E F G . F B 8 ) H 5 ( : I A ) B) C ) D ) E) F ) Figure 4. N AND2 g ate time delay and dynamic po wer percentage v ariation trend with B ULK, SOI and DG scaling. A) and D) depicts respecti v ely delay and dynamic po wer v ariation for B ULK technology . B) and E) depicts respecti v ely delay and dynamic po wer v ariation for SOI technology . C) and F) depicts respecti v ely delay and dynamic po wer v ariation for DG technology . where is the switching acti vity , f is the frequenc y and C is the total capac itance. In order to get sim plified analysis, tw o assumptions were made: i) The input probability is al w ays considered as 0.5 . ii) The computation of the switching acti vity for e v ery single node is based on a probabilistic model. Further details on the model are not reported for space reasons. Considering reliability de gradation, we assume all other parameters in abo v e equation are unaf fected by shift in V th ; thus P dy n becomes the function of f r eq uency only . The frequenc y change [ F =F ] in a circuit is measured as a direct measure of the de gradation, which is proportional to V th change under HCI [21]. 4.2. Results (Gate le v el) Fig. 4 sho ws de gradation scali n g trend of time delay and dynamic po wer for 2-input N AND g ate. Gate delay increases due to the v ariation, while maximum dynamic po wer decrease accordingly . It is possible to observ e a projection of the results analyzed at de vice le v el. B ULK transistor based N AND g ate is more e xposed to s tatic and dynamic de gradation when compared to the other technologies (see Fig. 4.A and Fig. 4.D). The change in V th directly af fects the time delay in a digital g ate [21], so the ef fect is more monotonic with the trend of V th de gradation scaling plots. Dynamic po wer de gradation trend is similar to the delay , because dynamic po wer depends upon the operating frequenc y which is the in v erse of critical path delay . As at de vice le v el analysis, RDF is contrib uting the major part of total de gradation. In Fig. 4, it is interesting to see that HCI induced de gradation is higher for SOI technology [20], with maximum time delay and dynamic po wer de gradation reported as 5.3 % and 5.11 % res pecti v ely for LOP 18 nm node at stress time t s = 10 3 (Fig. 4B and 4E), as compared to [0.56%, 0.56%] for same LOP 18 nm DG technology (Fig.4C and 4E). This sho ws, ho w the relati v e de gradation is af fected not only due to scaling of transistors, b ut with de vice structure as well [20]. T emporal shift of g ate le v el performance de gradation parameters are sho wn in Fig. 3b .A) (delay) and Fig. 3b .B) (maximum dynamic po wer). De gradation in dynamic po wer is the replication of time delay plots as e xpected, with the former plotted as % decrease. HCI induced de gradation increases with increase in stress time, v alidating the ac- curac y of inte grated modules. Maximum relati v e v ariation estimated for time delay is 5.5 % for 20 nm LOP B ULK technology as compared to 5 and 4.3 % for SOI and DG technologies (Fig. 3.bA). In order to mitig ate the impact of HCI induced v ariations at g ate le v el, V dd tuning and PMOS sizing are the most ef fecti v e techniques. The authors in [23] sho ws that as much as 12 % o v ersizing of g ate is needed across v e years of operations. 5. CONCLUSIONS In this paper we ha v e presented a detailed analysis of MOSFET performance de gradation considering the ef fects of Oxide Thickness Fluctuation (O TF), Random Dopant Fluctuation (RDF) and Hot-carrier -Inst ability (HCI). IJECE V ol. 8, No. 1, February 2018: 412 420 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 419 The w ork here described is unique in its genre because it does a coherent analysis from transistor to circuit le v el. The analysis is carried on considering se v eral types of transistor , considering the technology scaling and for the HCI ef fect, considering also the time e v olution. The w ork w as carried on under the T AMT AMS frame w ork, an open tool designed to help researchers and student to understand technologies based on transistors. As a future w ork, we are e xtending our analysis to system le v el by introducing digital circuits lik e adders, multipliers,FPGA, ALU , FIR filter models and dif ferent other chip layouts in the analysis as well. Secondly , additional ef fects that de grades the performance of transistors, lik e NBTI and electromigration w ould be interesting to analyze. W e are also addi n g more models to the tool and more technologies, e xtending the analysis to emer ging technologies and Post-Si de vices. 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420 ISSN: 2088-8708 [17] D. Sylv ester and K. K eutzer , “System Le v el Performance Modeling with B A CP A C, Berk ele y Adv anced Chip Performance Calculator, pr oc. of IEEE SLIP , pp. 109–114, 1999. [18] F . Riente, I. Hussain, M. R. Roch, and M. V acca, “Understanding cmos technology through tamtams web, IEEE T r ansactions on Emer ging T opics in Computing , v ol. 4, no. 3, pp. 392–403, July 2016. [19] K. Kang, S. P . P ark, K. Ro y , and M. A. Alam, “Estimation of statistical v ariation in temporal nbti de gradation and its impact on lifetime circuit performance, in 2007 IEEE/A CM International Confer ence on Computer -Aided Design , No v 2007, pp. 730–734. [20] B. Cheng, A. R. Bro wn, S. Ro y , and A. Aseno v , “Pbti/nbti-related v ariability in tb-soi and dg mosfets, IEEE Electr on De vice Letter s , v ol. 31, no. 5, pp. 408 410, May 2010. [21] R. Reis, Y . Cao, and G. W irth, Cir cuit Design for Reliability . Springer Ne w Y ork, 2016. [22] R. Gupta, B. T utuianu, and L. T . Pile ggi, “The elmore delay as a bound for rc trees with generalized input signals, IEEE T r ansactions on Computer -Aided Design of Inte gr ated Cir cuits and Systems , v ol. 16, no. 1, pp. 95–104, Jan 1997. [23] R. V attik onda, W . W ang, and Y . Cao, “Modeling and minimization of pmos nbti ef fect for rob ust nanometer design, in 2006 43r d A CM/IEEE Design A utomation Confer ence , July 2006, pp. 1047–1052. BIOGRAPHIES OF A UTHORS Izhar Hussain recei v ed his B.Sc. de gree in Electronics Engineering from UET Pesha w ar , P akistan in 2008. He recei v ed his M.Sc. de gree in Nanotechnologies for ICTs in October 2014 from Po- litecnico di T orino, Ita ly and enrolled in the same uni v ersity as Ph.D. student in No v ember 2014. Since then, he has been acti v e in research acti vities with VLSI group in the Department of Elec- tronics and T elecommunications, Politecnico di T orino. His research area includes Modelling and Characterization of CMOS nano-transistors and emer ging de vices. Mar co V acca Marco V acca recei v ed the Dr .Eng. de gree in electronics engineering from the Po- litecnico di T orino, T urin, Italy , in 2008. In 2013, he got the Ph.D. de gree in electronics and com- munication engineering. He is currently w orking as an Assistant Professor in the Politecnico di T orino. Since 2010, he has been teaching Design of Digital Circuits and Po wer Electronics. His research interests include quantum-dot cellular automata and others be yond-CMOS technologies. F abrizio Riente recei v ed the M.Sc. (Hons.) (magna cum laude) de gree in electronics enginee r - ing from the Polit ecnico di T orino, in 2012, where he is currently pursuing the Ph.D. de gree with the Department of Elec-t ronics and T elecommunications. His primary research interests are de vice modeling, circuit design for nanocomputing, with a particular interest in magnetic QCA, and sil- icon nano wire technologies. His interest also co v ers the de v elopment of ED A tool for emer ging technologies, with the main focus on the ph ysical design. Mariagrazia Graziano recei v ed the Dr .Eng. and the PhD de grees in Electronics Engineering from the Politecnico di T orino, Italy , in 1997 and 2001, respecti v ely . Since 2002, she is a researcher and since 2005, an assistant professor at the Politecnico di T orino. Since 2008, she is adjunct f aculty at the Uni v ersity of Illinois at Chicago and since 2014 she is a Marie-Sk odo wska-Curie Intra-European Fello w at the London Centre for Nanotechnology . Her research interests include design of CMOS and be yond CMOS de vices, circuits and architectures.She is author and coauthor of more than 120 published w orks. She is a Member of the IEEE since 2007. IJECE V ol. 8, No. 1, February 2018: 412 420 Evaluation Warning : The document was created with Spire.PDF for Python.