Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
5, N
o
. 1
,
Febr
u
a
r
y
201
5,
pp
. 55
~63
I
S
SN
: 208
8-8
7
0
8
55
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
An Improved Des
i
gn of
Li
near
Congruential Generator based
on Wordlengths Reduction
Technique into FPGA
Hubbul Wa
lida
i
ny
, Z
u
lfikar
Department o
f
Electrical Engin
e
ering, S
y
iah Kuala University
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Oct 22, 2014
Rev
i
sed
D
ec 12
, 20
14
Accepted Dec 30, 2014
This pap
e
r
exp
o
ses an improv
ed design
of linear
congruen
t
ial g
e
ner
a
tor
(LCG) based on
wordlengths reduction t
echn
i
qu
e into F
P
GA. The cir
c
uit
is
derived
from LCG algorithm pr
oposed b
y
Leh
m
er and th
e previous design.
The wordlength
s
reduction tech
nique has
been
develop
e
d more in order to
simplif
y
further
cir
c
uit. The
p
r
oposed
design
based on
th
e
fact that
in
applications only
specif
ic
input data
wer
e
used. Some nets
connections
between b
l
ocks
of the cir
c
uit ar
e ignor
ed or tru
n
cated. Simulations either
behavior or timing have been do
ne and
the result
s is
sim
ilar to its algorithm
.
Four best Xilinx
chips have
been
chosen to
extra
c
t com
p
arison d
a
ta of sp
ee
d
and occupi
ed ar
ea. F
u
rth
e
r com
p
aris
on of occup
i
ed are
a
in t
e
rm
s
of flip-flop
and full add
e
r h
a
s been
made.In
gener
a
l, th
e pro
posed design ov
ercome th
e
previous published LCG
cir
c
uit.
Keyword:
FPGA
Im
prove
LC
G
Lin
ear C
o
n
g
ruen
tial Generator
Word
leng
th
s red
u
c
tion
Xilin
x
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Hu
b
bul
Wal
i
d
a
i
ny
Depa
rtem
ent of Electrical E
n
gine
ering
,
Syiah
Ku
ala Un
iv
ersity,
Jl Syech
Ab
dur
Rauf
, D
a
r
u
ss
ala
m
,
Banda Aceh, Indonesia.
Em
a
il: h
w
alid
ain
y
@un
s
yiah
.ac.id
1.
INTRODUCTION
The use
of
random
num
bers has bec
o
m
e
habit in
daily activities since long tim
es ago. Right now,
even
a c
h
ea
p
k
i
d’s t
o
y
co
nt
ai
ns a
ra
nd
om
num
ber ci
rcui
t
i
n
side
it. For i
n
stance, i
n
a t
oy that m
i
mic
m
obile
p
hon
e
will ring v
a
riatio
n
typ
e
s of so
und
wh
en
th
e sam
e
b
u
tto
n is
p
r
essed
man
y
ti
m
e
s.
R
a
nd
om
num
bers t
h
e
o
ry
has
bee
n
re
-i
nt
r
o
duce
d
i
n
t
h
e l
a
st
several
de
cades.
Li
near
con
g
r
ue
nt
i
a
l
gene
rat
o
r (
L
C
G
) t
h
at
i
n
t
r
o
duce
d
19
5
4
by
Lehm
er [
1
]
i
s
t
h
e ol
d
e
st
and t
h
e
m
o
st
co
m
m
onl
y
used
p
s
eu
do
rand
o
m
n
u
m
b
e
r
g
e
n
e
rato
r (PNG)
[2
]. Park
an
d
M
iller sug
g
e
sted
go
od
p
a
ram
e
ters for LCG
[3
]. Th
eir
id
ea h
a
s
b
een used
i
n
Matlab
fo
r g
e
n
e
rating
un
ifo
r
m
rand
o
m
nu
m
b
ers un
til n
o
w
[4
].
M
a
ny
ot
her
t
h
eori
es
o
f
ran
d
o
m
num
ber g
e
nerat
o
rs
ha
ve
bee
n
pr
o
p
o
s
e
d
a
n
d
al
so
u
s
ed i
n
m
a
ny
ap
p
lication
s
. B
l
u
m
Blu
m
Sh
ub
,
W
i
ch
m
a
n
n
-
Hill, Co
m
p
le
men
t
ary m
u
ltip
l
y
with
carry,
In
v
e
rsiv
e con
g
ru
en
tial
gene
rator, ISAAC
(ci
phe
r), Lagged
Fibonacci gene
rator, Linear fee
d
ba
ck
s
h
ift
regist
er, Ma
xim
a
l periodic
recip
r
o
cals, M
e
rsenn
e
t
w
ister, Mu
ltip
ly-with
-carry
,
Naor-Rein
g
o
l
d Pseu
dorando
m
Fu
n
c
tio
n, RC4
PRGA,
Wel
l
Equi
di
st
r
i
but
ed L
o
ng
-
p
eri
o
d Li
near
, a
nd
Xo
rs
hi
ft
ar
e som
e
of t
h
e com
m
on and
wel
l
-
k
n
o
w
n
m
e
t
h
o
d
s
[
5
]-[
8
]
.
Har
d
w
a
re
f
o
r
gene
rat
i
n
g
ran
dom
n
u
m
b
er i
s
al
so a
v
ailable
as well as
their algorithm
s
. Hardware
ha
s
been
use
d
si
n
ce 20
08
. LET
ech i
s
t
h
e fas
t
est
am
ong
al
l
har
d
wa
re f
o
r
gene
rat
i
ng r
a
nd
om
num
bers, t
h
i
s
har
d
ware has
b
een devel
o
p
e
d
and
m
a
rketed s
i
nce
200
8 [9
],
[
1
0
]
.
R
e
search
fo
r s
earchi
ng s
u
i
t
a
bl
e al
g
o
ri
t
h
m
s
of
ge
nerat
i
n
g r
a
nd
om
num
bers i
s
wel
l
est
a
bl
i
s
hi
n
g
fi
el
d
u
n
til n
o
w.
Research
ers u
s
e
fi
eld
p
r
o
g
rammab
l
e g
a
te
arra
ys (FPGA) fo
r testin
g th
eir
alg
o
rith
m
s
. Some o
f
go
o
d
desi
g
n
ha
s
bee
n
real
i
zed
i
n
t
o
ha
rd
wa
re
and s
o
ld i
n
to t
h
e m
a
rket [5],
[10].
In
itially, Th
e
alg
o
rith
m
o
f
LCG th
at
h
a
s b
e
en
co
m
b
ined
with
Mon
t
e Carlo
m
e
th
o
d
u
s
ed
for
gene
rat
i
n
g n
o
n
uni
f
o
rm
rand
om
nu
m
b
er i
n
M
a
t
l
a
b [11]
.
Lat
e
r, t
h
e de
v
e
l
opm
ent
has been i
m
pl
em
ent
e
d i
n
FPGA
[12]. In the
pa
per, the inc
r
em
ent factor
(
c
) has been
i
g
no
red
(
c
=0). Later t
h
en, t
h
e techni
que
for
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
5, No
. 1, Feb
r
uar
y
20
1
5
:
5
5
– 63
56
gene
rat
i
n
g ra
n
dom
num
ber
b
a
sed
on
f
u
l
l
L
C
G al
g
o
ri
t
h
m
al
so av
ai
l
a
bl
e
[1
3]
. T
h
e
pape
r ex
p
o
se
d t
h
e
LC
G
circu
it d
e
si
gn
with
ou
t igno
ri
n
g
th
e i
n
crem
en
t fact
o
r
.
We
a
n
alyze that the
technique m
a
y be im
proved further.
In
t
h
is work,
we
d
e
sign
th
e m
o
re efficient circu
it b
y
red
u
c
i
n
g wo
rd
len
g
t
h
s
o
f
so
m
e
in
pu
t data.
Mo
reo
v
e
r t
h
e
tech
n
i
qu
e propo
sed
in [13
]
will p
r
odu
ce sli
g
h
tly d
i
fferen
t
ran
d
o
m
n
u
m
b
e
rs th
an th
e
orig
in
al
LCG
algor
ith
ms.
The rest
of t
h
e pape
ri
s o
r
ga
ni
zed as
fol
l
o
ws. Sect
i
o
n
2
deal
s wi
t
h
t
h
e
o
ry
o
f
LC
G al
go
ri
t
h
m
.
The
desi
g
n
o
f
im
prove
d LC
G ci
rc
ui
t
for F
P
G
A
i
m
pl
em
ent
a
t
i
on and net
s
m
odi
fi
cat
i
ons are e
xpl
ai
ne
d i
n
sec
t
i
on 3
.
The
dee
p
a
n
alysis and im
ple
m
entations are
pre
s
ente
d in
sectio
n
4
.
Fin
a
lly, th
e con
c
lu
si
on
s are su
mmarized
in
sect
i
on 5.
2.
THEORY
2.
1.
L
i
near
C
o
n
g
ruen
ti
al
G
e
nera
tor
There
i
s
a
p
o
pul
a
r
m
e
t
hod
and
m
o
st
used
t
o
gene
rat
e
r
a
nd
om
num
ber cal
l
e
d l
i
n
ea
r
co
ng
r
u
ent
i
a
l
g
e
n
e
rator.
Th
e
id
ea was in
trodu
ced b
y
Leh
m
er acco
r
d
i
ng
t
o
sequ
en
tial form
u
l
a in
(1
) [1
].
m
c
aX
X
n
n
mod
)
(
1
(1
)
Whe
r
e
m
is
m
odu
lu
s
,
a
is
mu
ltip
lier
,
c
is
increment
. P
a
ram
e
ters
a
,
c
and
m
ha
ve t
o
be
c
h
ose
n
carefu
lly in
o
r
d
e
r to
avo
i
d
rep
e
titio
n
of similar n
u
m
b
e
rs before
m
[
6
]-[8
]. Park
& Miller
sugg
ested
a
g
ood
resu
lts will
b
e
o
b
t
ain
e
d
b
y
cho
o
s
i
n
g
c
=0
[3
].
The
m
odu
lu
sm
sh
oul
d be a l
a
rge
pri
m
e i
n
t
e
ger
,
mu
ltip
lier
a will b
e
an
i
n
teg
e
r i
n
th
e
rang
e 2, 3, .
. .
,
m
-1. The cycle length
of
LC
G
will ne
ver e
x
ceed
m
odu
lu
s m
,
but
i
t
ca
n
be m
a
xim
i
zed usi
n
g t
h
ree
f
o
l
l
owi
n
g
co
nd
itio
ns [7
],
[14
]
:
c
is relat
i
v
e
ly p
r
i
m
e to
modul
u
s
m
,
mu
ltip
liera
-1 i
s
a
m
u
l
t
i
p
l
e
of every
di
vi
di
ng
mod
u
lusm
,
mu
ltip
liera
-1
is a
m
u
lt
ip
le o
f
fo
u
r
wh
en
m
odu
lu
sm
is
a
m
u
lti
pl
e of fo
ur.
2.2.
P
a
rame
te
rs in Com
m
on Use
of LCG
Th
e
requ
irem
en
ts m
e
n
tio
n
e
d
in
th
e
p
r
ev
iou
s
sectio
n
are
referred
to Hu
ll-Dob
e
ll th
eo
rem
[1
5
]
. LC
G
are ab
le to
prod
u
c
e th
e p
s
eudo
rand
o
m
n
u
m
b
e
r th
at can
p
a
ss test of random
n
e
ss. Th
e con
d
ition
is sen
s
i
tiv
e in
ch
oo
si
n
g
th
e go
od
p
a
r
a
m
e
ter
s
c, m
, a
n
d
a
.
In
hi
st
o
r
y
,
p
o
o
r c
h
oi
ces ha
d
been l
e
d t
o
t
h
e i
n
e
ffect
i
v
e
real
i
zat
i
ons
or
im
pl
em
ent
a
t
i
ons
o
f
LC
G
i
t
s
el
f. As a
n
e
x
am
pl
e of t
h
e
po
o
r
pa
ram
e
t
e
rs c
hoi
ce i
s
R
A
N
D
U
(see
T
a
bl
e 1
)
, t
h
i
s
m
e
t
h
o
d
was c
o
m
m
onl
y
i
m
p
l
e
m
en
ted
in
th
e early
1
970
an
d cause to
man
y
results t
h
at are c
u
rrently being
questioned.
Ran
d
o
m
n
u
m
b
e
rs resu
lted
b
y
LCG will b
e
m
o
re efficien
twh
e
n
th
e m
o
du
lu
s ap
pro
ach
a v
e
ry h
i
gh
num
bers,
often reach t
h
e m
a
xim
u
m
co
m
puter (m
achine)
ability such as
m
=2
32
or
m
=2
64
. Ta
bl
e 1 l
i
st
s t
h
e
p
a
ram
e
ters o
f
LCGs in
co
mm
o
n
l
y u
s
e, in
clu
d
i
ng
bu
ilt i
n
fun
c
tion
s
such
as
ra
nd(
)
t
h
a
t
u
s
e
d
i
n
r
u
n
t
i
m
e
libraries
of
va
r
i
ous
com
p
ilers
[2]
.
Tabl
e
1.
Param
e
t
e
rs i
n
c
o
m
m
o
n
us
ed
f
o
r
LC
G a
ppl
i
cat
i
o
ns
[2]
Sour
ce
m
(m
ultiplier)
a
(in
c
re
m
e
n
t
)
c
Nu
m
e
ric
a
l Recipes
2
32
1664
525
1013
904
223
Borland C/C++
2
32
2269
547
7
1
glibc (
u
sed by
GC
C)
2
31
1103
515
245
1234
5
ANSI C:
Watco
m
,
Dig
ital Ma
rs, Co
d
e
Wa
rrio
r
,
IB
M Vis
u
alAg
e C/C++
2
31
1103
515
245
1234
5
Bor
l
and Delphi,
Vir
t
ual Pascal
2
32
1347
758
13
1
M
i
cr
osoft Visual/Quick C/C++
2
32
2140
13
(
343FD
16
)
2531
011
(
2
6
9
E
C
3
16
)
Microsof
t Visual
Basic (6 and ea
rlie
r)
2
24
1140
671
485
(
43F
D43FD
16
)
1282
016
3 (
C
39E
C3
16
)
RtlU
niform
fr
o
m
N
a
tive
A
P
I
2
31
−
1
2147
483
629 (7FF
FFFED
16
) 2147
483
587
(7FF
FFFC3
16
)
Apple Car
bonL
ib,
C++11's
m
i
nstd_r
and0
2
31
−
1
1680
7
0
C++11's m
i
nstd_r
and
2
31
−
1
4827
1
0
M
M
I
X by Donald
Knuth
2
64
6364
136
223
846
79
3005
1442
695
040
888
96
3407
Newlib
2
64
6364
136
223
846
79
3005
1
VAX's
MT
H$RA
NDOM
, old ver
s
ions of glibc
2
32
6906
9
1
Java's java.util.Ra
ndo
m
,
glibc [ld]ra
nd48[_r]()
2
48
2521
490
391
7
11
RANDU
2
31
65539
0
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
Im
pr
ove
d
Desi
g
n
of
Li
ne
ar C
o
n
g
r
u
e
n
t
i
a
l
Ge
ner
a
t
o
r
b
a
se
d
on
Wo
rdl
e
ngt
hs …
(
H
u
b
bul
Wal
i
d
ai
ny)
57
3.
LCG CI
RC
UI
T
DESIG
N
3.
1.
Gener
a
l
Ci
rcui
t
of
L
C
G
Fi
gu
re
1
sh
o
w
t
h
e
LC
G
ci
rc
ui
t
p
r
o
p
o
se
d i
n
[
13]
.
Th
e
desi
gne
d
ci
rcui
t
us
ed e
q
ual
w
o
rdl
e
ngt
hs
o
f
n
fo
r c
o
n
n
ect
i
o
n
bet
w
ee
n
bl
oc
k
s
. T
h
e
desi
g
n
e
d
ci
rc
ui
t
co
nsi
s
t
of
(ass
um
ed m
odul
us=
2
n
):
On
e n
x
n
-
b
it
m
u
lt
ip
lier
On
e
n
-
b
it 2
-
to-1
m
u
l
tip
lex
e
r
One n-bi
t
adde
r
3 x
n ena
b
l
e
bu
ffers (B
1
, B
2
, B
3
)
n b
u
ffe
rs (B
4
)
For
cert
a
i
n
ap
pl
i
cat
i
ons,
t
h
e
desi
g
n
m
a
y
be im
pro
v
e
d
f
u
rt
her
.
B
y
usi
n
g
t
h
e sam
e
ci
rcui
t
bl
oc
ks,
w
e
pr
o
pose
d
a
ci
rc
ui
t
f
o
r a
m
o
re
effi
ci
ent
a
r
ea.
Thi
s
desi
g
n
re
qui
res s
o
m
e
assum
p
t
i
ons.
Th
e design
b
a
sed
on
th
e
fact
th
at in
app
licatio
n
on
ly sp
ecific
m
u
ltip
lier an
d
i
n
crem
en
t were used
[2]. He
re as an exam
ple, we
desig
n
an e
ffic
i
ent circuit fo
r
mo
dul
us
of max
i
m
u
m
8
-
b
it.It is assu
m
e
d
th
at th
e
word
leng
th
of
mu
ltip
lier
u
s
e 3
-
b
it an
d
th
e
word
leng
th
of
increme
n
tc
use
2-bi
t
dat
a
. Fi
gu
re 2 sh
o
w
a sl
i
ght
m
odi
fi
cat
i
on
ci
rcui
t
of
t
h
e pre
v
i
o
us desi
g
n
.
Fi
gu
re
1.
Ge
ne
ral
ci
rcui
t
of
l
i
n
ear
co
n
g
r
u
ent
i
al
gene
rat
o
r [
1
3]
Fi
gu
re
2.
Pr
o
p
o
se
d ci
rc
ui
t
de
si
gn
of a m
o
re
efficient a
r
ea
(n=8)
The p
r
op
ose
d
ci
rcui
t
i
n
t
h
e Fi
gu
re 2 i
s
al
so co
nt
r
o
l
l
e
d by
t
w
o si
g
n
al
s
en
abl
e
a
nd
reset
. The
co
n
t
ro
lling
process is equ
a
l to th
e prev
i
o
u
s
desig
n
. In
itially,
sig
n
a
l
reset
ha
ve t
o
be H
I
GH
(
enab
le
=LOW) in
order to clear the store
d
v
a
l
u
es in
th
e
bu
ffer B
4
. Si
gnal
e
n
abl
e
det
e
rm
i
n
e wh
ene
v
er
t
h
e
ope
rat
i
o
n s
h
o
u
l
d be
st
art
e
d. P
r
e-
de
fi
ne
ddat
a
of
se
ed
,
in
c
r
em
en
t
and
mu
ltip
lier
have t
o
be a
v
a
i
l
a
bl
e at
t
h
e i
nput
po
rt
s j
u
st
bef
o
re
si
gnal
enab
le
go
es HI
GH
(
res
e
t
m
u
st be LOW). Afte
rthat,
each tim
e
s the
clock
goes
HIGH, a random
num
ber
i
s
pr
o
duce
d
.
Fi
gu
re
3
vi
ews
t
h
e ci
rcui
t
co
nfigu
r
ation
o
f
th
e two con
t
ro
lsignals.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
5, No
. 1, Feb
r
uar
y
20
1
5
:
5
5
– 63
58
Fi
gu
re
3.
Si
g
n
a
l
cont
rol
s
o
f
t
h
e desi
gne
d LC
G ci
rc
ui
t
[
13]
In practice, th
e propo
sed circu
it will also
red
u
c
e
nu
m
b
er of n
e
t
conn
ection
s
b
e
tween
CE
1
, CE
2
and
bu
ffer
s
.
3.
2.
W
o
rdl
e
n
g
th
s Reduc
ti
o
n
Th
e circu
it of
Fig
u
re
2
u
s
ed
eq
u
a
l
wo
rd
leng
th
s ev
erywh
e
re. Th
erefo
r
e, th
e m
u
ltip
lier b
l
o
c
k
h
a
v
e
to
be im
pl
em
ent
e
d wi
t
h
an
8x
8
-
bi
t
ci
rcui
t
(as
s
um
ed n=
8)
. Ho
we
ver
,
t
h
e pr
o
pose
d
de
si
gn
req
u
i
r
es s
m
al
l
e
r
circu
it. Fi
g
u
re
4
sh
ows th
e
n
e
t co
nn
ection
s
co
nfigu
r
ation
of th
e m
u
ltip
lier b
l
o
c
k
.
Fi
gu
re
4.
Pr
o
p
o
se
d w
o
rdl
e
ngt
hs
red
u
ct
i
o
n i
n
m
u
l
t
i
p
l
i
e
r’s
bl
ock
Based
o
n
arithmetic ru
les and
to
red
u
ce area [16
]
, th
e mu
ltip
licatio
n
of B
4
(8
b
it) and
B
1
(3
b
it)
wou
l
d requ
ire
1
0
b
it at t
h
e
ou
tpu
t
.
In th
e
desig
n
,
we
sim
p
ly truncate
d
(disconnect
ed) t
h
e twoh
igh
e
r
n
e
ts
o
f
X(8
)
and
X(9
)
. Si
m
ilarly, we can
do
t
h
e same th
ing
to
the nets o
f
t
h
e add
e
r.
Ag
ai
n
,
b
a
sed o
n
arith
m
e
tic
ru
les
an
d to redu
ce
area
[15
]
, t
h
e a
d
d
ition
o
f
X (8
b
it)
and
B
2
(2
b
it)
wou
l
d requ
ire
9 b
it at t
h
e ou
tpu
t
. B
u
t, i
n
t
h
is
case only one
net (M
(8)) disc
onnect
ed as s
h
own i
n
the
Figure
5.
Fi
gu
re
5.
Pr
o
p
o
se
d w
o
rdl
e
ngt
hs
red
u
ct
i
o
n i
n
ad
der
’
s
bl
oc
k
4.
SIM
U
LATI
O
N
AN
D CO
M
P
AR
ISO
N
S
In
or
de
r t
o
e
v
al
uat
e
w
h
et
he
r t
h
e
desi
g
n
wo
rk
s pr
o
p
erl
y
,
we
sim
u
l
a
t
e
t
h
e pr
op
ose
d
ci
rc
ui
t
i
n
Fi
g
u
re
2
.
B
o
t
h
be
ha
vi
o
r
and t
i
m
i
ng si
m
u
l
a
t
i
on ha
ve
been
do
ne
usi
ng
Xi
l
i
nx
ISE
Desi
g
n
Sui
t
e
14
.2
.S
om
e impo
rt
ant
i
n
f
o
rm
at
i
on of
sy
nt
hesi
s
resu
l
t
i
s
present
e
d.
The c
o
m
p
ari
s
on t
o
t
h
e
p
r
evi
ous
desi
gn
o
f
area an
d s
p
ee
d
hav
e
b
een don
e to sev
e
ral
Xilin
x’s ch
ips.
Th
e
im
p
l
e
m
en
tatio
n
s
h
a
v
e
b
een d
o
n
e
u
s
in
g
th
ree word
leng
th
s
8-b
it,
16
-b
it,
and
3
1
-b
it.
Th
e
word
leng
th
s fo
r
see
d
a
nd
o
u
t
p
ut
are e
q
u
a
l
t
o
wo
rdl
e
n
g
t
h
s
desi
g
n
.
M
eanw
h
i
l
e
, so
m
e
i
nput
us
e sm
al
l
e
r
word
leng
th
s
wh
ich
are m
u
ltip
lier 3
-
b
it, i
n
cremen
t 2
-
b
it.
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISS
N
:
2088-8708
An
Im
pr
ove
d
Desi
g
n
of
Li
ne
ar C
o
n
g
r
u
e
n
t
i
a
l
Ge
ner
a
t
o
r
b
a
se
d
on
Wo
rdl
e
ngt
hs …
(
H
u
b
bul
Wal
i
d
ai
ny)
59
4.
1.
B
e
h
avi
or Si
mul
a
ti
on
Fi
gu
re
6 sh
o
w
s i
n
p
u
t
dat
a
and
res
u
l
t
s
o
f
be
ha
vi
or
si
m
u
l
a
t
i
on usi
n
g
m
o
dul
usm
= 2
8
,
see
d
= 7,
mu
ltip
lier a
= 3
an
d
in
c
r
em
en
t c
= 1. It can
be seen t
h
at the result nu
m
b
ers are ra
ndom
starting from
7
and all
num
bers a
r
e s
m
al
l
e
r t
h
an
2
8
.
Fi
gu
res 7 a
nd
8 sh
ow
be
havi
or si
m
u
l
a
t
i
on resul
t
s
of
m
odulu
s
m
= 2
16
and
m
= 2
31
, respe
c
tively. The
sim
u
lations als
o
produce
numbers
which ne
ver e
x
ceed the
m
odu
lu
s
.
Fi
gu
re
7.
Si
m
u
l
a
t
i
on be
ha
vi
o
r
res
u
l
t
o
f
pr
op
o
s
ed
desi
g
n
usi
n
g
m
=2
16
,
see
d
=7
,
a
=3
,
c
=1
Fi
gu
re
8.
Si
m
u
l
a
t
i
on be
ha
vi
o
r
res
u
l
t
o
f
pr
op
o
s
ed
desi
g
n
usi
n
g
m
=2
31
,
see
d
=7
,
a
=3
,
c
=1
4.
2.
S
y
nt
hesi
s
Resul
t
s
Som
e
im
port
a
nt
dat
a
a
f
t
e
r s
y
nt
hesi
s st
ep
of t
h
e
pr
op
ose
d
desi
g
n
ci
rc
u
i
t
usi
n
g
m
o
dul
usm
=2
8
in
t
o
Xilin
x
Zynq
chip
are:
HDL Synthesis Report
Macro Statistics
# Multipliers : 1
8x3-bit multiplier : 1
# Adders/Subtractors : 1
11-bit adder : 1
# Registers : 4
2-bit register : 1
3-bit register : 1
8-bit register : 2
# Multiplexers : 1
8-bit 2-to-1 multiplexer : 1
===========================================
Advanced HDL Synthesis Report
Macro Statistics MACs : 1
8x3-to-8-bit MAC : 1
# Registers : 19
Flip-Flops : 19
# Multiplexers : 1
8-bit 2-to-1 multiplexer : 1
Device utilization summary:
Selected Device : 7z010clg400-3
Slice Logic Utilization:
Number of Slice Registers: 19 out of 35200 0%
Number of Slice LUTs: 30 out of 17600 0%
Number used as Logic: 30 out of 17600 0%
Slice Logic Distribution:
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
5, No
. 1, Feb
r
uar
y
20
1
5
:
5
5
– 63
60
Number of LUT Flip Flop pairs used:40
Number with an unused Flip Flop: 21 out of4052%
Number with an unused LUT: 10 out of 40 25%
Number of fully used LUT-FF pairs:9 out of 40 22%
Number of unique control sets: 3
IO Utilization:
Number of IOs: 24
Number of bonded IOBs: 21 out of 10021%
Specific Feature Utilization:
Number of BUFG/BUFGCTRLs: 1 out of 323%
Timing Summary:
---------------
Speed Grade: -3
Minimum period: 2.436ns (Maximum Frequency: 410.526MHz)
Minimum input arrival time before clock: 0.892ns
Maximum output required time after clock: 0.511ns
Maximum combinational path delay: No path found
From
HDL
sy
nt
hesi
s
rep
o
r
t
,
t
h
e p
r
o
p
o
se
d d
e
si
gn ci
rc
u
it req
u
i
res an
8x3
-b
it m
u
lt
ip
lier, 1
1
-b
it ad
der,
t
w
o
8-
bi
t
regi
s
t
er, o
n
e 3
-
bi
t
r
e
gi
st
er,
one
2-
bi
t
regi
st
er a
n
d 8
-
bi
t
2
-
t
o
-1
m
u
lt
i
p
l
e
xer. I
n
t
e
r
m
s of sl
i
ce l
ogi
c
u
tilizatio
n
,
th
e
d
e
sign
o
c
cu
p
i
ed
1
9
slice reg
i
sters and
30
slice LUTs. Th
e
distrib
u
tion
o
f
slice lo
g
i
c fro
m
to
tal
am
ount
of 4
0
are
9 f
o
r ful
l
y
use
d
LU
T-F
F
pai
r
s, 1
0
t
o
u
n
u
se
d
LU
T
an
d
21
f
o
r u
nus
ed
fl
i
p
-
f
l
o
p.
T
h
e ci
rcui
t
al
so
re
q
u
i
r
es 3 uni
que
co
nt
r
o
l
set
s
.
The m
a
xim
u
m
fre
que
ncy
of t
h
e ci
rc
ui
t
l
i
m
ited t
o
a
r
o
u
nd
4
1
0
.
5
2
M
H
z w
h
en i
t
i
s
i
m
pl
em
ent
e
d i
n
t
o
Zy
nq
. T
h
e m
i
ni
m
u
m
i
nput
a
rri
val
t
i
m
e
bef
o
re
cl
oc
k i
s
0
.
89
2
ns
. T
h
i
s
m
eans t
h
e
dat
a
sh
o
u
l
d
be
a
v
ai
l
a
bl
e
(
a
rr
iv
e) at input p
o
r
t
b
e
fo
r
e
that ti
m
e
. Th
e max
i
m
u
m
o
u
t
pu
t r
e
q
u
i
r
e
d
tim
e af
ter
clock is 0.51
1 n
s
.
4.
3.
T
i
mi
ng S
i
mul
a
ti
o
n
Fi
gu
re 9 s
h
ow
s
a cl
ose vi
ew
o
f
t
i
m
i
ng sim
u
l
a
t
i
on res
u
l
t
.
The
fi
gu
re s
h
o
w
t
r
ansi
t
i
on
bet
w
e
e
n 2
0
2
an
d
9
5
. Th
ere are so
m
e
g
litch
e
s ap
p
e
ars
b
ecau
s
e o
f
t
h
e tim
e fro
m clo
c
k
edg
e
t
o
p
a
d
s
v
a
ries.
Th
e
v
a
riation
v
a
lu
es
are
ra
n
g
i
n
g fr
o
m
8.39
0 ns
t
o
8.
52
7 ns (
post
-
PAR
st
at
i
c
t
i
m
i
ng re
po
rt
).
Fig
u
re
9
.
A close loo
k
of tim
i
n
g sim
u
latio
n
post-PAR static timing report
Clock Clock to Pad
------------+-----------------+------------+-----------------+------------+------------------+--------+
|Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
------------+-----------------+------------+-----------------+------------+------------------+--------+
O<0> | 8.390(R)| SLOW | 4.033(R)| FAST |Clock_BUFGP | 0.000|
O<1> | 8.391(R)| SLOW | 4.035(R)| FAST |Clock_BUFGP | 0.000|
O<2> | 8.404(R)| SLOW | 4.046(R)| FAST |Clock_BUFGP | 0.000|
O<3> | 8.440(R)| SLOW | 4.071(R)| FAST |Clock_BUFGP | 0.000|
O<4> | 8.397(R)| SLOW | 4.037(R)| FAST |Clock_BUFGP | 0.000|
O<5> | 8.422(R)| SLOW | 4.049(R)| FAST |Clock_BUFGP | 0.000|
O<6> | 8.425(R)| SLOW | 4.052(R)| FAST |Clock_BUFGP | 0.000|
O<7> | 8.527(R)| SLOW | 4.155(R)| FAST |Clock_BUFGP | 0.000|
------------+-----------------+------------+-----------------+------------+------------------+--------+
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
Im
pr
ove
d
Desi
g
n
of
Li
ne
ar C
o
n
g
r
u
e
n
t
i
a
l
Ge
ner
a
t
o
r
b
a
se
d
on
Wo
rdl
e
ngt
hs …
(
H
u
b
bul
Wal
i
d
ai
ny)
61
4.
4.
C
o
mp
ari
s
ons
Fou
r
Xilin
x chip
s h
a
v
e
b
e
en
ch
osen
fo
r area and
sp
eed co
m
p
ariso
n
b
e
t
w
een th
e
p
r
opo
sed
d
e
sign
ci
rcui
t
and t
h
e
previ
o
us o
n
e.
Tabl
e 2 vi
e
w
s
c
om
pari
son
of
occu
pi
ed a
r
ea of
m
odu
lu
s m
=2
8
(8
b
it),
m
=2
16
(16
b
it) an
d
m
=2
31
(
3
1
bi
t
)
o
v
er
Vi
rt
ex
7,
S
p
art
a
n
6,
Ki
nt
e
x
7 a
n
d Zy
nq
chi
p
s.
Table
2.
Occ
u
pied area
com
p
arison am
ong Xilinx chi
p
s
Chips
Area Occupies
8 bit
(
S
lic
es/LUTs)
16 bit
(
S
lic
es/LUTs)
31 bit
(
S
lic
es/LUTs)
[
1
3
]
P
r
oposed
[
1
3
]
P
r
oposed
[
1
3
]
P
r
oposed
Vir
t
ex
7
16/10
19/30
32/18
36/62
92/63
66/12
2
Spar
tan 6
16/10
19/30
32/18
33/19
92/63
67/12
2
Kintex 7
16/10
19/30
32/18
35/62
92/63
65/12
2
Z
y
nq 16/10
19/30
32/18
35/62
92/63
65/12
2
Based on synthesis report, for
m
=2
8
, t
h
e
req
u
i
red area (
bot
h sl
i
ces and LUT
s
) of t
h
e
pr
op
o
s
ed desi
g
n
is m
o
re th
an the prev
i
o
us
d
e
si
g
n
. Th
is is sligh
tly d
i
fferen
t
fo
r
m
=2
16
, t
h
e
num
b
er of
slices
is ab
ou
t three
ti
m
e
s
and t
h
e n
u
m
b
er o
f
LUT
s
i
s
al
m
o
st
equal
.
When t
h
e p
r
o
p
o
s
e
d desi
gn i
s
i
m
pl
em
ent
e
d usi
n
g
m
=2
31
, the
num
b
er
o
f
slices is less, ev
en
t
h
oug
h th
e
n
u
m
b
e
r
o
f
LU
Ts is still
mo
re. Tab
l
e 2 sho
w
s th
is
ph
enomen
a.
Tabl
e
3
vi
ews
t
h
e s
p
eed
com
p
ari
s
on
o
f
t
h
e
pr
o
pose
d
desi
g
n
a
n
d
t
h
e
p
r
evi
ous
one
. It
c
a
n
be see
n
t
h
at
t
h
e p
r
op
ose
d
desi
g
n
i
s
fast
e
r
. T
h
e m
a
xi
m
u
m
freq
u
en
cy
t
h
at
can
be
re
ached
va
ri
es
f
r
om
15
4 M
H
z
t
o
41
1
MHz.
As the
wordle
ngths i
n
creases, t
h
e m
a
xim
u
m
freque
nc
y d
e
creases.
Sp
artan
6
is the slo
w
est ch
ip, Kin
t
ex
7
an
d Z
ynq
ar
e th
e
b
e
s
t
ch
o
i
ce
.
Table
3. Ma
xi
m
u
m
freque
nc
y com
p
arison a
m
ong Xilinxchips
Chips
M
a
xim
u
m
Frequency
(M
Hz)
8 bit
16 bit
31 bit
[
1
3
]
P
r
oposed
[
1
3
]
P
r
oposed
[
1
3
]
P
r
oposed
Vir
t
ex
7
270
376
270
361
139
337
Spar
tan 6
154
248
154
158
73
209
Kintex
7
309
411
270
397
158
369
Z
y
nq
272
411
272
397
140
369
In
or
de
r t
o
m
a
ke a m
o
re det
a
i
l
com
p
ari
s
on
, t
h
e ar
ea
of the de
signed ci
rc
ui
t
an
d t
h
e
p
r
evi
ous
o
n
e
arere
-
im
ple
m
e
n
ted,a
n
alyzed andwe
pu
t
so
m
e
cal
cul
a
t
i
ons of t
h
e sy
nt
h
e
si
s resul
t
s
of
t
h
e pr
o
pose
d
a
nd t
h
e
pre
v
i
o
us m
e
t
h
ods
. Tabl
e 4 u
p
t
o
Tabl
e 9 d
e
scri
be m
o
re abo
u
t
area com
p
ari
s
on
. The a
r
ea i
s
represe
n
t
e
d i
n
t
e
rm
s of use
d
fl
i
p
-fl
op
an
d
f
u
l
l
ad
der
.
From
Tabl
es
4
and
5,
t
h
e
num
bers
o
f
fl
i
p
-fl
i
p
and
ad
der
o
f
t
h
e p
r
op
ose
d
de
si
gn i
s
a
b
out
a
hal
f
of t
h
e
pre
v
i
o
us
one
. The p
r
o
p
o
se
d desi
g
n
bec
o
m
e
m
o
re and m
o
re ef
fi
ci
ent
f
o
r
hi
g
h
er m
odul
us as can
b
e
see
n
i
n
Tabl
es 6
a
n
d 7 fo
r
m
=2
16
a
n
d Ta
bl
es
8 a
n
d
9
fo
r
m
=2
31
.
Tabl
e
4. C
a
l
c
ul
at
i
on
of
area
b
a
sed
o
n
sy
nt
he
si
s res
u
l
t
s
f
o
r
m
odu
lu
s
8
bi
t
[
13]
Cir
c
uits
Bit Size
Counts
Flip-
F
lops
Full Adder
s
Multipliers
8x8-bit
1
-
64
Adder
s
16-
bit
1
-
16
Register
s 8-
bit
4
32
-
Total 32
80
Tabl
e
5. C
a
l
c
ul
at
i
on
of
area
b
a
sed
o
n
sy
nt
he
si
s res
u
l
t
s
f
o
r
m
odu
lu
s
8
bi
t
(
p
r
o
pose
d
desi
g
n
)
Cir
c
uits
Bit Size
Counts
Flip-
F
lops
Full Adder
s
Multipliers
8x3-bit
1
-
24
Adder
s
11-
bit
1
-
11
Register
s 8-
bit
2
16
-
3-
bit 1
3
-
2-
bit 1
2
-
Total 21
35
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
5, No
. 1, Feb
r
uar
y
20
1
5
:
5
5
– 63
62
Tabl
e
6. C
a
l
c
ul
at
i
on
of
area
b
a
sed
o
n
sy
nt
he
si
s res
u
l
t
s
f
o
r
m
odu
lu
s
1
6
bi
t
[
13]
Cir
c
uits
Bit Size
Counts
Flip-
F
lops
Full Adder
s
Multipliers
16x1
6-bit
1
256
Adder
s
32-
bit
1
-
32
Register
s 16-
bit
4
64
T
o
tal 64
288
Tabl
e
7. C
a
l
c
ul
at
i
on
of
area
b
a
sed
o
n
sy
nt
he
si
s res
u
l
t
s
f
o
r
m
odu
lu
s
1
6
bi
t
(
p
r
o
p
o
se
d desi
gn
)
Cir
c
uits
Bit Size
Counts
Flip-
F
lops
Full Adder
s
Multipliers
17x3-bit
1
-
51
Adder
s
20-
bit
1
-
20
Register
s 17-
bit
1
17
-
16-
bit
1
16
-
3-
bit 1
3
-
2-
bit 1
2
-
Total 38
71
Tabl
e
8. C
a
l
c
ul
at
i
on
of
area
b
a
sed
o
n
sy
nt
he
si
s res
u
l
t
s
f
o
r
m
odu
lu
s
3
1
bi
t
[
13]
Cir
c
uits
Bit Size
Counts
Flip-
F
lops
Full Adder
s
Multipliers
31x3
1-bit
1
-
961
Adder
s
32-
bit
1
-
32
Register
s 31-
bit
4
124
T
o
tal 124
983
Tabl
e
9. C
a
l
c
ul
at
i
on
of
area
b
a
sed
o
n
sy
nt
he
si
s res
u
l
t
s
f
o
r
m
odu
lu
s
3
1
bi
t
(
p
r
o
p
o
se
d desi
gn
)
Cir
c
uits
Bit Size
Counts
Flip-
F
lops
Full Adder
s
Multipliers
31x3-bit
1
-
93
Adder
s
32-
bit
1
-
32
Register
s 31-
bit
2
64
-
3-
bit 1
3
-
2-
bit 1
2
-
T
o
tal 69
125
The p
r
op
ose
d
desi
g
n
i
s
de
ri
v
a
t
e
d fr
om
t
h
e
habi
t
o
f
i
n
put
dat
a
, i
t
m
i
ght
be va
ri
ed
base
d o
n
LC
G
application. For sure,
one thing that ca
n be l
earne
d fro
m
th
e design is the
r
e are s
p
ace to
reduce
o
cc
upie
d
area
and im
prove
the spee
d
what
ever ap
p
licatio
n it is.
5.
CO
NCL
USI
O
NS
An i
m
pro
v
e
d
desi
g
n
a
nd i
m
pl
em
ent
a
t
i
on of l
i
n
ea
r c
o
n
g
r
ue
nt
i
a
l
gene
r
a
t
o
r i
n
t
o
FP
G
A
ha
ve
been
done
succes
sfully. It is as
sumed that
the
designe
d ci
rcuit
is use
d
for sp
ecific applications
.
In ge
ne
ra
l, the
pr
o
pose
d
desi
g
n
ci
rc
ui
t
i
s
far
fast
er a
nd l
e
ss
i
n
use
d
fl
i
p
-
f
l
o
p an
d
ful
l
a
dde
r. I
n
t
e
rm
of sl
i
ces an
d L
U
Ts
base
d
on
FP
GA
sy
nt
hesi
s, t
h
e p
r
op
ose
d
desi
g
n
re
qui
res m
o
re t
h
an t
h
e
desi
gn
pu
bl
i
s
he
d i
n
[
1
3]
. It
ca
n
be j
u
st
i
f
i
e
d,
th
e prev
iou
s
o
n
e
used equal word
leng
ths wh
ile th
e propo
sed circu
it i
m
p
l
e
m
en
t v
a
ri
o
u
s
word
l
e
n
g
t
h
s
.
There
f
ore,
t
h
e
num
ber
of
sl
i
ces an
d L
U
Ts
increases for
t
h
e propose
d
desi
gn.
ACKNOWLE
DGE
M
ENTS
Th
e au
tho
r
s
g
r
atefu
lly ack
nowledg
e th
e
finan
c
ial sup
p
o
r
t
fro
m
Syiah
Kuala Un
iv
ersity, Min
i
stry o
f
Edu
catio
n and Cu
ltu
r
e
, Ind
o
n
e
sia und
er pro
j
ect
H
i
b
a
h
B
e
r
s
aing
,
No
.
49
8
/
U
N
11
/S/LK
-
B
O
PT/
2
014
, 26
May
2
014
.
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NC
ES
[1]
D.H. Lehmer, “Random number
genera
tion on the BRL high speed computing
machines”, b
y
M. L. Juncosa.
Math
.
Rev.
15
(1954)
,
559
[2]
http://en
.
wikiped
i
a.org
(2014) -
Linear
congru
e
ntial g
e
ner
a
tor, 10th March
http://en
.
wikiped
i
a.org
/
wiki/L
inear_congruen
tial_
generator
[3]
S.K. Park, and
K.W. Miller
,
“Ran
dom number gen
e
rators: good on
es are hard
to
fin
nd”,
Association
for Computin
g
Machiner
y
, 31(1
0
)
, pp: 1192-200
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I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
Im
pr
ove
d
Desi
g
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of
Li
ne
ar C
o
n
g
r
u
e
n
t
i
a
l
Ge
ner
a
t
o
r
b
a
se
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rdl
e
ngt
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u
b
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i
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ai
ny)
63
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[Num
erical
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h
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A
TLAB,
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y
C
l
ev
e B.
M
o
ler
,
SI
AM
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http://en
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i
a.org
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r
a
ndom nu
mber gener
a
tors, 11th Mar
c
h
http://en
.
wikiped
i
a.org
/
wiki/L
ist_
of_random_number_gener
a
tors
[6]
N. Harald
, “Ran
dom Number Generati
on
and Quasi-Monte Car
l
o Methods”,
So
ciety for
lndustrial and App
l
ied
Mathematics
, Ph
ilad
e
lphia, 1992.
[7]
A note on
rando
m number gener
a
tion
,
Christoph
e
Dutang
and
Diethelm Wuertz,
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[8]
Wolfram Mathe
m
atica
®
Tu
torial Co
llection
,
R
ANDO
M NUM
BER GENERA
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http://www.letech.jpn.com (2014
) - Genu
ine R
a
n
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.
wikiped
i
a.org
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mparison of
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a
ndom number gener
a
to
rs, 10th
March
http://en
.
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i
a.org
/
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pari
son_of_hard
ware_random_number_generato
rs
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Zulfik
ar, “Generating Non Unif
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”,
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nal R
eka
yas
a
El
ektr
i
ka
, Vol. 8 No. 2, Octob
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r 2009
[12]
Zulfik
ar, “FPGA Implementati
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a
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i
ka
, Vol. 11 No. 1, April
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[13]
Zulfik
ar and Hubbul Walidaiy
,
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t
ial Gener
a
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n
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i
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he Art of C
o
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ve
ra
nc
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te
m M
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i
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[16]
Zulfik
ar,
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verse Walsh Transf
orms for
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Electrical Engin
e
ering Journal
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o
l.18. No. 8, Pp: 3-8, October
20
12
BIOGRAP
HI
ES OF
AUTH
ORS
Hubbul Walida
i
ny
.
He was born in Banda Aceh, Aceh, I
ndonesia, in 1973. He graduated from
Electrical Engin
eering
Dep
a
rtment
at Gadjah Mada University
,
Yog
y
ak
arta, Indo
nesia,
in 1998.
The M
a
s
t
er De
gree in
Ele
c
tri
c
al Engin
eer
ing
from
Gadjah M
a
da Univers
i
t
y
, Yog
y
a
k
art
a
,
Indonesia, in
20
03.
He joined in th
e
Department of Electrical En
g
i
neering, S
y
iah Kuala University
, Aceh, Indonesia
in 2000, as
a
teaching st
aff. His
current
position
is the head of
Telecom
m
unicat
io
n Labor
ator
y
.
Z
u
lfikar.
He was born in Beureunuen, Aceh
, Ind
onesia,
in 1975
.
He received his
B.Sc. degr
ee in
Electrical Engin
eering
from North Sumatera Univ
ersity
, M
e
dan, I
ndonesia, the M. Sc. Degr
ee
in
Electrical Engin
eering from Kin
g
Saud Univer
sity
, Riy
a
dh, Sau
d
i Arabia, in 19
99 and 2011,
res
p
ect
ivel
y
He joined as
t
each
ing s
t
aff i
n
the Departm
e
nt of Ele
c
tron
ics
at P
o
lit
ekni
k Caltex Ri
au,
Pekanbaru, Indo
nesia in
2003.
He served
as head
of Industrial
Control Laborator
y
,
Politekni
k
Caltex Riau fro
m 2003 to 2006.
In 2006, he join
ed
the Electrical
Engineering Dep
a
rtment, S
y
iah
Kuala Unive
r
s
i
t
y
.
His
curren
t
p
o
s
ition is
he
ad
of
Digital Labor
ator
y
,
and his
current r
e
search
inter
e
sts include
VLSI design
and
S
y
stem on
Chip
s (SoC).
Evaluation Warning : The document was created with Spire.PDF for Python.