Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
6, N
o
. 3
,
Ju
n
e
201
6, p
p
. 1
183
~ 11
89
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
3.9
448
1
183
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Desi
gn of a Nonvolatil
e 8T1R SRAM Cell for
Instant-On Op
eration
J. Mounic
a
, G
.
V.
G
a
nesh
Department o
f
Electronics
a
nd C
o
mmunication Engineer
ing, K
L
University
, A.
P
,
India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Dec 9, 2015
Rev
i
sed
Jan 19, 201
6
Accepte
d
Fe
b 5, 2016
Now-a-day
s
, En
erg
y
consumptio
n is th
e majo
r k
e
y
factor
in Memories. B
y
switching the
circuit
in off mode and
with
a
n
lower volt
a
ge
s, leads to
decre
a
s
e
in an
power dis
s
i
pation of the circ
uit. Com
p
ared
to DRAM
SRAM’S are m
o
stl
y
used
bec
a
u
se of
thei
r dat
a
ret
a
ining
cap
a
b
ilit
y.
Th
e
major advantag
e of using SRAM’s rath
er than
DRAM’S is that,
the
y
ar
e
providing f
a
st p
o
wer-on/off speeds. He
nc
e S
R
AM
’s
are m
o
re pr
eferred
ove
r
DRAM’s for better instant-on op
eration.
Gen
e
ra
ll
y S
R
AM
’s
are
c
l
as
s
i
fied
in
to two ty
pes n
a
mely
volatile
a
nd non-volatile SRAM’s.
A
non-volatile
S
R
AM
enables
chip to ach
ieve
perform
ance fa
ctors
and als
o
provides
a
n
restore op
eratio
n which will b
e
enab
led b
y
an
restore sign
al
to
restore th
e
data
and also p
o
wer-up operation is pe
rformed. This pap
e
r des
c
ribes abou
t
novel NVSRAM circuit which produces
b
e
tter “instant-o
n operation”
compared to previous techniqu
es used
in SRAM’
s
. In addition to
normal 6T
S
R
AM
core, we are us
ing RRAM
circ
uitr
y (
R
esistive RAM) to provide
better instant-on
operation. B
y
co
mpari
ng the perf
ormance factors with 8T2R
and 9T2R, 8T1R
design performs the best
in th
e
Nano m
e
ter scal
e. Thus this
paper provid
e
s better performances in
power, en
erg
y
, propagation
delay
and
area
fa
ctors
as
c
o
m
p
ared with
ot
her des
i
gns
.
Keyword:
En
erg
y
co
nsum
p
t
io
n
Leaka
g
e reduct
ion
Non
-
vo
latile me
m
o
ry
Po
wer di
ssi
pat
i
o
n
Resistiv
e RAM (RRAM)
Static random
access m
e
m
o
ry
Tanner
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
J. Moun
ica,
Depa
rtem
ent of Electrical and Comm
unication E
ngi
neeri
n
g,
K L Un
iv
ersity,
A P
,
I
n
dia.
Em
a
il: lsn
tl@c
c
u
.
ed
u.tw
1.
INTRODUCTION
Lat
e
adva
nces
i
n
m
e
m
o
ry
i
nno
vat
i
o
n ha
ve
m
a
de concei
va
bl
e ne
w m
e
t
hods o
f
o
p
e
r
at
i
o
n f
o
r
Na
no
scale IC’s.
On th
e o
t
h
e
r hand
SRAM
’s are u
n
-pred
i
ctab
le, in
th
is way
no
n-stab
ility cap
acity is req
u
i
red
for
shut
d
o
w
n
o
p
er
at
i
ons [1]
,
[2]
.
Gene
ral
l
y
SR
AM
’s
a
r
e p
r
eferre
d tha
n
DR
AM’s
beca
us
e of it’s
d
a
ta
retain
in
g
cap
ab
ility. SRAM p
e
rform
s
b
o
t
h
vo
latile a
n
d
n
o
n
-
vo
latile
o
p
e
ratio
n
s
. In
o
u
r proj
ect we co
n
c
en
trate mo
re on
n
on-vo
latile SRAM wh
ich
p
r
o
d
u
ces in
stan
t
o
n
op
eratio
n
[3] . Th
ese are
desig
n
e
d
i
n
two
tech
no
log
i
es
na
m
e
l
y
transistor technol
ogy and re
s
i
stive t
echnol
ogy. In accordi
ngly, resistive
t
echnology use
s
1R and 2R s
e
ries.
Co
m
p
ared
to
2
R
series 1
R
p
r
od
u
ces m
o
re no
n-vo
latile
op
eration
effect
iv
ely. Hen
ce i
n
th
is
proj
ect
we are
u
s
ing
resistiv
e tech
no
log
y
which
was o
f
ten
called
as
Resis
tiv
e RAM (RRAM). Fo
r co
n
t
ro
lling
o
r
fl
o
w
in
g
of
cur
r
ent
/
v
ol
t
a
ge
t
h
ro
u
gh t
h
e r
e
si
st
or,
we are
usi
ng
on
e ad
di
t
i
onal
t
r
an
si
st
or w
h
i
c
h
was
so cal
l
e
d as cont
rol
tran
sistor.
As we k
now
t
h
at th
e
tran
sistor
will act as a
resisto
r
i
n
lin
ear reg
i
on
.
Th
e R
R
AM circu
itry wh
ich
we are
u
s
ing
in th
is
p
a
p
e
r
was act as
a “Me
r
mistor” (m
e
m
o
r
y resistor) [4].
As the years
progresse
d, e
x
pande
d
thickness 6
4kb & quicke
r get to
have
bee
n
accounted
for
NVSVR
A
M’S for m
i
l
itary a
p
p
lication
s
. The p
r
og
ramm
in
g
techno
log
y
o
f
an
FPGA’s
are g
e
n
e
rally u
tilizes
SRA
M
technolo
g
y
[
1
].
Th
e
en
erg
y
co
n
s
um
p
t
io
n
[
5
]
h
a
s b
e
co
m
e
a maj
o
r
sou
r
ce due to
an
con
s
ider
ab
ly
increase
in a
n
l
eakage
c
u
rr
ent
whi
l
e
we a
r
e
r
e
duci
n
g
i
t
’
s s
u
ppl
y
vol
t
a
ge a
n
d
feat
ure
si
ze
of
an
SR
AM
.
I
n
st
ant
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
11
8
3
– 11
89
1
184
o
n
op
eratio
n
mean
s,
b
y
ap
plyin
g
rest
o
r
e an
d power-up op
eration
t
h
e
d
a
ta
h
e
ld in th
e
SRAM
will b
e
cleared
and that
will be placed wit
h
t
h
e
non-
volatile data
held i
n
t
h
e st
ora
g
e cel
l
.
[6],[7] The
de
m
a
nd
for SR
AM is
in
creasing
with
larg
e u
s
e of SRAM
in
syste
m
-o
n
ch
i
p
a
n
d i
n
hi
gh
pe
rf
o
r
m
a
nce VLS
I
ci
rcui
t
s
.
Due
t
o
r
a
pi
d
i
n
crease i
n
t
h
r
e
sh
ol
d
vol
t
a
ge
[3]
,
[6]
,
[8]
fl
u
c
t
u
at
i
ons
w
h
i
c
h w
e
re ca
use
d
by
t
h
e
vari
at
i
ons
i
n
ul
t
r
a s
h
o
r
t
-
chan
nel
de
vi
ces, [
9
]
6T
SR
A
M
an
d i
t
’
s
pa
r
a
m
e
t
e
rs can
n
o
t
be
w
o
r
k
ed
un
der
hi
ghl
y
s
u
p
p
l
i
e
d
v
o
l
t
a
ges
whi
c
h
causes a
n
yield loss
[10].
I
n
t
h
is pro
j
ect
, w
e
ar
e
u
s
ing a r
e
sistor
instead
of
p
a
ss t
r
an
sist
o
r
t
h
oug
h it p
r
ov
id
es less en
er
g
y
consum
ption
because; pas
s
transistor
logic doe
s not provi
d
e a com
p
lete ‘0’
or ‘1’ a
s
an output signal
. The
Nan
o
m
e
t
e
r t
echn
o
l
o
gi
es
use
d
i
n
t
h
i
s
pa
per
are o
f
22
nm
te
chnology. T
h
e
y
are BSIM (B
erkley Short-c
h
annel
IGF
ET M
odel
)
, T
S
M
C
(Ta
l
wan
Sem
i
conduct
o
r M
a
n
u
f
act
uri
n
g C
o
m
p
any
Lt
d)
an
d PTC
(P
redi
ct
i
v
e
Technol
ogy M
odel
)
[11].
The
45
nm
technol
ogy lea
d
s to t
h
e dra
w
backs
of stability, delay and a
n
inc
r
e
a
se in
po
we
r di
ssi
pat
i
on ca
uses seve
re vt
vari
at
i
o
n [6]
,
[1
2]
i
n
ultra short-c
h
anne
l devices at
an aggressively scaled
technology nodes suc
h
as 22nm
.
The ne
t constraints s
u
ch
as power, ene
r
gy
,delay are
calculated using this
technology.
1.
1.
R
e
sist
i
v
e Techno
logy
R
e
si
st
i
v
e R
a
nd
om
Access M
e
m
o
ry
(R
R
A
M
or R
e
R
A
M
)
i
s
one
o
f
t
h
e t
y
p
e
of
N
V
R
A
M
t
h
at
w
o
r
k
s
by the cha
nge
of a resista
n
ce
value acr
oss a
dielectric
m
a
te
rial ie a solid st
ate
m
a
terial which work
or a
c
t as a
mer
m
isto
r [4
].
A m
e
r
m
isto
r is an on
e of t
h
e
form
a n
on-vo
l
a
tile
m
e
m
o
ry
t
h
at was b
a
sed
o
n
th
e
switch
i
n
g
of
an
resisto
r
th
at
in
tu
rn
s resu
lts
in
in
creasing
t
h
e cu
rren
t
fl
o
w
t
h
r
o
u
g
h
resi
st
or i
n
one
di
rect
i
on a
n
d
decrea
ses i
n
th
e ano
t
h
e
r d
i
rectio
n
ie
o
ppo
site d
i
rection. Th
e m
a
teri
als use
d
i
n
t
h
i
s
t
echn
o
l
o
gy
ar
e of i
n
b
r
oa
d
ran
g
e
ap
p
lication
s
.
Th
ey rang
e fro
m h
ealth
care t
o
v
i
d
e
o
su
rv
eillan
ce an
d o
t
h
e
r po
wer
g
a
ting
tech
n
i
q
u
e
s [13
]
.
The
phy
si
cal
p
h
en
om
enon
w
h
i
c
h
has
bee
n
do
ne si
nce
40y
ears i
n
t
h
e R
R
AM
ci
rc
ui
t
r
y
o
p
erat
i
o
n
was
resi
st
ance swi
t
chi
n
g w
h
en a
n
i
nput
v
o
l
t
a
ge
or c
u
r
r
ent
i
s
appl
i
e
d
,
t
h
at
re
si
st
ance was s
o
cal
l
e
d as ne
gat
i
v
e
resistance
[11]. MOM (Metal-Oxi
de-M
etal) s
t
ructures s
u
c
h
as SiO
x
, Al
2
O
3
, TO
2
O
5
, Z
r
O
2
&
TiO
2
[8
]
are som
e
of the m
a
terials that produce negativ
e
resistance. In a bipolar RRAM, wh
en t
h
e ap
pl
i
e
d
vol
t
a
ge c
h
a
nge
s by
in
creasing
,
an
in
itial h
i
g
h
resistan
ce state g
r
ad
u
a
lly d
ecrea
ses to
lo
w resistan
ce state. Th
is is so
called
as a
SET (Single
El
ectro
n T
r
ansist
or).
2.
CO
NVE
NTI
O
N
A
L DE
SI
GN
Th
is p
a
p
e
r fu
lly d
e
scrib
e
s abo
u
t
th
e techn
o
l
o
g
y
u
s
ed
fo
r ach
i
ev
ing
a no
n-vo
latile SRAM fo
r in
stant
o
n
o
p
e
ration
.
RRAM p
r
o
v
i
des g
ood
stab
ility an
d
also
produ
ces a p
e
rfect o
u
t
p
u
t
as co
m
p
ared
to p
a
ss
tran
sistor log
i
c. Th
e no
rm
al 6
T
SR
AM cel
l p
r
o
v
i
d
e
s
p
oor stab
ility an
d h
i
gh
h
a
s static no
ise m
a
rg
in
s.
On
d
o
i
n
g
t
h
is op
eratio
n
,
th
e stab
i
lity o
f
an
SRAM cell d
ecreases d
u
e
t
o
app
l
y v
o
ltag
e
d
i
v
i
d
e
r b
e
tween
th
e
d
r
i
v
er
transistors.
2.
1.
Previous NVSRAM’s
Th
is section
rev
i
ews t
w
o NVSRAM cells usin
g
RR
AM’s
for
n
o
n
-
vo
latile sto
r
ag
e. Th
e 8
T
2
R
and
9T
2R
cel
l
s
ad
o
p
t
di
ffe
rent
pr
o
cess an
d
sche
m
e
s t
o
p
r
o
g
r
a
m
t
h
e N
V
SR
A
M
.
2.
1.
1.
8T
2
R
NV
SR
A
M
mem
or
y ce
l
l
[1]
Th
e
8
T
2
R
NVSRAM cell is
p
l
ann
e
d u
tilizin
g a co
m
p
le
m
e
n
t
ary circu
it (Fig
ure
1
)
as sh
own b
e
l
o
w.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Design
o
f
a
Non
v
o
l
a
tile 8
T
1
R
S
R
AM Cell fo
r In
stan
t-On Opera
tion
(J. Mou
n
i
ca
)
1
185
Fi
gu
re
1.
R
R
A
M
base
d
8T
2R
N
V
SR
AM
cel
l
Two
RRAMs
(RRAM1, RRAM2) are
u
tilized
p
e
r SR
AM cell (g
iv
en
b
y
th
e MOSFETs M1
-M
6
)
.
The re
sistive c
o
m
pone
nts are
joi
n
ed
w
ith t
h
e inform
ation hubs
of t
h
e SR
AM
cell to store the intellige
n
t data
fo
r t
h
e
6T cel
l
du
ri
n
g
"F
orce
of
f", i
n
t
h
i
s
m
a
nner
wi
t
h
st
andi
ng t
o
t
h
e
gene
ral
m
odel
of a
NV
SR
A
M
, t
h
e
resistive com
pone
nts are a
piece of two RRAMs and are
go
tten to utilizing two contro
l transist
ors
.
Acc
o
rding
to the data put away at the inform
at
ion hubs (D,
DN)
of the 6T center,
each RRAM
is
m
odified either to a
LRS
or
H
R
S [1
4
]
,[
15
]. A
t
the
po
in
t w
h
e
n
t
h
e
force s
u
ppl
y is turned ON, th
e i
n
form
ation is c
o
m
posed
back t
o
the 6T SR
AM
center i
n
view
of the states
put away in t
h
e
re
sistive com
p
onents
.
2.
1.
2.
9T
2
R
NV
SR
A
M
mem
or
y ce
l
l
So al
s
o
, t
h
e
9T
2R
m
e
m
o
ry
cel
l
(Fi
g
u
r
e
2)
[
1
]
expl
oi
t
s
t
w
o
pr
o
g
ram
m
abl
e
R
R
A
M
s
f
o
r
n
o
n
-
u
nst
a
bl
e
capacity amid the "S
hu
t dow
n" state as sh
own
b
e
low
.
Fi
gu
re
2.
R
R
A
M
base
d
9T
2R
N
V
SR
AM
cel
l
No
t
w
ith
stand
i
n
g
a
6
T
SR
AM cen
ter, a levelin
g
tran
sist
or is prese
n
ted.
The s
o
urce a
n
d deplete of the
center tra
n
sistor are
joine
d
with
the capac
ity hubs D a
n
d DN sepa
rate
ly. The entryways of the two access
tran
sistors of th
e SRAM cen
t
e
r an
d
th
e ev
en
ing
ou
t tran
si
stor are ent
w
ined to th
e Restore signal. Likewise
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
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08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
11
8
3
– 11
89
1
186
uni
que in
relation to the
8T2R circuit, it uses j
u
st a
solita
ry Piece Line (BL) and
presents an ext
r
a Source
Li
ne (SL
)
t
o
p
r
o
g
ram
t
h
e t
w
o R
R
A
M
’
s. T
h
e m
i
ddl
e of t
h
e road
hubs of the two
1T1R cells are ass
o
ciate
d
with
th
e first an
d supp
lem
e
n
t
BL’s
o
f
th
e
SRAM cen
t
er separately [6
].
Th
e
wellsp
r
i
n
g
s
of two
word
lin
e
signals
are ent
w
ine
d
to the SL,
whil
e alternate fini
shes
of t
h
e
1T
1R
cel
l
s
are
associ
at
ed
wi
t
h
B
L
.
Eac
h
1T
1R
cel
l
has
i
t
s
ow
n
part
i
c
ul
ar
Wo
r
d
Li
ne
(si
gni
fi
ed as
WL
L an
d
WLR i
n
d
i
v
i
dually); alo
n
g
these lin
es, th
e
in
fo
rm
atio
n
are pu
t away in th
e t
w
o RRAM’s am
id
th
e
"Shu
t
down" state a
n
d
restored bac
k
to the
6T SR
AM
center
when the
force
sup
p
ly is tu
rn
ed
ON.
3.
PROP
OSE
D
DESIG
N
Th
e
p
r
o
p
o
s
ed
8
T
1
R
NVSRAM o
u
tlin
e is app
eared
in
Figu
re 3
.
In
t
h
is d
e
si
g
n
we
u
s
e
o
n
l
y
o
n
e
1
T
1
R
(wi
t
h
a resi
st
i
v
e com
pone
nt
den
o
t
e
d as R
R
A
M
1
)
was adde
d t
o
t
h
e n
o
r
m
a
l 6T SR
AM
cel
l (M
1-M
6
)
.
Th
e
resistiv
e RRAM1
was con
t
rolled
b
y
th
e tran
sisto
r
wh
ich
wa
s above the re
sistor. It is
j
o
ined
str
a
igh
t
fo
rwar
d
l
y
to
th
e in
fo
rm
atio
n
nod
e o
f
t
h
e m
e
m
o
ry co
re and
is u
tilized
to
store th
e lo
g
i
c d
a
ta of th
e SRAM fo
rced
to
p
r
od
u
ce its "Sh
u
t
do
wn
" stat
e. The tran
sisto
r
m
easu
r
i
n
g
meth
o
d
o
l
og
y fo
r
ou
tlin
ing
the 8
T
1
R
relies
o
n
upon
th
e cen
ter of th
e propo
sed
cell (fo
r th
is situ
atio
n, a
6
T
SRAM) and
m
u
st co
n
s
id
er its Read
/
W
rite operatio
n
rig
h
tness
.
Fi
gu
re
3.
Pr
o
p
o
se
d
8T1R
N
V
S
R
A
M
cel
l
Sub
s
equ
e
n
tly, lik
e th
e
8
T
2
R
NVSRAM cell
and
relying
up
on
t
h
e p
a
rticu
l
ar
d
a
ta pu
t away at the
SR
AM
i
n
f
o
rm
at
i
on h
u
b
,
t
h
e
R
R
A
M
co
m
pone
nt
cha
nge
s
i
t
s
resi
st
ance
bet
w
ee
n t
h
e L
o
w R
e
si
st
ance
St
at
e
(LR
S
) a
n
d t
h
e
Hi
g
h
R
e
si
st
ance St
at
e (
H
R
S
). T
h
e
SET
pr
oce
d
u
r
e c
h
a
nge
s t
h
e
resi
st
ance c
o
m
pone
nt
fr
om
HRS to LRS;
the RESET
proce
d
ure is
utilized for th
e
opposite ope
r
ation.
To
accom
p
l
i
sh
non-unstable
"Inst
a
nt
- o
n
" o
p
erat
i
o
n,
[3]
t
h
e pr
op
ose
d
m
e
m
o
ry
cell
has two esse
nt
i
a
l
st
at
es:
"Shut
d
o
w
n" a
nd "P
o
w
er-
up"
.
"Forc
e
up" re
q
u
i
r
es t
o
"R
eset
" (i
.e. t
h
e R
E
SET pr
oce
d
u
r
e hap
p
e
n
s i
n
R
R
A
M
1
,
ho
we
ver
i
n
fl
uen
c
i
n
g l
i
k
ewi
s
e
the m
e
m
o
ry
center)
, "St
o
re"
a
n
d
"Resto
re".
4.
SIM
U
LATI
O
N
RESULTS
AN
D DIS
C
US
SION
S
4.
1.
8
T
2R
N
V
SRAM
cell
Th
e
8
T
2
R
NVSRAM m
e
m
o
ry cell si
m
u
lati
o
n
resu
lts
are
a
s
f
o
l
l
o
ws
N
o
r
m
al
ly
SR
AM
per
f
o
r
m
s
bot
h
read
and
write o
p
e
ration
s
.
In read
op
eration o
f
th
is
s
p
ecifi
c SRAM cell perform
s
operations like
when bot
h
in
pu
ts su
ch as
b
it lin
e an
d word lin
e are h
i
gh, th
e
p
r
o
d
u
ced
out
put
i
.
e
q
b
al
so
go
es t
o
hi
gh
[
1
]
.
In write op
eratio
n
,
i
f
word
lin
e is set to
l
o
w i.e
zer
o, t
h
e
o
u
t
p
ut
st
o
r
es
t
h
e p
r
e
v
i
o
us
S
R
AM
val
u
e
whi
c
h
per
f
o
r
m
s
i
n
st
ant
-
o
n
o
p
e
rat
i
o
n
.
T
h
e i
n
put
s
re
prese
n
t
e
d
in th
is
Figu
re 4
,
5,
6
an
d th
ey are in th
e
order
o
f
b
o
tto
m
to
top
(b
l, wl, q
,
qb
,
cn
trl1,
cn
trl2).
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
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:
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8-8
7
0
8
Design
o
f
a
Non
v
o
l
a
tile 8
T
1
R
S
R
AM Cell fo
r In
stan
t-On Opera
tion
(J. Mou
n
i
ca
)
1
187
Fi
gu
re
4.
Si
m
u
l
a
t
i
on res
u
l
t
s
o
f
8T2R
N
V
SR
AM
ce
ll fo
r in
stan
t-
on
op
er
ati
o
n at 22n
m
tec
h
no
log
y
Th
e abo
v
e
fi
g
sh
ows th
e simu
latio
n resu
lts
o
f
8
T
2
R
NVSRAM cell fo
r in
stan
t-on
op
eratio
n
at
22
n
m
t
echn
o
l
o
gy
.
It
per
f
o
r
m
s
bot
h
read
an
d
w
r
i
t
e
ope
rat
i
o
ns i
n
n
o
rm
al
m
ode a
n
d i
n
st
an
d
b
y
m
ode
.
In
n
o
r
m
a
l
m
ode
i
t
perr
f
o
rm
s read
ope
rat
i
o
n a
n
d
i
n
st
a
n
d
b
y
m
ode [7]
,
i
t
pe
rfo
r
m
s
write op
eration
.
Su
ppo
se in th
e abo
v
e figu
re
if b
itlin
e is eq
u
a
l to
1
and
also
wo
rd
lin
e is eq
u
a
l to
1
th
en q
b
is eq
u
a
l to
1
.
In
o
t
her case if wo
rd
lin
e is eq
u
a
l
to
0, th
en
t
h
e
ou
tpu
t
qb
sto
r
es
th
e prev
iou
s
v
a
lu
e wh
ich rep
r
esen
ts th
e in
stan
t-o
n
op
erati
o
n.
4.
2.
9
T
2R
NV
SRAM
cell
The
9T
2R
N
V
SR
AM
m
e
m
o
ry
cel
l
si
m
u
lat
i
on r
e
sul
t
s
a
r
e as Fi
g
u
re
5. T
h
i
s
fi
g
u
re
sh
ow
s t
h
e
sim
u
lation res
u
lts of
9T
2R
NVSRAM
cell for insta
n
t-on
operation at
22nm
technology.
It pe
rform
s
bot
h
read
and
w
r
i
t
e
o
p
er
at
i
ons i
n
no
rm
al
m
ode a
n
d
i
n
st
an
dby
m
ode.
Fi
gu
re
5.
Si
m
u
l
a
t
i
on res
u
l
t
s
o
f
8T2R
N
V
SR
AM
ce
ll fo
r in
stan
t-
on
op
er
ati
o
n at 22n
m
tec
h
no
log
y
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
11
8
3
– 11
89
1
188
In norm
a
l
m
ode and standby
m
ode, it perform
s
either
low or hi
gh si
gnal
i.e 0 (or) 1. Because he
re
we ap
p
l
y an
resto
r
e
sign
al.
So
, it will op
erate in
stand
b
y
m
o
d
e
. As com
p
ared
to
p
r
ev
iou
s
on
e it do
es
no
t
p
r
od
u
ces b
e
tter in
stan
t-on
o
p
e
ratio
n lik
e th
at
d
e
sign
.
4.
3.
8
T
1R
N
V
SRAM
cell
Th
e
8
T
1
R
NVSRAM m
e
m
o
ry cell si
m
u
lati
o
n
resu
lts are as Figu
re 6. Th
e figu
re sh
ows t
h
e
sim
u
l
a
t
i
on res
u
l
t
s
of
8T
1R
N
V
SR
AM
cel
l
f
o
r
i
n
st
ant
-
o
n
o
p
erat
i
o
n at
2
2
n
m
t
echnol
o
g
y
.
It
pe
rf
orm
s
b
o
t
h
read
and
w
r
i
t
e
o
p
er
at
i
ons i
n
no
rm
al
m
ode a
n
d
i
n
st
an
d
by
m
ode.
Fi
gu
re 6.
Si
m
u
l
a
t
i
on
res
u
l
t
s
o
f
8T1R
N
V
SR
AM
cell fo
r in
stan
t-
on
op
er
ati
o
n at 22n
m
tec
h
no
log
y
.
Thi
s
pr
op
ose
d
8T
1R
N
V
SR
AM
p
r
o
v
i
d
es
i
n
st
ant
-
on
-
ope
r
a
t
i
on as
best
as com
p
ared t
o
pre
v
i
o
us
t
echn
o
l
o
gi
es.
I
n
rea
d
o
p
erat
i
o
n i
t
pe
rf
orm
s
t
h
e sam
e
operat
i
on as
pe
r t
h
e
pre
v
i
o
us t
e
c
h
n
i
ques a
n
d al
so
i
n
t
h
e
in
th
e
write op
eration
sam
e
tech
n
i
q
u
e
fo
l
l
o
w
s. As
p
e
r th
e
figu
re, if wo
rd
lin
e is eaq
u
a
l t
o
1
it
d
o
e
sno
t
p
r
od
u
ces an
perfect oup
u
t
si
g
n
a
l as
well if it will b
e
eq
ual to
0
,
it stores th
e prev
i
o
us v
a
lu
e
with
ou
t an
y
distortions
and also less
dela
y and also m
i
n
i
m
i
zes so
m
e
perform
a
nce cri
t
eria due to
t
h
e
use
o
f
rest
o
r
e
si
gnal
[6]
i
n
o
u
r
de
si
g
n
.
He
nce t
h
i
s
p
r
o
p
o
sed
desi
g
n
pr
o
duc
es l
e
ss
del
a
y
,
l
o
w
po
w
e
r a
nd al
s
o
occ
upi
es
a l
e
ss am
ou
nt
of
area.
S
o
,
we
co
nsi
d
e
r
t
h
i
s
a
s
a
bet
t
e
r de
si
g
n
fo
r
pr
o
duci
n
g
bet
t
e
r i
n
st
a
n
t
-
o
n
o
p
erat
i
o
n.
Tab
l
e 1
.
C
o
m
p
arisio
n
of d
i
fferen
t NVSRAM
typ
e
s
5.
CO
NCL
USI
O
N
Th
is p
a
p
e
r
p
r
esen
ts th
at a lo
w po
wer non
-v
o
l
atile SRAM (NVSRAM
)
cell d
e
sig
n
wh
ich
can
b
e
u
tilized
fo
r i
n
stan
t-on
op
eratio
n i.e.
b
y
ap
p
l
yin
g
rest
ore and
p
o
wer-u
p operatio
n th
e
d
a
t
a
h
e
ld in
t
h
e SRAM
will be cleared and that will be pl
aced wi
th the non-vol
a
tile data held
in the storage
m
e
m
o
ry cel
l
.
The
p
r
op
o
s
ed
8
T
1R SRAM m
e
m
o
ry cell ach
iev
e
s in an drastic redu
ction in
term
s o
f
en
erg
y
an
d power as
NVSRAM
T
y
pes
Power
Energy
Delay
8T
2R
2.
63 W
5.
24J
2.
4525e-
0
1
0
9T
2R
9.
54W
10.
2J
5.
4525e-
0
1
2
8T
1R
2.
53W
7.
60J
2.
5251e-
0
1
0
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Design
o
f
a
Non
v
o
l
a
tile 8
T
1
R
S
R
AM Cell fo
r In
stan
t-On Opera
tion
(J. Mou
n
i
ca
)
1
189
co
m
p
ared
with o
t
h
e
r
NVSR
AM m
e
m
o
ry c
e
lls as we d
i
scu
ssed
in
th
e introd
u
c
tion
sect
io
n
.
Th
e normal 6
T
SRAM core re
qui
res efficien
t
energy while
the written operation is ta
king place a
n
d also in sta
n
dby
m
ode.
Bu
t, th
e
n
a
tu
re of an
no
n-v
o
l
atile
SRAM (NVSRAM) sav
e
s en
erg
y
d
i
ssip
atio
n in an
sig
n
i
fican
t
m
a
n
n
e
r.
At
last, th
is
p
a
p
e
r
sh
ows th
at t
h
e
p
r
op
o
s
ed
NVSRAM m
e
m
o
ry
cell produ
ces
an
efficien
t
v
a
riatio
n
s
in all the n
e
t
constraints s
u
c
h
as
delay,
power and e
n
ergy.
ACKNOWLE
DGE
M
ENT
I sin
c
erely th
an
k to m
y
p
r
o
j
ect g
u
i
d
e
, who h
e
lp
ed m
e
in
all asp
ects
o
f
my p
r
oj
ect to
co
m
p
lete in
sh
ort term
.
W
e
also
t
h
ank
KL Un
iv
ersity for
p
r
ov
id
ing
n
ecessary facilities to
ward
s carryin
g ou
t th
is wo
rk
.
REFERE
NC
ES
[1]
W. Wei, “Design of a Non-v
o
latile 7T!R
S
R
AM
cell
for
Ins
t
ant-On Op
erat
ion,”
IEEE transactions o
n
nanotechno
logy
, vol/issue: 13(5)
, 2014.
[2]
O. Turk
yilm
a
z
,
et al
., “RRAM-based FPGA for “Nor
mally
O
ff,
Instantl
y On” A
pplic
ations,
”
Pr
oceed
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