Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
8,
No.
2,
April
2018,
pp.
933
–
938
ISSN:
2088-8708
933
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
Lo
w-P
o
wer
D-Band
CMOS
Amplifier
f
or
Ultrahigh-Speed
W
ir
eless
Communications
T
uan
Anh
V
u
1,2
,
K
y
oya
T
akano
1
,
and
Minoru
Fujishima
1
1
Graduate
School
of
Adv
anced
Sciences
of
Matter
,
Hiroshima
Uni
v
ersity
,
Japan
2
VNU
Uni
v
ersity
of
Engineering
and
T
echnology
,
V
ietnam
Article
Inf
o
Article
history:
Recei
v
ed
September
7,
2017
Re
vised
December
28,
2017
Accepted:
Jan
29,
2018
K
eyw
ord:
Amplifier
D-Band
Dif
ferential
Capaciti
v
e
Neutralization
Millimeter
-W
a
v
e
ABSTRA
CT
This
paper
present
s
a
lo
w-po
wer
D-Band
amplifier
suitable
for
ultrahigh-speed
wireless
communications.
The
three-stage
fully
dif
ferential
amplifier
with
capaciti
v
e
neutralization
is
f
abricated
in
40
nm
CMOS
pro
vided
by
TSMC.
Measurement
results
sho
w
that
the
D-
band
amplifier
obtains
a
peak
g
ain
of
9.6
dB
o
v
er
a
-3
dB
bandwidth
from
138
GHz
to
164.5
GHz.
It
e
xhibi
ts
an
output
1
dB
compression
point
(OP1dB)
of
1.5
dBm
at
the
center
frequenc
y
of
150
GHz.
The
amplifier
consumes
a
lo
w
po
wer
of
27.3
mW
from
a
0.7
V
supply
v
oltage
while
its
core
occupies
a
chip
area
of
0.06
mm
2
.
Copyright
c
2018
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
Name:
T
uan
Anh
V
u
Af
filiation:
VNU
Uni
v
ersity
of
Engineering
and
T
echnology
Address:
144
Xuan
Thuy
Rd.,
Cau
Giay
Dist.,
Hanoi,
V
ietnam
Phone:
+84-4-3754-9338
Email:
tanhvu@vnu.edu.vn
1.
INTR
ODUCTION
According
to
the
current
trend,
the
frequenc
y
used
for
wireless
communication
will
reach
the
terahertz
band
in
2020.
The
unallocated
frequenc
y
re
gion
be
yond
275
GHz
with
v
ast
bandwidth
can
be
potentially
utilized
for
ultrahigh-speed
wireless
communication.
In
particular
,
the
300
GHz
band
is
attracti
v
e
since
propag
ation
decay
in
air
around
300
GHz
is
relati
v
ely
lo
w
.
Ho
we
v
er
,
since
studies
on
terahertz
wireless
communication
including
the
300
GHz
band
are
still
in
early
stage
when
only
a
fe
w
transcei
v
ers
operating
abo
v
e
275
GHz
were
reported
[1]
[2].
Since
the
maximum
operating
frequenc
y
or
the
unity-po
wer
-g
ain
frequenc
y
,
f
max
,
of
the
n-type
MOSFET
e
v
en
with
adv
anced
CMOS
process
is
belo
w
300
GHz,
realization
of
300
GHz
RF
front-end
is
challenging.
One
solution
is
to
use
frequenc
y
multipliers.
A
300
GHz
CMOS
RF
front-end
w
as
reported
using
a
tripler
[4].
Ho
we
v
er
,
the
tripler
generates
not
only
the
desired
RF
signal
b
ut
also
the
higher
-order
spurious.
As
a
result,
the
RF
signal
may
be
distorted
by
a
higher
-order
spurious.
On
the
other
hand,
since
quadratic
nonlinearity
of
a
MOSFET
is
stronger
than
its
cubic
counterpart,
a
doubler
can
generate
higher
output
po
wer
than
a
tripler
does.
When
the
doubler
is
emplo
yed,
the
300
GHz
output
signal
can
be
generated
from
the
150
GHz
input
one.
In
this
paper
,
we
are
going
to
present
a
lo
w-po
wer
D-band
amplifier
whose
center
frequenc
y
is
150
GHz.
This
amplifier
will
be
used
as
the
preceding
stage
of
the
300
GHz
doubler
.
2.
DESIGN
OF
D-B
AND
AMPLIFIER
The
D-band
amplifier
is
designed
using
TSMC
40
nm
1P10M
CMOS
GP
process.
Its
back
end
consists
of
10
copper
layers
and
a
top
aluminum
redistrib
ution
layer
(RDL).
The
cross-vie
w
of
a
grounded
coplanar
w
a
v
e-guide
transmission
line
(GCPW
-TL)
is
depicted
in
Fig.
1
[5].
The
GCPW
-TL
with
the
characteristic
impedance
of
50
(the
50
GCPW
-TL)
is
used
for
connecting
to
the
input
and
output
pads
of
the
D-band
amplifier
.
Its
signal
line
consists
of
the
RDL
layer
wi
th
a
width
of
9
µm.
Ground
(GND)
w
alls
composed
of
the
6th
to
10th
metal
layers
with
a
width
of
2.7
µm
are
placed
on
the
both
side
of
the
signal
line
at
the
distance
of
7.2
µm.
The
GCPW
-TL
with
the
charact
eristic
impedance
of
71
(the
71
GCPW
-TL)
is
used
for
the
shunt
stubs
of
the
amplifier’
s
matching
J
ournal
Homepage:
http://iaescor
e
.com/journals/inde
x.php/IJECE
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
,
DOI:
10.11591/ijece.v8i2.pp933-938
Evaluation Warning : The document was created with Spire.PDF for Python.
934
ISSN:
2088-8708
netw
orks
and
the
series
stubs
of
the
rat-race
balun.
The
width
of
the
t
op-layer
signal
line
is
2.9
µm,
and
the
GND
w
all
placed
at
a
distance
of
7.6
µm
from
the
signal
line
has
the
width
of
1.8
µm.
The
3nd
to
5th
metal
layers
are
meshed
and
stitched
together
with
vias
to
form
the
GND
plane.
Figure
1.
The
cross-vie
w
of
the
71
GCPW
-TL.
Figure
2.
The
proposed
D-band
amplifier
.
The
complete
circuit
of
the
proposed
amplifier
with
all
component
v
alues
are
gi
v
en
in
Fig.
2.
It
includes
in-
put
matching
netw
orks,
output
matching
netw
orks,
three
fully
dif
ferential
amplifying
stages
and
inter
-stage
matching
netw
orks.
F
or
bandwidth
enhancement,
multi-stage
matchings
using
capacitors
and
GCPW
-TLs
are
adopted.
The
series
capacitors
and
shunt
GCPW
-TLs
form
4th-order
high-pass
filters
at
the
inputs
and
outputs
of
the
amplifier
.
Both
the
inputs
and
outputs
are
matched
to
50
for
measurement
purpose.
The
inter
-stage
matching
netw
orks
are
based
on
PI
netw
orks
for
wideband
performance.
All
of
the
capacitors
also
act
as
coupling
capacitors
while
the
DC
bias
v
oltages
are
applied
through
the
GCPW
-TLs.
The
bias
v
oltages
are
common
to
all
amplifying
stages.
The
shunt
stubs
composed
of
the
71
GCPW
-TLs
are
arranged
re
gularly
with
sharing
GND
w
alls,
and
the
space
between
the
GCPW
-TLs
is
17
µm.
The
near
-end
and
f
ar
-end
crosstalk
simulated
by
EM
simulation
are
belo
w
-30
dB
and
-34
dB
at
100
GHz
and
250
GHz,
respecti
v
ely
.
It
indicates
that
the
cross-coupling
between
stubs
is
ne
gligible..
The
connection
between
the
MOSFETs,
MOM
capacitors
and
GCPW
-TLs
are
made
by
the
8th
to
10th
metal
layers.
The
lengths
of
the
GCPW
-TLs
and
the
number
of
finger
s
of
MOM
capacitors
are
determined
by
a
nonmetric
optimization
process
taking
into
account
the
models
of
MOSFETs,
MOM
capacitors
and
GCPW
-TLs.
The
f
ar
end
of
each
shunt
IJECE
V
ol.
8,
No.
2,
April
2018:
933
–
938
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
935
Figure
3.
Amplifier
core
(a)
and
its
equi
v
alent
circuit
with
e
xtracted
parasitics
(b).
stub
is
terminated
by
a
wideband
decoupling
po
wer
line
with
v
ery
lo
w
characteristic
impedance
(the
0
TL)
[6].
The
internal
ne
g
ati
v
e
feedback
path
caused
by
the
parasitic
g
at
e-drain
capacitor
,
C
GD
limits
the
po
wer
g
ain
and
re
v
erse
isolation,
and
potentially
causes
instability
.
In
order
to
impro
v
e
the
stabil
ity
without
compromising
the
g
ain
of
the
MOSFET
,
the
internal
feedback
in
the
transistor
has
to
be
reduced.
An
ele
g
ant
technique
to
accomplish
this
is
to
neutralize
C
GD
in
a
dif
ferential
pair
by
us
ing
cross
coupling
capacitors
[7].
Fig.
3a
sho
ws
the
core
of
the
amplifier
that
is
a
fully
dif
ferential
pair
with
capaciti
v
e
neutralization.
The
cross
coupling
capacitor
whose
v
alue
is
16.1
fF
is
determined
to
obtain
high
g
ain.
Fig.
3b
re
v
eals
the
parasitics
associated
at
each
node
of
the
amplifier
core.
The
parasitic
components
are
e
xtract
ed
using
bond-based
design
which
is
a
measurement-based
design
approach
to
a
v
oiding
the
dif
ficulty
associated
with
layout
parasitics
when
ordinary
layout
parasitic
e
xtraction
(LPE)
tools
used
for
chip
design
do
not
e
xtract
inductances
[8].
Multistage
amplifiers
for
terahertz
frequencies
tend
to
occup
y
a
lar
ge
area
since
inter
-stage
matching
netw
orks
consist
typically
of
se
v
eral
passi
v
e
de
vices
that
are
much
lar
ge
than
MOSFETs.
T
o
realize
cost-ef
fecti
v
e
chips,
area
reduction
is
important.
In
order
to
reduce
the
area
of
the
amplifier
,
we
proposed
the
”fishbone
layout”
[9].
In
this
technique,
GCPW
-TL
stubs
used
in
matching
netw
orks
are
arranged
re
gularly
at
narro
w
spacings,
and
the
GCPW
-TLs
themselv
es
are
designed
to
be
narro
w
,
thereby
reducing
the
footprint.
Figure
4.
The
die
microphotograph
of
the
D-band
amplifier
.
Low-P
ower
D-Band
CMOS
Amplifier
for
Ultr
ahigh-Speed
W
ir
eless
...
(T
uan
Anh
V
u)
Evaluation Warning : The document was created with Spire.PDF for Python.
936
ISSN:
2088-8708
T
able
1.
Comparison
with
pre
vious
published
amplifiers
operating
in
the
similar
frequenc
y
band
P
arameter
MWCL
’11
[10]
Elec.
Let’11
[11]
APMC’13
[12]
RFIT’15
[5]
This
w
ork
CMOS
T
echnology
65
nm
65
nm
65
nm
40
nm
40
nm
No.
of
Stages
3/Dif
ferential
5/Dif
ferential
4/Dif
ferential
5/Dif
ferential
3/Differ
ential
Gain
(dB)
20.6
8.1
7.1
19.7
9.6
Center
Freq.
(GHz)
144
200
147
138
150
-3
dB
BW(GHz)
3*
5*
13*
22
26.5
Die
Area
(mm
2
)
0.05
0.06
0.12
0.06
0.06
Supply
V
oltage
(V)
1.4
2.0
2.0
0.94
0.7
Po
wer
Cons.
(mW)
54.6
108
104
75
27.3
GBWP/
P
DC
0.59
0.12
0.28
2.83
2.93
*
Estimated
graphically
3.
MEASUREMENT
RESUL
TS
In
order
to
v
erify
the
performance
of
the
D-band
amplifier
,
a
chip
prototype
w
as
f
abricated
in
TSMC
40
nm
CMOS.
Fig.
4
sho
ws
the
die
microphotograph
of
the
amplifier
.
The
amplifier
occupies
an
area
of
0.65
0.74
mm
2
including
probe
pads,
input
and
output
balun
while
its
core
is
only
0.06
mm
2
.
The
rat
-race
balun
composed
of
the
71
GCPW
-TLs
is
designed
for
con
v
ersion
between
the
single-ended
and
dif
ferential
signals
at
the
inputs
and
outputs
of
the
amplifier
.
The
length
of
the
GCPW
-TL
unit
of
the
rat-race
balun
is
300
µm
which
is
equi
v
alent
to
/4
at
150
GHz
(
is
the
w
a
v
e
length).
The
compact
design
is
realized
by
folding
the
GCPW
-TLs
and
sharing
the
GND
w
all.
The
amplifier
w
as
measured
by
means
of
on-chip
probings
using
a
probe
station.
The
RF
probe
pads
were
designed
for
ground-signal-ground
(GSG)
probes
with
750
µm
pitch.
The
Anritsu
37397D
VN
A
and
D-band
frequenc
y
e
xtenders
were
used
for
measuring
small-signal
S-parameters.
Fig.
5
sho
ws
the
measured
and
simulated
S-parameters
of
the
D-band
amplifier
.
As
can
be
seen
in
this
figure,
the
measured
results
sho
w
good
agreements
with
the
simulated
ones.
Both
input
and
output
ret
urn
loss
indicate
wideband
performance
when
S
11
and
S
22
remain
belo
w
-10
dB
o
v
er
the
-3
dB
bandwidth
from
138
GHz
to
164.5
GHz.
The
D-band
amplifier
achie
v
es
a
peak
g
ain
of
9.6
dB
at
150
GHz
(after
compensating
for
the
rat-race
balun’
s
loss).
The
re
v
erse
isolation
is
lo
wer
than
-40
dB.
A
high
re
v
erse
isolation
guarantees
high
stability
for
the
amplifier
.
Fig.
6
plots
the
output
po
wer
v
ersus
the
input
po
wer
.
A
K
e
ysight
E8244A
signal
generator
and
a
V
i
v
aT
ech
VTXF
A-06-12
signal
module
were
used
for
generating
input
signal
at
150
GHz
while
a
VDI
PM5-305V
po
wer
sensor
w
as
used
to
measure
the
output
po
wer
.
At
150
GHz,
the
designed
amplifier
obtains
a
OP1dB
of
approximately
1.5
dBm.
The
amplifier
consumes
a
lo
w
po
wer
of
27.3
mW
from
a
0.7
V
supply
v
oltage.
T
able
1
summarizes
the
performance
of
the
proposed
amplifier
and
compares
it
to
other
published
ones
operating
in
the
similar
frequenc
y
range.
Figure
5.
The
measured
and
simulated
S-parameter
of
the
D-band
amplifier
.
IJECE
V
ol.
8,
No.
2,
April
2018:
933
–
938
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
937
Figure
6.
The
measured
and
simulated
output
po
wer
v
ersus
the
input
po
wer
of
the
D-band
amplifier
.
4.
CONCLUSIONS
In
this
paper
,
we
ha
v
e
presented
the
designs
and
measurement
results
of
the
D-band
amplifier
tar
geted
for
ultrahigh-speed
wireless
communications.
The
proposed
amplifier
obtains
the
peak
g
ain
of
9.6
dB
o
v
er
the
-3
dB
bandwidth
from
138
GHz
to
164.5
GHz.
Supplied
by
the
0.7
V
supply
v
oltage,
the
amplifier
consumes
the
lo
w
po
wer
of
27.3
mW
while
its
core
occupies
the
chip
area
of
0.06
mm
2
.
A
CKNO
WLEDGEMENT
This
w
ork
w
as
supported
by
the
R&D
on
W
ireless
T
ranscei
v
er
Systems
with
CMOS
T
echnology
in
300-
GHz
Band,
as
part
of
an
R&D
program
on
K
e
y
T
echnology
in
T
erahertz
Frequenc
y
B
ands
of
the
Ministry
of
Internal
Af
f
airs
and
Communications,
Japan.
REFERENCES
[1]
H.-J.
Song,
J.-Y
.
Kim,
K.
Ajito,
N.
K
ukutsu,
and
M.
Y
aita,
50-gb/s
Direct
Con
v
ersion
QPSK
Modulator
and
Demodulator
MMICS
for
T
erahertz
Communications
at
300
GHz,
IEEE
T
ransactions
on
Micro
w
a
v
e
Theory
and
T
echniques
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62,
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3,
pp.
600-609,
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2014.
[2]
C.
W
ang,
B.
Lu,
C.
Lin,
Q.
Chen,
L.
Miao,
X.
Deng,
and
J.
Zhang,
0.34-THz
W
ireless
Link
Based
on
High-Order
Modulation
for
Future
W
ireless
Local
Area
Netw
ork
Applications,
IEEE
T
ransactions
on
T
erahertz
Science
and
T
echnology
,
v
ol.
4,
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1,
pp.
75-85,
January
2014.
[3]
K.
Katayama,
K.
T
akano,
S.
Amaka
w
a,
S.
Hara,
A.
Kasamatsu,
K.
Mizuno,
K.
T
akahashi,
T
.
Y
oshida,
and
M.
Fujishima,
A
300GHz
40nm
CMOS
T
ransmitter
with
32-QAM
17.5Gb/s/ch
Capability
o
v
er
6
Channels,
2016
IEEE
International
Solid-State
Circuits
Conference
(ISSCC
2016)
,
pp.
342-343,
February
2016.
[4]
S.
Kang,
S.
V
.
Th
yag
arajan,
and
A.
M.
Niknejad,
A
240GHz
W
ideband
QPSK
T
ransmitter
in
65nm
CMOS,
2014
IEEE
Radio
Frequenc
y
Inte
grated
Circuits
Symposium
(RFIC
2014)
,
pp.
353-356,
June
2014.
[5]
S.
Hara,
I.
W
atanabe,
N.
Sekine,
A.
Kasamatsu,
K.
Katayama,
K.
T
akano,
T
.
Y
oshida,
S.
Amaka
w
a,
and
M.
Fujishima,
Compact
138-GHz
Amplifier
with
18-Db
Peak
Gain
and
27-GHz
3-dB
Bandwidth,
2015
IEEE
Inter
-
national
Symposium
on
Radio-Frequenc
y
Inte
gration
T
echnology
(RFIT
2015)
,
pp.
55-57,
August
2015.
[6]
S.
Amaka
w
a,
R.
Goda,
K.
Katayama,
K.
T
akano,
T
.
Y
oshida,
and
M.
Fujishima,
W
ideband
CMOS
Decoupling
Po
wer
Line
for
Millimeter
-w
a
v
e
Applicationss,
2015
IEEE
MTT
-S
International
Micro
w
a
v
e
Symposium
(IMS
2015)
,
pp.
1-5,
May
2015.
[7]
N.
Deferm
and
P
.
Re
ynaer
,
”CMOS
Front
Ends
for
Millimeter
W
a
v
e
W
ireless
Communication
Systems,
”
Springer
International
Publishing
,
2015.
[8]
M.
Fujishima,
M.
Moto
yoshi,
K.
Katayama,
K.
T
akano,
N.
Ono,
and
R.
Fujimoto,
98
mW
10
Gbps
W
ireless
T
ranscei
v
er
Chipset
with
D-Band
CMOS
Ci
rcuits,
IEEE
Journal
of
Solid-State
Circuits
,
v
ol.
48,
no.
10,
pp.
Low-P
ower
D-Band
CMOS
Amplifier
for
Ultr
ahigh-Speed
W
ir
eless
...
(T
uan
Anh
V
u)
Evaluation Warning : The document was created with Spire.PDF for Python.
938
ISSN:
2088-8708
2273-2284,
October
2013.
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Hara,
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T
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I.
W
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N.
Sekine,
A.
Kasamatsu,
T
.
Y
oshida,
S.
Amaka
w
a,
and
M.
Fujishima,
Compact
160-GHz
Amplifier
with
15-Db
Peak
Gain
and
41-GHz
3-db
Bandwidth,
2015
IEEE
Radio
Frequenc
y
Inte
grated
Circuits
Symposium
(RFIC
2015)
,
pp.
1-4,
May
2015.
[10]
Z.
Xu,
Q.
J.
Gu,
and
M.
F
.
Chang,
A
Three
Stage,
Fully
Dif
ferential
128-157
GHz
CMOS
Amplifier
with
W
ide
Band
Matching,
IEEE
Micro
w
a
v
e
and
W
ireless
Components
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,
v
ol.
21,
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1,
pp.
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October
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[11]
Z.
Xu,
Q.
J.
Gu,
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M.
F
.
Chang,
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Amplifier
W
orking
Close
to
De
vice
f
T
,
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ol.
47,
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11,
pp.
639641,
August
2011.
[12]
C.
H.
Li,
C.
W
.
Lai,
and
C.
N.
K
uo,
A
147
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ferential
D-Band
Amplifier
Design
in
65-nm
CMOS,
2013
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acific
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w
a
v
e
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691693,
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ember
2013.
BIOGRAPHIES
OF
A
UTHORS
T
uan
Anh
V
u
recei
v
ed
the
B.S
de
gree
and
M.Sc
de
gree
in
Electronics
and
T
elecommunications
T
echnology
from
Uni
v
ersity
of
Engineering
and
T
echnology
,
V
ietnam
National
Uni
v
ersity
in
2006
and
2009,
respecti
v
ely
.
In
2013,
he
recei
v
ed
Ph.D
de
gree
in
the
field
of
analog/mix
ed-signal
RF
nanoelectronics
from
Uni
v
ersity
of
Oslo,
Norw
ay
.
Since
2014,
he
has
been
a
lecturer
at
F
aculty
of
Electronics
and
T
elecommunications,
VNU
Uni
v
ersity
of
Engineering
and
T
echnology
.
Dr
.
T
uan
Anh
V
u
w
as
doing
postdoc
at
Department
of
Semiconductor
Electronics
and
Inte
gration
Science,
Hiroshima
Uni
v
ersity
,
Japan.
His
research
interests
are
analog
RF
inte
grated
c
ircuit
designs
includ-
ing
po
wer
amplifiers,
lo
w
noise
amplifiers,
mix
ers,
frequenc
y
multipliers,
etc.
K
y
oya
T
akano
recei
v
ed
the
B.E.,
M.E.,
and
Ph.D.
de
grees
in
electrical
engineering
from
the
Uni-
v
ersity
of
T
ok
yo,
T
ok
yo,
Japan
in
2006,
2008,
and
2012,
respecti
v
ely
.
He
joined
Hiroshima
Uni-
v
ersity
,
Hig
ashi-hiroshima,
Japan,
as
an
Assistant
Professor
in
2012.
His
current
research
interests
include
design
and
modeling
of
millimeter
-w
a
v
e
and
terahertz
CMOS
circuits.
Minoru
Fujishima
recei
v
ed
his
B.E.,
M.E.
and
Ph.D.
de
grees
in
Electronics
Engineering
from
the
Uni
v
ersity
of
T
ok
yo,
Japan,
in
1988,
1990
and
1993,
respecti
v
ely
.
He
joined
the
f
aculty
of
the
Uni
v
ersity
of
T
ok
yo
in
1988
as
a
research
associate
and
w
as
a
n
associate
professor
of
the
School
of
Frontier
Sciences,
Uni
v
ersity
of
T
ok
yo.
He
w
as
a
visiting
professor
at
the
ESA
T
-MICAS
Lab-
oratory
,
Katholiek
e
Uni
v
ersiteit
Leuv
en,
Belgium,
from
1998
to
2000.
Since
2009,
he
has
been
a
professor
of
the
Graduate
School
of
Adv
anced
Sciences
of
Matter
,
Hiroshima
Uni
v
ersity
.
He
is
currently
serving
as
a
technical
committee
member
of
se
v
eral
international
conferences.
His
current
research
interests
are
in
the
design
of
lo
w-po
wer
ultrahigh-speed
millimeter
-
and
short-millimeter
-
w
a
v
e
wireless
CMOS
circuits.
He
is
a
member
of
IEEE
and
JSAP
.
IJECE
V
ol.
8,
No.
2,
April
2018:
933
–
938
Evaluation Warning : The document was created with Spire.PDF for Python.