Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
6, N
o
. 2
,
A
p
r
il
201
6, p
p
.
89
5
~
90
0
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
2.4
07
8
95
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Influence of Gate Material a
nd Process
on Juncti
onless F
E
T
Subthreshold Performance
Mun
a
w
a
r
A
Ri
y
a
di
,
Iraw
a
n
D
Su
kaw
a
ti
,
T
e
guh
Pr
ak
o
s
o,
D
a
rj
at
Department o
f
Electrical Engin
e
eri
ng, Dipon
egor
o University
, Ind
onesia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Sep 19, 2015
Rev
i
sed
D
ec 27
, 20
15
Accepte
d
Ja
n 18, 2016
The r
ecen
t progr
es
s
of dim
e
ns
ion s
caling
of e
l
e
c
tr
onic dev
i
c
e
in
to
nano s
cal
e
has
m
o
tivated
th
e inven
tion of
al
terna
tive m
a
teri
a
l
s
and s
t
ructur
es
. One new
device that shows great poten
tial to
prolong
th
e scaling is junctionless FET
(JLFET). In co
ntrast to conv
en
ti
onal MOSFETs, JLFET does not requir
e
steep junction fo
r source and drain. The
d
e
vice processing di
rectly
influ
e
nce
the p
e
rform
anc
e
,
ther
efore
it
is cruc
ial
to u
nderstand
the r
o
le of
ga
t
e
processing in
JLFET.
This pap
e
r
investig
at
es the
influ
e
nce
of g
a
te m
a
t
e
ri
al
and process on subthreshold per
f
o
rmance
of jun
c
tionless FET, b
y
comparing
four sets of gate properties and
proce
ss techniqu
es. Th
e result shows that in
terms of subthr
eshold slope, JLFET a
pproach
es near ideal value of 60
m
V
/decade
,
which is superior than th
e SOI FET for sim
ilar doping rate. On
the o
t
her h
a
nd, the thr
e
shold value s
hows differ
e
nt tendenc
ies
b
e
t
w
een thos
e
ty
p
e
s of d
e
vice.
Keyword:
Gate m
a
terial
In
-si
t
u
d
opi
ng
Jun
c
t
i
onl
ess
F
ET
SOI
Sub
t
hr
esho
ld per
f
o
r
m
a
n
c
e
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
M
una
war
A
R
i
y
a
di
,
Depa
rt
m
e
nt
of
El
ect
ri
cal
Engi
neeri
n
g
,
Dipo
n
e
go
ro
Un
iv
ersity,
Kam
pus Tem
b
al
ang,
Sem
a
rang
,
In
d
onesi
a.
Em
a
il: m
u
n
a
war@u
n
d
i
p.ac.i
d
1.
INTRODUCTION
Ul
t
r
a-s
h
ar
p
j
u
nct
i
o
n
s
i
n
so
u
r
ce a
n
d
d
r
ai
n
are e
x
t
r
em
el
y
im
port
a
nt
i
n
m
e
t
a
l
oxi
de se
m
i
cond
uct
o
r
field effect transistor (M
OSFET
)
especi
ally at nanos
cale dim
e
nsion as
it direct
ly affect the
ove
rall
per
f
o
r
m
a
nce. For
exam
pl
e, t
h
e s
p
rea
d
o
f
d
opa
nt
i
n
a
9
0
-
n
m
t
echnol
o
g
y
m
a
y
affect
t
h
e sprea
d
of t
h
r
e
sh
ol
d
vol
t
a
ge (
V
T
)
up to
30
m
V
[1
].
Th
is d
e
v
i
ation
in
tu
rn
tri
g
g
e
rs ch
ang
e
s i
n
curren
t th
at in
su
ch
circu
m
stan
ce
m
a
y
lead to catastrophic problem
in the
chi
p
. U
n
f
o
rt
unat
e
l
y
, wi
t
h
t
h
e co
nt
i
n
uo
us scal
i
ng i
n
t
h
e devi
ce di
m
e
nsi
o
n
,
t
h
e co
ncent
r
at
i
on
di
st
ri
b
u
t
i
o
n
req
u
i
r
em
ent
of sha
r
p
ju
nct
i
o
n i
s
har
d
t
o
h
a
ndl
e f
u
rt
her
,
especi
al
l
y
whe
n
t
h
e
scal
i
ng rea
c
h
nan
o
m
e
t
e
r regi
m
e
. One e
x
ci
t
i
ng a
p
pr
oac
h
t
o
ove
rc
om
e t
h
i
s
shar
p
ju
nct
i
o
n
scal
i
ng
pr
obl
e
m
i
s
by
usi
n
g
ju
nc
t
i
onl
ess fi
el
d
effect
t
r
a
n
si
st
or (
J
LFE
T
).
I
n
co
nt
rast
t
o
t
h
e con
v
e
n
t
i
onal
M
O
SFE
T, t
h
e
junctionless transistor uses
a stru
cture with
ou
t semico
nd
u
c
t
o
r
j
u
n
c
tion
s
either in the cha
nnel
-
source or
chan
nel
-
drai
n
regi
ons
[2]
.
There
f
ore, a
hom
oge
neo
u
s
t
y
pe of d
o
p
i
ng an
d co
nc
ent
r
at
i
o
n are
appl
i
e
d
t
h
r
o
u
g
h
o
u
t
t
h
e
s
e
re
gi
o
n
s,
t
h
u
s
el
im
i
n
at
i
ng
t
h
e need
s of ul
t
r
a-s
h
ar
p so
urce
an
d drai
n ju
nc
t
i
ons.
The
ju
nct
i
o
nl
e
ss FET
o
ffe
rs
m
a
ny
adva
nt
a
g
es.
Fi
rst
l
y
, i
t
s
fab
r
i
cat
i
o
n
p
r
ocess
w
oul
d b
e
easi
e
r t
h
a
n
th
e conv
en
tional MOSFETs
as th
e in
t
r
i
cat
e d
opi
ng
p
r
oce
s
s f
o
r s
o
urce
a
n
d
d
r
ai
n i
s
a
v
oi
de
d.
Seco
n
d
l
y
, t
h
e
electric field
i
n
th
e ON-state of th
e d
e
v
i
ce is low
[3
].
Th
ird
l
y, th
e mo
b
ility in
JLFET is im
p
r
ov
ed
an
d
insensitive to t
h
e interface of gate
oxide to
channel due to its bulk co
nduction,
unlike surface conduct
i
on i
n
t
h
e i
n
versi
o
n
m
ode devi
ce,
e.g.
M
O
S
F
ET
[4]
.
It
al
so
o
f
f
e
rs m
o
re r
o
bu
s
t
desi
g
n
as
i
t
i
s
si
m
p
l
e
t
o
pr
o
duce
i
n
thin silicon lay
e
r.
Othe
r a
d
va
ntage
is
on the
possibility to reach
faster swi
t
ching that ca
n be
m
a
nifested
in the
lowe
r subthre
s
hol
d slope
. For MOSFET, the
ideal value
is
60 m
V
/decade. Howeve
r,
in reality,
many devices
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 2, A
p
ri
l
20
16
:
89
5 – 9
0
0
89
6
cannot m
eet this value due to severa
l reasons, on
e of wh
ich
is th
e in
flu
e
nce of interfac
e trap. As the JLFET
doe
s
not
rely on s
u
rface/interface m
echanis
m, it is expected
that its slope c
oul
d
be closer t
o
the
ideal
value.
A n
u
m
b
er o
f
J
L
FET st
r
u
ct
u
r
es ha
ve bee
n
p
r
o
p
o
sed
wi
t
h
v
a
ri
at
i
ons i
n
t
o
p
o
l
o
gi
es, s
u
c
h
a
s
si
ngl
e
gat
e
b
u
l
k
p
l
an
ar JLFET[3
]
, sing
le g
a
te silico
n
-
on
-i
n
s
u
l
ator
(SOI) JLFET
[4],
m
u
lti-g
a
te n
a
n
o
wire
j
u
n
c
tio
n
l
ess
t
r
ansi
st
o
r
s [
5
]
,
gat
e
-al
l
-
ar
o
u
n
d
na
n
o
wi
re j
u
nct
i
onl
ess t
r
an
si
st
ors[
6]
, as
wel
l
as j
unct
i
o
nl
ess t
u
nnel
F
ET[
7]
.
Howev
e
r, little
atten
tio
n
is
g
i
v
e
n on
th
e g
a
t
e
m
a
terials
in
JLFET as well
as th
e
p
r
o
cessin
g
sequ
en
ce on
th
e
gate.
It is
broa
dly accepte
d t
h
at the
de
vice
processi
ng infl
uence
s
the
pe
rf
orm
a
nce, therefore it is c
r
uc
ial to
un
de
rst
a
n
d
t
h
e
rol
e
of
gat
e
p
r
o
cessi
ng
i
n
JLF
ET.
Ou
r
pre
v
i
o
us
pape
r
rep
o
rt
e
d
t
h
e s
ubt
hres
h
o
l
d
per
f
o
rm
ance of
j
u
nct
i
onl
ess t
r
an
si
st
or i
n
c
o
m
p
ari
s
o
n
wi
t
h
S
O
I M
O
SFET
FET.
T
h
e
per
f
o
r
m
a
nces we
re e
x
t
r
ac
t
e
d f
o
r
gat
e
l
e
ngt
hs
of
50
-2
0
0
nm
t
o
o
b
ser
v
e t
h
e
sho
r
t
cha
n
nel
e
ffect
s,
fo
r si
ngl
e t
h
i
c
k
n
ess
of
oxi
de,
t
ox
, a
nd
wi
t
h
fi
xed c
h
a
nnel
do
pi
ng
N
A
[8]
.
In t
h
is pa
p
e
r,
we
elab
orate th
e v
a
riation
of materials fo
r g
a
te, wh
ich
i
s
cru
c
ial in
d
e
term
in
in
g
th
e th
resho
l
d
v
o
ltag
e
.
Furt
herm
ore,
d
i
ffere
nt
t
h
i
c
kn
esses o
f
oxi
de
were
al
so c
h
o
s
en i
n
o
r
der t
o
u
nde
rst
a
n
d
br
oade
r as
pect
o
f
t
h
e
devi
ce pe
rf
orm
a
nce.
2.
R
E
SEARC
H M
ETHOD
Jun
c
t
i
onl
ess
F
ET
does
not
re
qui
re a
n
y
ju
nct
i
on
i
n
t
h
e c
h
a
n
nel
bet
w
ee
n s
o
urce
an
d
d
r
ai
n.
The
r
ef
o
r
e,
j
u
nctionless transistor operat
es in accum
u
lation m
ode
. Figure 1 (a
) illustrates
an n-channel
junctionless
t
r
ansi
st
o
r
w
h
i
c
h ha
s an
N+
–
N
+–
N+
do
pe
d
st
ruct
u
r
e f
o
r t
h
e so
urce, c
h
a
n
nel
an
d d
r
ai
n
r
e
gi
o
n
,
whi
l
e
Fi
gu
re
1
(b
) s
h
o
w
s t
h
e
con
v
e
n
t
i
onal
M
O
SFET
w
h
i
c
h
wo
rk
s i
n
i
nve
rsi
o
n m
ode
. Fo
r
g
o
o
d
el
e
c
t
r
i
cal
ope
rat
i
o
n
,
t
h
e
j
u
n
c
tion
l
ess tran
sistor sho
u
l
d
m
eet
sp
ecific co
nd
itio
ns: fi
rst, v
e
ry th
in
semico
n
d
u
c
ting
layer is essen
tial fo
r
drai
n, c
h
an
nel
,
and
so
urce
re
gi
o
n
s t
o
ac
hi
e
v
e f
u
l
l
de
pl
et
i
on i
n
O
F
F
-
st
at
e. Lat
e
r,
hi
g
h
do
pi
n
g
c
onc
en
t
r
at
i
o
n
(~1
0
19
-1
0
20
cm
-3
) is requ
ired
i
n
th
e sem
i
co
n
d
u
c
tin
g layer to
ach
iev
e
suffici
en
tly h
i
gh
ON-cu
r
ren
t
[9
,
10
].
Fi
gu
re
1.
C
r
os
s sect
i
o
n
o
f
FE
T-ba
sed
de
vi
ce
s:
(a)
JLFE
T,
(
b
)
i
n
versi
o
n
-
m
ode
FET
[
1
0]
Ju
nctio
n
l
ess FET requ
ires
d
i
electric iso
l
ati
o
n
u
n
d
e
r th
e se
m
i
co
n
d
u
c
tor layer, similar
with
th
e SOI
M
O
SFET
.
A
s
t
h
e sem
i
cond
uct
i
ng l
a
y
e
r l
i
es on t
op
o
f
di
el
ect
ri
c i
n
su
l
a
t
i
on, t
h
e c
h
annel
i
s
el
ect
r
i
cally
in
su
lated
to
t
h
e su
b
s
t
r
ate. The th
ick
n
e
ss and
dop
ing
co
n
c
en
tration
of the silico
n
layer d
e
term
in
e wh
eth
e
r th
e
chan
nel
i
s
i
n
ful
l
y
de
pl
et
ed
(F
D)
or
pa
rt
i
a
l
l
y
depl
et
ed (
P
D)
o
p
erat
i
o
n
m
ode. If t
h
e
sem
i
cond
uct
o
r
l
a
y
e
r
th
ick
n
e
ss is less th
an
th
e m
a
x
i
m
u
m
d
e
p
l
etion
,
, it is i
n
th
e
FD m
o
d
e
,
wh
i
l
e th
ick
e
r layer en
su
res it in
PD m
ode. Ho
weve
r, t
h
e
r
e ar
e st
ark con
s
t
r
a
s
t
s
bet
w
een S
O
I FET a
nd JL
FET. I
n
ad
di
t
i
on t
o
hi
gh s
o
u
r
ce/
drai
n
do
pi
n
g
re
qui
re
m
e
nt
(o
f
di
ffe
r
e
nt
t
y
pe
wi
t
h
c
h
an
nel
)
, S
O
I
F
ET u
s
ual
l
y
em
pl
oy
s l
o
w
o
r
e
v
en
u
n
d
o
p
e
d
c
h
an
nel
,
whi
l
e
JLFE
T r
e
qui
res hi
gh
d
opi
ng
fo
r al
l
so
urce
-cha
n
n
el
-
d
rain
reg
i
on
s. Th
e th
ickn
ess
o
f
se
m
i
co
n
d
u
c
tor layer
to
ach
iev
e
fu
ll
d
e
p
l
etion
(b
oth
for FD SOI FET and
JLFET) sh
ou
ld
b
e
less th
an
th
ick
n
e
ss of m
a
x
i
m
u
m
depl
et
i
o
n
, calcu
lated
fro
m
th
e fo
llo
wi
n
g
fo
rm
u
l
a
:
4
(1
)
whe
r
e
is th
e
p
e
rm
itt
iv
ity o
f
silico
n
,
q
is t
h
e electron
charge
,
is th
e im
p
u
r
ity co
n
c
en
tration
o
f
t
h
e
sem
i
cond
uct
o
r
l
a
y
e
r, an
d
is th
e Ferm
i lev
e
l. Acco
rd
ing
to
Eq.
(1), t
h
e requ
irem
en
t of h
i
g
h
dop
ing
in
JLFET im
p
lies th
e silicon
layer sh
ou
ld b
e
v
e
ry th
in.
Th
e off state o
f
JLFET is d
u
e
to
th
e
m
ech
an
is
m
o
f
fu
ll d
e
pletio
n
o
f
th
e chan
n
e
l. Th
is is i
n
con
t
rast wit
h
t
h
e co
nve
nt
i
o
n
a
l
M
O
SFET t
h
at
i
s
based o
n
t
h
e re
verse
bi
as
of t
h
e j
u
nct
i
o
n. T
h
e de
pl
et
i
o
n m
echani
s
m
is due
t
o
t
h
e di
ffe
re
n
ce bet
w
een t
h
e gat
e
and t
h
e
chan
nel
wo
rk
fu
nct
i
o
ns. T
h
e
use of di
ffe
re
nt
gat
e
m
a
t
e
rial
can
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Inf
l
u
e
n
ce of
G
a
t
e
M
a
t
e
ri
al
a
n
d
Pr
ocess o
n
Junct
i
o
nl
ess F
E
T Su
bt
hre
s
h
o
l
d
…
(
M
u
n
a
w
a
r
A
Ri
y
adi
)
89
7
resu
lt in d
i
fferen
t way
o
f
how th
e
JLT
work
s. In
t
h
e case o
f
P+
po
lysilico
n
g
a
te electrod
e
, the d
e
v
i
ce is
tu
rn
ed
o
n
wh
en
th
e gate electrod
e
is con
n
e
cted
to
po
sitive v
o
ltag
e
equ
a
l o
r
larg
er th
an th
e flatb
a
nd
vo
ltag
e
,
an
d conv
ersely
fo
r t
h
e
g
a
te el
ectrod
e
is
o
f
N+ po
lysilico
n
[9
].
The
pr
ocessi
n
g
se
que
nce
of
JLFET
was s
i
m
u
l
a
t
e
d by
u
s
i
ng TC
A
D
t
o
ol
s (
A
t
h
e
n
a)
f
o
l
l
o
we
d
by
electrical ch
aracterizatio
n
o
f
its su
b
t
h
r
esho
ld
p
e
rform
a
n
ce b
y
u
s
in
g
Atlas.
Th
e th
in
silicon
ep
itax
i
al laye
r was
g
r
o
w
n
on
top
o
f
silicon
ox
ide wh
ich
serv
es as d
i
electri
c insu
lato
r, fo
llowed
b
y
g
r
owing
g
a
te ox
id
e layer with
d
r
y
ox
id
ation
p
r
o
cess to
create th
e fi
el
d e
f
fect transistor
mechanism
.
Th
e selected tran
sport m
o
d
e
l
was
d
r
i
f
t-
di
ff
usi
on
base
d
on B
o
l
t
z
m
a
nn
carri
er st
at
i
s
t
i
c
s, al
on
g
wi
t
h
t
h
e S
hoc
kl
ey
-R
ead-
H
al
l
R
eco
m
b
i
n
at
i
on wi
t
h
fi
xed
carri
er
l
i
f
et
im
es m
odel
s
. I
n
a
d
di
t
i
on,
t
h
e
com
b
i
n
at
i
o
n
of
G
u
m
m
e
l
and
Ne
w
t
on
n
u
m
e
ri
cal
m
e
t
hods
we
re
use
d
.
The
gat
e
m
a
t
e
ri
al
of JLFE
T i
s
bel
i
e
ve
d t
o
b
e
one i
m
port
a
n
t
aspect
i
n
det
e
rm
i
n
i
ng t
h
e s
ubt
hres
h
o
l
d
per
f
o
r
m
a
nces.
There
f
ore,
t
h
i
s
researc
h
c
o
nd
uct
e
d t
h
e si
m
u
l
a
t
i
on o
n
t
h
e g
a
t
e
m
a
t
e
ri
al
vari
at
i
on t
o
fi
nd
out
t
h
e
i
m
p
act o
f
m
a
t
e
rial ch
an
g
i
n
g
. Two
d
i
fferen
t g
a
te m
a
terials
were sim
u
late
d
:
po
lysilico
n
an
d alu
m
in
u
m
.
The
wo
rk
-f
u
n
ct
i
o
n fo
r b
o
t
h
m
a
t
e
rial
s are di
ffere
n
t
, t
hus t
h
e fl
at
-
b
an
d v
o
l
t
a
ge i
s
sup
p
o
s
ed t
o
c
h
an
ge de
pe
ndi
ng
on
h
o
w m
u
ch
th
e
d
i
fferen
ce is. In
add
ition
,
th
e
way th
e
p
o
l
ycilico
n
is created
m
a
y co
m
e
as a sou
r
ce
o
f
v
a
riatio
n
in
th
e
p
e
rforman
ce.
Th
e d
i
fferen
ce b
e
tween
in
-situ
d
o
p
e
d
po
lysilico
n
and
so
urce-dra
in
self-alig
n
e
d
im
p
l
an
ted
doping of polysilicon is thought as crucia
l in th
e nano regim
e
. As a com
p
arison,
SOI F
ET was
also
sim
u
l
a
t
e
d. The
r
ef
ore
,
we
set
up
f
o
u
r
set
s
o
f
gat
e
m
a
t
e
ri
al
s t
o
be c
o
m
p
ared. Ta
bl
e
4.
3 s
h
ows
t
h
e c
o
m
p
ari
s
o
n
of
pa
ram
e
t
e
rs use
d
f
o
r eac
h
d
e
vi
ce.
Tabl
e
1.
Vari
at
i
on
o
f
param
e
ters i
n
si
m
u
l
a
t
i
on
o
f
S
O
I a
n
d
JL-FE
T
SOI-
base
d
JLT-
pol
y g
a
t
e
JLT-
in situ
ga
te
JLT-
meta
l g
a
t
e
Lg
(n
m
)
5
0
/
1
0
0
/
200
5
0
/
1
0
0
/
200
5
0
/
1
0
0
/
200
5
0
/
1
0
0
/
200
t
ox
(nm
)
3/
5/
7
3/
5/
7
3/
5/
7
3/
5/
7
tsi
(nm
)
3,
2/
1
2
,
8
/
2
2,
9/
3/
5/
1
0
3/
5/
1
0
3/
5/
1
0
N
A
(cm
-3
)
1,
58
x
1
0
14
/
1,
58
x
1
0
15
/
1,
58
x
1
0
16
/
1,
99
x
1
0
17
/
1,
99
x
1
0
18
/
1,
99
x
1
0
19
1,
99
x
1
0
17
/
1,
99
x
1
0
18
/
1,
99
x
1
0
19
1,
99
x
1
0
17
/
1,
99
x
1
0
18
/
1,
99
x
1
0
19
3.
R
E
SU
LTS AN
D ANA
LY
SIS
The re
sul
t
o
f
subt
hre
s
h
o
l
d
s
i
m
u
l
a
t
i
on i
s
sho
w
n i
n
Fi
gu
r
e
2 f
o
r J
L
FE
T an
d SO
I F
ET wi
t
h
fo
u
r
di
ffe
re
nt
m
a
t
e
r
i
al
pr
ocesses
f
o
r
gat
e
,
eval
ua
t
e
d f
o
r
ef
fect
i
v
e cha
nnel
l
e
n
g
t
h L=
50
-2
0
0
n
m
and t
h
e e
ffe
ct
i
v
e
chan
nel
d
opi
n
g
N
A
=
3.98.10
16
cm
-3
. The
re
sult shows t
h
e
com
p
arison
of
Ig
-V
ds
cu
rve
s
of
all struct
ure
s
wit
h
t
h
e drai
n v
o
l
t
a
ge V
D
=
1
V. T
h
e t
h
re
sh
ol
d
v
o
l
t
a
ge r
o
l
l
-
o
ff
was f
o
un
d f
o
r
al
l
t
y
pes of de
vi
ce, b
u
t
wi
t
h
di
ffe
re
n
t
t
e
nde
nci
e
s, as
de
pi
ct
ed i
n
Fi
gu
re
2.
The
SO
I F
ET
pr
od
uces
l
o
wer
t
h
res
hol
d
vol
t
a
ge. M
o
re
o
v
er
, i
n
t
h
e
red
u
ct
i
o
n of c
h
an
nel
l
e
ngt
h,
i
t
s
val
u
e fo
r V
T
decreases wi
th larger ste
p
than
its JLFET
co
un
terp
arts. On
th
e
ot
he
r si
de, al
l
vari
a
n
t
s
of J
L
FET y
i
el
d i
n
h
i
ghe
r V
T
v
a
l
u
es th
at in
crease in
th
e sho
r
ter ch
ann
e
l leng
th
. Th
e
val
u
e o
f
V
T
is
h
eav
ily related to
th
e ch
ann
e
l do
p
i
n
g
as
well as th
e
work
fu
n
c
tion
of th
e
g
a
te.
In
t
h
is case, the
p
o
l
ysilico
n
g
a
te o
f
SOI-b
a
sed an
d
p
o
l
ysilicon
-b
ased
JLFET stru
ctures are d
o
p
e
d
with
10
18
cm
-3
of As,
whil
e
al
um
i
num
i
s
subject
e
d
fo
r m
e
tal
-
base
d JL
FE
T.
Fi
gu
re
2.
C
o
m
p
ari
s
on
o
f
t
h
re
shol
d
v
o
l
t
a
ge f
o
r
JLFE
T
vari
a
n
t
s
a
n
d
S
O
I
FE
T wi
t
h
t
ox
= 3 nm
0
0.2
0.4
0.6
0.8
1
0
5
0
100
150
200
250
Vt
(volt)
Lg
(nm)
SOI
‐
based
JLT
‐
based
JLT
‐
in
situ
gate
JLT
‐
metal
gate
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 2, A
p
ri
l
20
16
:
89
5 – 9
0
0
89
8
Fi
gu
re
3.
C
o
m
p
ari
s
on
o
f
s
u
bt
hres
h
o
l
d
sl
o
p
e
fo
r JL
FET
va
ri
ant
s
a
n
d
S
O
I
F
ET at
se
veral
g
a
t
e
l
e
ngt
hs
Wh
en
th
e ch
an
n
e
l leng
th
is
g
e
ttin
g
sm
aller
,
th
e sub
t
hresho
ld
slop
e
v
a
lue for all stru
ctu
r
es i
n
crease
as re
veal
ed
i
n
Fi
gu
re
3.
H
o
w
e
ver
,
t
h
e
sl
o
p
e
val
u
es
fo
r JLFET
v
a
rian
ts are
g
e
n
e
rally lower th
an
th
at
o
f
SOI
b
a
sed
d
e
v
i
ce,
with
th
e
slop
e
v
a
lu
e app
r
o
a
chin
g
n
ear id
eal
v
a
lu
e
o
f
60
mV/d
ecad
e
.
In
ad
d
ition
,
t
h
e variatio
n
for bo
th
sub
t
hresho
ld
slop
e an
d
t
h
resho
l
d
vo
ltag
e
fo
r JLT v
a
rian
ts are si
milar o
r
sm
al
l
e
r th
an
th
e SOI FET
for sim
ilar d
o
p
in
g
rate an
d
oxid
e
th
ickn
ess.
Th
is fi
nd
in
g s
h
ows t
h
e
real
adva
ntage
of J
L
FET t
h
at it can turn
t
h
e de
vi
ce o
n
or
of
f fast
e
r
w
h
en
use
d
f
o
r s
w
i
t
c
hi
n
g
. T
h
e
faster slope is
due t
o
th
e
b
u
l
k tran
sp
ort m
e
c
h
an
ism
use
d
in JLFE
T that the current fl
ows i
n
all part of
t
h
e
conducting c
h
annel, in
c
ontrast to the surface
co
ndu
ctio
n en
du
red
i
n
co
nv
entio
n
a
l MOSFET as
well as SOI
FET.
The i
n
fl
uence
of di
ffe
rent
o
x
i
de t
h
i
c
kne
ss was al
so i
n
ves
t
i
g
at
ed. The si
m
u
l
a
t
i
on sh
ow
n i
n
Fi
gu
re 4
in
d
i
cates th
at th
e JLFET wi
th
p
o
l
ysilico
n
g
a
te ch
ang
e
its th
resh
o
l
d
v
o
ltag
e
faster th
an
its
m
e
t
a
l g
a
te
co
un
terp
art i
n
b
r
o
a
d
rang
e of
ch
ann
e
l leng
th
wh
en
t
h
e ox
ide th
ickn
ess is
red
u
c
ed
. On
th
e
o
t
h
e
r h
a
nd
, t
h
e SOI
b
a
se
d
e
v
i
ce sho
w
s rat
h
er small v
a
riatio
n in th
resho
l
d vo
ltag
e
i
n
th
e redu
ced ox
i
d
e th
i
c
k
n
e
ss.
Sm
alle
r tox
p
r
od
u
ces l
o
wer th
resho
l
d
vo
ltag
e
fo
r bo
th
m
e
tal an
d
p
o
l
ysilico
n
g
a
tes. In
ad
d
ition
,
bo
th
materials
su
ffer
fro
m
v
o
ltag
e
ro
ll-off in
sho
r
t ch
annel. Th
is find
ing
und
erlin
es t
h
e i
m
p
o
r
tan
ce
of tak
i
ng
sm
alle
r ox
id
e th
ick
n
e
ss in
th
e redu
ction
o
f
ch
ann
e
l leng
th
, as
h
a
s
b
e
en
propo
se
d s
e
veral
dec
a
des
ago
by
De
nn
ard
fo
r co
n
v
e
n
t
i
onal
MOSFET, to
main
tain
th
e near con
s
tan
t
field
alo
n
g
th
e ch
ann
e
l.
In
simu
ltan
e
ou
s co
mb
in
ation
of L
an
d
t
ox
red
u
ct
i
o
ns f
o
r
JLFET, t
h
e c
h
ange
of V
T
can
b
e
m
a
in
tain
e
d
sm
a
ll, as th
e
in
crease o
f
V
T
due t
o
L scal
i
ng i
s
com
p
ensated by
the
decrease of V
T
du
e to
t
ox
redu
ctio
n. Howev
e
r,
for th
e
si
m
ilar scen
ario
in
SOI-b
ased FET,
th
e V
T
ro
ll-o
f
f is
am
p
lified
.
Fi
gu
re
4.
T
h
re
shol
d
v
o
l
t
a
ge s
h
i
f
t
due
t
o
o
x
i
d
e t
h
i
c
k
n
ess
va
r
i
at
i
on f
o
r
JLF
E
T an
d
SO
I F
E
T
60
65
70
75
80
0
5
0
100
150
200
250
S
(mV/decade
Lg
(nm)
SOI
‐
based
JLT
‐
based
JLT
‐
in
situ
gate
JLT
‐
metal
gate
0
0.2
0.4
0.6
0.8
1
1.2
2
3456
78
Vt
(volt)
t
ox
(nm)
SOI
‐
based
JLT
‐
based
JLT
‐
in
situ
gate
JLT
‐
metal
gate
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Inf
l
u
e
n
ce of
G
a
t
e
M
a
t
e
ri
al
a
n
d
Pr
ocess o
n
Junct
i
o
nl
ess F
E
T Su
bt
hre
s
h
o
l
d
…
(
M
u
n
a
w
a
r
A
Ri
y
adi
)
89
9
Fi
gu
re 5.
S
u
bt
hres
h
o
l
d
sl
o
p
e shi
f
t
due
t
o
o
x
i
d
e
t
h
i
c
kne
ss va
ri
at
i
on fo
r
J
L
F
ET
an
d SO
I F
ET
The si
m
u
l
a
ti
on
s
h
ow
n
i
n
Fi
gu
re 5
re
veal
s
t
h
at
bot
h
t
h
e
SO
I FET
an
d vari
a
n
t
s
of
JLFET
wi
t
h
p
o
l
ysilico
n
g
a
t
e
ob
tain
l
o
wer
su
b
t
h
r
esho
ld slo
p
e
in
t
h
inn
e
r
silico
n
o
x
i
d
e
t
ox
. Th
is tend
en
cy is also
ev
id
en
t for
d
i
fferen
t
sets o
f
ch
an
n
e
l leng
th
. Sm
aller t
ox
produces lowe
r slope
, with the
tende
ncy of reaching ideal
value
fo
r t
o
x l
e
ss t
h
an
3 nm
. The
subt
hre
s
h
o
l
d
sl
ope
i
s
i
n
fl
ue
nc
ed
by
t
h
e c
h
an
nel
l
e
n
g
t
h
vari
at
i
on as
wel
l
a
s
t
h
e
g
a
te m
a
terials
u
s
ed
in
JLFET. Th
e slop
e,
S,
is risin
g
in
t
h
e
sh
orter ch
an
nel len
g
t
h L,
wh
ile th
e sm
al
ler o
x
i
d
e
th
ick
n
e
ss exh
i
b
it lo
wer
slope, wh
ich is
b
e
tter. Sm
alle
r tox produces
highe
r ca
pacitance
betwee
n
gate and
b
u
l
k
silicon
, t
h
erefore t
h
e ch
arg
e
un
d
e
r the ox
id
e layer
is u
n
d
e
r
g
r
eat
er con
t
ro
l
o
f
g
a
te fo
r inv
e
rsio
n
.
In
ad
d
ition
,
t
h
e
po
lysilico
n
-
b
a
sed
g
a
te sh
ows
better slo
p
e
th
an
th
e m
e
tal g
a
t
e
in
sho
r
t ch
ann
e
l leng
th
. Howev
e
r,
th
e
m
e
tal
g
a
te
b
a
sed
JLFET produ
ces simila
r slo
p
e
with
SOI FET in
th
ick
e
r ox
i
d
e. On
th
e o
t
h
e
r h
a
nd
,
eith
er
th
e
in
situ
o
r
do
p
e
d
po
lysilico
n
g
a
te
b
a
sed
JLFET
ach
i
ev
e
lo
wer slop
e, wh
ich
is m
o
re b
e
n
e
ficial.
B
a
sed o
n
t
h
e t
r
en
d of s
u
bt
h
r
esh
o
l
d
vari
at
i
ons i
n
t
h
e cha
nge
of c
h
an
ne
l
l
e
ngt
h as we
l
l
as oxi
de
thinni
ng, the s
h
ort cha
nnel e
ffect (SCE
) can be eval
ua
ted
furt
her f
o
r all
variants. T
h
e
SCE in subt
hr
esh
o
ld
per
f
o
r
m
a
nce i
s
evi
d
e
n
t
on t
h
e
vol
t
a
ge t
h
res
h
ol
d r
o
l
l
of
f an
d sl
o
p
e i
n
creas
e. Ho
we
ver
,
t
h
e op
po
si
n
g
t
e
n
d
ency
of V
T
cha
nge
betwee
n JLFETs and SOI FET leaves
di
ffe
re
nt scenario to resist against SCE
.
The
m
a
ni
fest
at
i
on of SC
E i
n
t
h
e form
of V
T
in
all
th
ree v
a
rian
ts o
f
JLFET can
b
e
main
tain
ed
small b
y
sim
u
l
t
a
neous
com
b
i
n
at
i
on o
f
L scal
i
ng a
nd
o
x
i
d
e t
h
i
n
ni
ng
th
at result in
ad
v
e
rse
d
i
rection
of thresho
l
d
change. The
r
efore
,
the voltage
roll-of
f is re
duced a
n
d eve
n
t
u
ally the shor
t
channel effect
(SCE) is m
i
nimized.
Howev
e
r, th
e
v
o
ltag
e
ro
ll-off in
SOI is
d
e
t
e
rio
r
ated
further with
t
h
e ox
i
d
e th
inn
i
n
g
com
b
in
ed
with
ch
ann
e
l
scaling, the
r
efore worsen the
SCE.
On t
h
e
o
t
her ha
n
d
, t
h
e t
r
en
d o
f
su
bt
hre
s
hol
d slope inc
r
ease due to channel
scalin
g
can
b
e
co
m
p
en
sated
with
th
e d
e
crease o
f
o
x
i
d
e
th
ickn
ess in
b
o
th
SOI and
JLFET, wit
h
th
e in
-situ
pol
y
gat
e
JLF
E
T as t
h
e
be
st
p
e
rf
orm
e
r bet
w
e
e
n t
h
ose
st
r
u
ct
ures
u
n
d
er
i
n
v
e
st
i
g
at
i
on.
Ov
erall, th
e JLFET offers b
e
t
t
er
perform
a
nce than SOI es
pecially
in
the SCE. Of J
L
FET
structures
,
t
h
e p
o
l
y
-
b
ased
JLFET
p
r
o
d
u
c
e
s sl
i
ght
l
y
bet
t
er
pr
om
i
s
i
ng p
e
rf
orm
a
nce t
h
a
n
i
m
pl
ant
e
d
po
l
y
-based
JLF
E
T,
but
out
per
f
o
r
m
t
h
e m
e
t
a
l
based
J
L
FET.
4.
CO
NCL
USI
O
N
The subthres
hold electrical perform
a
n
ces o
f
fo
ur d
i
fferen
t
sets o
f
FETs, i.e. SOI FET,
metal-b
a
sed
JLFET,
i
m
pl
ant
e
d
pol
y
-
base
d
FET
an
d i
n
-si
t
u p
o
l
y
-
b
ase
d
FET
ha
ve
bee
n
obt
ai
ned
an
d
eval
uat
e
d
f
o
r
L=5
0
-
20
0
nm
usi
ng
TC
AD t
ool
s
.
I
n
fl
uence
of
di
f
f
ere
n
t
o
x
i
d
e t
h
i
c
kness a
n
d t
h
e scal
i
ng e
ffect
were i
nvest
i
g
a
t
ed as
wel
l
.
The res
u
l
t
sho
w
s t
h
at
for si
m
i
l
a
r dopi
ng r
a
t
e
, t
h
e vari
ant
s
o
f
JLFET ge
ne
ra
l
l
y
prod
uce s
upe
ri
o
r
subt
hre
s
hold sl
ope tha
n
the SOI F
ET
with the slope value
approac
h
ing
near ideal val
u
e of 60 m
V
/decade.
Th
is trend
is ev
id
en
t in bo
th
t
ox
and
L
red
u
c
t
i
ons t
h
at
se
rve
as a
n
a
d
vant
a
g
e.
O
n
t
h
e
ot
h
e
r
han
d
,
t
h
e
t
h
r
e
sh
ol
d
val
u
e s
h
o
w
s
di
ffe
rent
t
e
n
d
enc
i
es bet
w
een t
h
ose t
y
pes o
f
d
e
vi
ce. The
vari
at
i
on o
f
V
T
in
all th
ree v
a
rian
ts of
JLFET ca
n be
m
a
i
n
t
a
i
n
ed sm
al
l
by
sim
u
l
t
a
n
e
ou
s com
b
i
n
at
i
on
of L scal
i
n
g
and
oxi
de t
h
i
n
ni
n
g
, t
h
us re
d
u
c
i
ng
th
e sho
r
t ch
ann
e
l effect (SC
E
) in
term
s o
f
v
o
ltag
e
ro
ll-
off.
Howev
e
r, un
lik
e th
e t
h
e s
cenari
o
in J
L
FET, the
SO
I su
ff
er
s fr
om
v
o
ltag
e
ro
ll-o
f
f
w
h
en
th
e scali
ng
of
cha
n
n
e
l
i
s
com
b
i
n
ed
wi
t
h
oxi
de t
h
i
n
ni
n
g
.
Th
e
b
e
n
e
fit
o
f
bu
lk
t
r
an
spo
r
t
m
ech
an
ism
o
f
fered
b
y
JLFET is ev
id
ent in
th
e b
e
tter sub
t
hresh
o
l
d
slope
. The investigation of the cha
r
acterist
i
c of junctionl
ess tran
sistor on
th
e v
a
riatio
n o
f
g
a
te m
a
teri
al and
60
65
70
75
80
85
90
23
45
6
7
8
S
(mV/decade
t
ox
(nm)
SOI
‐
based
JLT
‐
based
JLT
‐
in
situ
gate
JLT
‐
metal
gate
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 2, A
p
ri
l
20
16
:
89
5 – 9
0
0
90
0
work
fun
c
tion also
sh
ows t
h
at sh
ifting
of th
resho
l
d v
o
l
t
a
ge an
d su
bt
h
r
esh
o
l
d
sl
ope are evi
d
ent. The
p
o
l
ysilico
n
g
a
t
e
JLFET app
e
ars to prov
i
d
e
better stru
ct
u
r
e th
an m
e
tal g
a
te
JLFET fo
r op
t
i
m
a
l o
u
t
p
u
t
in
v
e
ry
sho
r
t
cha
n
nel
wi
t
h
bet
t
e
r
pe
r
f
o
r
m
a
nce i
n
m
a
nagi
ng t
h
e s
h
ort
c
h
an
nel
ef
f
ect
(SC
E
).
Thi
s
res
u
l
t
of
fers
bet
t
e
r
un
de
rst
a
n
d
i
n
g
on
p
r
oces
si
n
g
seq
u
ence
o
f
t
h
e de
vi
ces w
h
i
c
h are
ve
ry
p
r
om
i
s
i
ng fo
r t
h
e fut
u
re
ge
ner
a
t
i
on
devi
ces
.
ACKNOWLE
DGE
M
ENTS
The aut
h
ors express t
h
eir gratitude to LPPM
Dipone
g
o
ro
Un
iv
ersity, fo
r
fu
nd
ing
th
e research
u
n
d
e
r
th
e RPI-PNBP
2
015
sch
e
m
e
.
REFERE
NC
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odeling, fa
brica
tion and c
h
aracter
izatio
n
of d
oub
le g
a
te MOSFETs fo
r
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i
g
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anal
o
g
/
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ong
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g
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u
n
d
a
p
ane
n
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n
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o
t
t
a
nt
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ray
i
l
,
"B
ul
k pl
ana
r
j
u
nct
i
onl
ess t
r
a
n
si
st
or (B
P
J
LT
):
An
attractiv
e d
e
v
i
ce altern
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for scaling
,
"
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.
[4
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J. P. C
o
lin
g
e
,
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ilicon
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su
l
a
to
r (
S
OI)
Tech
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and
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Y
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y
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[5]
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b, a
n
d J.-M
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, "Ana
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m
odel for
ultr
a-thi
n
body
junctionless
sy
mm
e
t
ric d
oub
le g
a
te M
O
SFETs in sub
t
hresho
ld reg
i
m
e
,"
So
lid
-S
ta
te Electro
n
i
cs
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l
.
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]
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m
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eh
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mé, J.-M. Sallese,
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i
n
sk
i
,
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M. Ion
e
scu
,
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n
m
o
b
i
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r
act
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o
n i
n
t
r
i
a
ng
ul
ar
gat
e
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l
l
-
aro
u
n
d
Si
na
no
wi
re
j
u
nct
i
o
nl
ess
nM
O
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t
h
cr
oss
-
s
ect
i
on
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o
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n
t
o
50
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,"
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a
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.
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k
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a
m
,
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o
n
d
al
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d B
.
Gh
os
h
,
"Pe
r
f
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rm
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i
m
a
t
i
on o
f
sub
-
30
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n
c
t
i
onl
ess t
u
n
n
e
l
FET (JLTF
ET),"
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ur
nal
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o
m
p
ut
at
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.
A. R
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a
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t
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,
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hres
h
o
l
d
pe
rf
o
r
m
a
nce com
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ari
s
on
o
f
Junctionless
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,
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Pro
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n
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o
f
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e
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n
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.
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lid-S
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Evaluation Warning : The document was created with Spire.PDF for Python.