Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
10,
No.
4,
August
2020,
pp.
3988
3998
ISSN:
2088-8708,
DOI:
10.11591/ijece.v10i4.pp3988-3998
r
3988
Dual
output
DC-DC
quasi
impedance
sour
ce
con
v
erter
Muhammad
Ado
1
,
A
wang
J
usoh
2
,
T
ole
Sutikno
3
,
Mohd
Hanipah
Muda
4
,
Zeeshan
Ahmad
Arfeen
5
1,2,5
School
of
Electrical
Engineering,
Uni
v
ersiti
T
eknologi
Malaysia,
Malaysia
1
Department
of
Ph
ysics,
Bayero
Uni
v
erity
,
Nigeria
3
Department
of
Electrical
Engineering,
Uni
v
ersitas
Ahmad
Dahlan,
Indonesia
4
F
aculty
of
Electrical
and
Automation
Engineering
T
echnology
,
T
ati
Uni
v
ersiti
Colle
ge,
Malaysia
5
Uni
v
ersity
Colle
ge
of
Engineering
&
T
echnology
,
The
Islamia
Uni
v
ersity
of
Baha
w
alpur
,
P
akistan
Article
Inf
o
Article
history:
Recei
v
ed
Jan
30,
2020
Re
vised
Mar
5,
2020
Accepted
Mar
15,
2020
K
eyw
ords:
Bidirectional
Buck-boost
con
v
erters
Con
v
erters
Double
output
Quasi-Z-source
Z-source
ABSTRA
CT
A
double
output
port
DC-DC
quasi
impedance
source
con
v
erter
(q-ZSC)
is
proposed.
Each
of
the
outputs
has
a
dif
ferent
v
oltage
g
ain.
One
of
the
outputs
is
capable
of
bidirectional
(four
-quadrant)
operation
by
only
v
aryi
ng
the
duty
ratio.
The
second
output
has
the
g
ain
of
traditional
tw
o-switch
b
uck-boost
con
v
erter
.
Operation
of
the
con
v
erter
w
as
v
erified
by
simulating
its
responses
for
dif
ferent
input
v
oltages
and
duty
ratios
using
MA
TLAB
SIMULINK
softw
are.
Its
a
v
erage
steady-state
output
current
and
v
oltage
v
alue
s
were
determined
and
used
to
determine
the
ripples
that
e
xisted.
These
ripples
are
less
than
5%
of
the
a
v
erage
steady-state
v
alues
for
all
the
input
v
oltage
and
duty
ratio
ranges
considered.
Copyright
©
2020
Insitute
of
Advanced
Engineeering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
A
w
ang
Jusoh,
School
of
Electrical
Engineering,
Uni
v
ersiti
T
eknologi
Malaysia,
81310
Skudai,
Johor
,
Malaysia.
Email:
a
w
ang@utm.my
1.
INTR
ODUCTION
Use
of
rene
w
able-ener
gy
(RE)
generation
systems
has
been
dramatically
increasing
due
to
en
viron-
mental
ef
fects
and
the
e
xhaustion
of
fossil
fuels
[1].
The
major
RE
sources
are
photo
v
oltaic
(PV)
ener
gy
,
wind
po
wer
,
and
fuel
cells
(FC).
The
outputs
of
these
RE
sources
are
unre
gulated,
thus
require
po
wer
con
v
erters
such
as
DC-DC
con
v
erters
for
re
gulation
[2–8].
Functions
of
these
DC-DC
con
v
erters
include
re
gulating
the
v
ariable
output
v
oltages
to
a
gi
v
en
set
point
to
char
ge
the
ener
gy
storage
systems
(ESSs)
[4],
char
ging
and
dischar
ging
of
batteries
or
other
ener
gy
storage
systems
(ESSs)
[9],
stepping
up/
do
wn
of
v
oltages
in
fuel
cell
electric
v
ehicles
(FCEVs)
[5]
and
po
wering
DC
loads
or
in
v
erters.
Impedance
source
con
v
erters
(ISCs
or
ZSCs
)
[10]
are
types
of
po
wer
con
v
erters
capable
of
A
C-A
C,
A
C-DC,
DC-A
C
and
DC-DC
con
v
ersion.
The
y
couple
con
v
erter’
s
main
circuit
by
using
an
impedance
netw
ork
to
it
s
input
po
wer
source
and
pro
vide
other
e
xclusi
v
e
features
[11,
12].
ISCs
permit
shoot-through
(ST)
in
v
oltage-fed
ISCs
without
causing
o
v
er
-current
for
v
oltage
boosting
by
allo
wing
short-circuiting
of
their
output
terminal
[13].
The
y
permit
open-circuit
(OC)
in
current-fed
ISCs
by
allo
wing
interruption
of
current
for
current
boosting
without
causing
o
v
er
-v
oltage
[14].
T
urning
ON
switches
of
a
H-bridge’
s
common
le
g
simultaneously
results
in
ST
while
turning
them
ON
triggers
OC
[6].
Inductors
are
used
during
ST
to
store
ener
gy
that
is
released
later
during
other
modes
[15].
ISCs
are
rob
ust
because
the
y
could
be
controlled
by
PWM
signals
with
or
wit
hout
OC
and/or
ST
modes.
Q-ZSCs
[16]
are
class
of
ISCs
obtained
by
sw
apping
switches
and
inductors
to
remedy
some
limitations
of
ZSCs.
Ho
we
v
er
,
J
ournal
homepage:
http://ijece
.iaescor
e
.com
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
3989
limitations
lik
e
discontinuous
input
current
and
high
v
oltage
st
ress
on
switches
are
still
common
in
some
q-ZSC
topologies.
Incorporating
OC
modes
into
the
switching
signals
could
reduce
switching
stress
[3].
Q-ZSC
application
w
as
e
xtended
to
DC-DC
application
by
taking
the
output
across
one
of
the
ca
paci-
tors
[17].
Ho
we
v
er
,
[18–20]
took
their
outputs
across
a
switch
in
what
is
called
pulse-width
modulated
DC-DC
ISCs.
M.
Ado
et
al
[11]
and
[21]
later
proposed
additional
topology
each
to
form
an
additional
class
[22].
M.
Ado
et
al
[23]
e
xtended
the
f
ami
ly
of
DC-DC
q-ZSCs
from
tw
o
classes
to
three
and
from
four
members
to
six.
Each
of
the
classes
has
tw
o
members
and
a
unique
v
oltage
g
ain.
Although
some
of
the
proposed
topologies
are
capable
of
four
-quadrant
(bidirectional)
ener
gy
transfer
,
the
y
all
ha
v
e
single
input
and
single
output
(SISO)
v
oltages.
This
paper
presents
a
DC-DC
q-ZSC
topology
with
a
single
input
v
oltage
source
and
dual
output
v
oltage
ports
as
sho
wn
in
Figure
1.
The
tw
o
outputs
ha
v
e
dif
ferent
v
oltage
g
ains.
The
significance
of
ha
ving
dif
ferent
v
oltage
g
ains
is
that
tw
o
dif
ferent
output
v
olt
ages
could
be
obtained
simultaneously
.
The
operation
of
the
proposed
con
v
er
ter
w
as
v
erified
by
simulating
its
response
in
MA
TLAB
SIMULINK.
The
v
erification
in
v
olv
ed
simulating
its
response
at
dif
ferent
input
v
oltages
(V
g
)
and
duty
ratios
(D).
The
a
v
erage
steady-state
output
current
(I
O
)
and
v
oltages
(V
O
)
of
each
simulation
w
as
determined
and
analyzed.
Ripple
ratios
for
these
a
v
erage
v
oltages
and
currents
were
determined
and
compar
ed
with
theoretical
v
alues.
The
comparison
sho
wed
that
the
a
v
erage
v
oltages
were
abo
v
e
89%
of
the
theoretical
v
alues.
Figure
1.
T
opology
of
proposed
con
v
erter
2.
CIRCUIT
AN
AL
YSIS
F
or
easy
analysis,
the
circuit
is
operated
based
on
tw
o
operating
modes.
The
modes
are
obtained
by
complementary
switching
of
the
con
v
erter’
s
switches
S
1
and
S
2
.
2.1.
Mode
I
During
this
operating
mode,
S
1
is
turned
ON
while
S
2
is
turned
OFF
as
sho
wn
in
Figure
2a.
The
circuit
equations
during
this
mode
are:
V
L
1
=
V
C
2
V
C
1
(1)
V
L
2
=
V
g
(2)
2.2.
Mode
II
During
this
operating
mode,
S
1
is
turned
OFF
while
S
2
is
tur
n
e
d
ON
as
sho
wn
in
Figure
2b.
The
circuit
equations
during
this
mode
are:
V
L
1
=
V
g
V
C
1
(3)
V
L
2
=
V
O
2
(4)
Applying
v
olt-second
balance
on
L
1
yields
D
V
C
2
D
V
C
1
+
V
g
V
C
1
D
V
g
+
D
V
C
1
=
0
(5)
Dual
output
DC-DC
quasi
impedance
...
(Muhammad
Ado)
Evaluation Warning : The document was created with Spire.PDF for Python.
3990
r
ISSN:
2088-8708
Applying
v
olt-second
balance
on
L
2
yields
D
V
g
+
V
C
2
(1
D
)
=
0
(6)
Simplifying
(6)
sho
ws
that
V
C
2
=
D
1
D
V
g
(7)
Substituting
(7)
into
(5)
and
simplifying
yields
V
C
1
=
1
2
D
1
D
(8)
From
Figure
1,
V
O1
is
in
parallel
with
C
1
,
thus
V
C
1
=
V
O
1
(9)
Also
from
Figure
1,
V
O2
is
in
parallel
with
C
2
,
thus
V
C
2
=
V
O
2
(10)
(a)
(b)
Figure
2.
Equi
v
alent
circuit
of
the
proposed
con
v
erter
during
(a)
mode
I,
(b)
Mode
II
2.3.
First
output
(V
O1
)
The
e
xpression
for
V
O1
is
obtained
by
substituting
(9)
into
(8)
as
V
O
1
=
1
2
D
1
D
V
g
(11)
The
g
ain
of
this
output
is
A
1
=
V
O
1
V
g
=
1
2
D
1
D
(12)
2.4.
Second
output
(V
O2
)
The
e
xpression
for
V
O2
is
obtained
by
substituting
(10)
into
(7)
as
V
O
2
=
D
1
D
V
g
(13)
The
g
ain
of
this
output
is
A
2
=
V
O
2
V
g
=
D
1
D
(14)
Int
J
Elec
&
Comp
Eng,
V
ol.
10,
No.
4,
August
2020
:
3988
–
3998
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
3991
A
plot
comparing
the
tw
o
dif
ferent
outputs
of
the
con
v
erter
V
O1
and
V
O2
ag
ainst
duty
ratio
(D)
is
sho
wn
in
Figure
3.
The
follo
wing
can
be
deduced
from
Figure
3:
(a)
Both
the
tw
o
outputs
are
capable
of
stepping
up
(boosting)
or
stepping
do
wn
(b
ucking)
the
input
v
oltage
as
D
is
v
aried
from
0
to
1.
Ho
we
v
er
,
the
b
uck
operation
in
V
O2
is
in
v
erted.
(b)
As
D
is
v
aried
from
0
to
0.5,
the
tw
o
outputs
are
less
than
or
equal
to
the
input
v
oltage
magnitude
(c)
F
or
V
O2
,
v
arying
the
output
from
0.5
to
1
results
in
boost
operation
(d)
F
or
V
O1
,
v
arying
D
from
0.5
to
0.667
results
in
in
v
erted
b
uck
(stepping
do
wn)
operation
before
achie
ving
in
v
erted
boost
operation
from
0.667
to
1
(e)
T
w
o
dif
ferent
b
uck
operations
could
be
achie
v
ed
from
V
O1
namely:
positi
v
e
b
uck
(from
D
=
0
to
0.5)
and
ne
g
ati
v
e
b
uck
(from
D
=
0.667
to
1)
(f)
The
positi
v
e
and
ne
g
ati
v
e
b
uck
operati
on
implies
bidirectional
b
uck
capability
[23,
17].
The
bidirectional
b
uck
capability
means
that
during
the
ne
g
ati
v
e
b
uck,
ener
gy
is
transferred
from
source
to
V
O1
while
during
the
positi
v
e
b
uck,
it
could
be
transferred
from
V
O1
to
source
[17]
at
lo
wer
v
oltage
magnitude.
Figure
3.
Comparison
of
v
oltage
g
ains
of
the
con
v
erter’
s
tw
o
outputs
ag
ainst
duty
ratio
(D)
3.
VERIFICA
TION
Operation
of
the
con
v
erter
w
as
v
erified
by
simulating
a
specifically
designed
prototype
using
MA
T
-
LAB
SIMULINK.
3.1.
Components
selection
The
design
equations
of
DC-DC
q-ZSC
deri
v
ed
in
[24]
and
presented
here
as
(15)
through
(18)
were
used
to
determine
the
components
v
alues
for
a
prototype.
The
specifications
for
the
prototype
are
gi
v
en
in
T
able
1.
C
1
=
D
(1
D
)
I
O
V
(1
2
D
)
f
V
g
(15)
Where
I
O
is
the
output
current,
f
is
the
minimum
operating
frequenc
y
,
V
is
the
v
oltage
ripple
ratio,
V
g
is
the
input
v
oltage.
C
2
=
2(1
D
)
I
O
V
f
V
g
(16)
L
1
=
D
V
g
f
I
I
O
(17)
Where
I
is
the
current
ripple
ratio.
L
2
=
D
(
D
1)
V
g
f
(
D
+
1)
I
I
O
(18)
Dual
output
DC-DC
quasi
impedance
...
(Muhammad
Ado)
Evaluation Warning : The document was created with Spire.PDF for Python.
3992
r
ISSN:
2088-8708
T
able
1.
Design
specifications
P
arameter
Minimum
Maximum
Input
V
oltage
(V
g
)
10
V
15
V
Output
Current
(I
O
)
0.4
A
2
A
Switching
Frequenc
y
(f)
100
kHz
Max
Duty
Ratio
(D)
0.7
3.2.
Component
v
alues
3.2.1.
Capacitor
1
(C
1
)
C
1
=
D
max
(1
D
max
)
I
O
;max
(1
2
D
max
)
f
min
V
V
g
;min
(19)
I
O,max
is
the
maximum
output
current,
f
min
is
the
minimum
frequenc
y
,
V
is
the
v
oltage
ripple
ratio,
V
g,min
is
the
minimum
input
v
oltage.
C
1
=
0
:
72
(1
0
:
72)
2
1
(2
0
:
72)
100
10
3
0
:
2
10
F
=
4
:
52
F
(20)
3.2.2.
Capacitor
2
(C
2
)
C
2
=
2(1
D
max
)
I
O
;max
f
min
V
V
g
;min
(21)
C
2
=
2
(1
0
:
72)
2
100
10
3
0
:
2
10
F
=
5
:
6
F
(22)
L
1
=
D
max
V
g
;max
f
min
I
I
O
;min
(23)
Where
V
g,max
is
the
maximum
input
v
oltage,
I
is
the
c
urrent
ripple
ratio
and
I
O,min
is
the
minim
u
m
output
current.
L
1
=
0
:
72
15
100
10
3
0
:
2
0
:
4
H
=
1
:
35
mH
(24)
L
2
=
D
max
(1
D
max
)
V
g
;max
(
D
max
+
1)
f
min
I
I
O
;min
(25)
L
2
=
0
:
72
(1
0
:
72)
15
(0
:
72
+
1)
100
10
3
0
:
2
0
:
4
H
=
87
:
9
H
(26)
The
components
v
alues
found
i
n
(20),
(22),
(24)
and
(26)
implies
the
use
of
asymmetric
components
[25,
6,
3]
3.3.
Simulations
and
methods
The
components
v
alues
obtained
in
(20),
(22),
(24)
and
(26)
as
sho
wn
in
T
able
2
were
used
to
simulate
the
response
of
the
proposed
con
v
erter
.
This
simulation
w
as
in
order
to
v
erify
the
ideal
operation
of
the
con
v
erter
.
Thus,
ideal
components
were
used
and
parasitic
resistances
were
ne
glected.
A
load
with
resistance
of
20
w
as
connected
to
the
first
output
(output
1)
to
consume
a
v
oltage
V
O1
.
Also,
another
load
with
resistance
of
20
w
as
connected
to
the
second
output
(output
2)
to
consume
a
v
oltage
V
O2
as
sho
wn
in
Figure
1.
T
o
analyze
the
response
of
the
con
v
erter
at
v
arious
input
v
oltages
(V
g
)
and
duty
ratios
(D),
paramet
ric
sweep
of
V
g
and
D
for
10
V
V
g
15
V
with
step
size
of
1
V
and
0
D
0
:
7
with
step
size
of
0.1
respecti
v
ely
.
This
implies
that
the
con
v
erter’
s
response
w
as
simulated
for
all
possible
operating
v
oltages
and
duty
ratios
based
on
the
design
specifications
and
step
size.
Some
selected
steady-state
responses
of
the
con
v
erter
at
minimum
and
maximum
input
v
oltages
and
duty
rati
os
are
s
ho
wn
in
Figure
4a
through
Figure
5b.
Since
steady-state
v
alues
o
f
DC-DC
con
v
er
ters
contain
Int
J
Elec
&
Comp
Eng,
V
ol.
10,
No.
4,
August
2020
:
3988
–
3998
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
3993
ripples
that
are
dependent
of
switching
frequenc
y
and
v
alues
of
the
reacti
v
e
components
due
to
char
ging
and
dischar
ging,
a
v
erage
v
alues
of
the
con
v
erter’
s
steady-state
output
v
oltages
and
currents
V
O1
,
V
O2
,
I
O1
and
I
O2
for
e
v
ery
gi
v
en
V
g
and
D
were
determined.
Plots
of
these
a
v
erage
output
v
oltages
and
currents
ag
ainst
D
are
sho
wn
in
Figure
6a
and
6b
respecti
v
ely
.
The
ripples
in
the
output
v
oltages
and
curr
ents
determined
using
Equation
(27)
where
A
is
the
v
oltage
or
current,
A
(%)
is
the
ripple
ratio
in
percentage,
A
max
is
the
steady-state
maximum
v
alue
of
the
signal,
A
min
is
its
minimum
and
A
a
v
is
its
a
v
erage
v
alue.
A
(%)
=
A
max
A
min
2
A
av
100
(27)
The
v
alues
of
output
v
oltages
and
currents
along
with
their
ripple
v
alues
V
O1
(%)
,
V
O2
(%)
,
I
O1
(%)
and
I
O2
(%)
for
10
V
V
g
15
V
and
0
:
3
D
0
:
7
are
presented
in
T
able
3
through
T
abl
e
8.
0
:
3
D
0
:
7
w
as
considered
because
the
ef
ficienc
y
of
complementary
switched
con
v
erters
reduces
when
operated
outside
this
range
[22,
12,
19].
A
significance
of
the
the
ripple
ratio
is
to
measure
the
appositeness
of
the
adapted
design
equations.
This
is
becaus
e
v
ery
lo
w
ripple
indicates
o
v
erv
alue
while
v
ery
high
ripple
indicates
underv
alue
of
reacti
v
e
component.
T
able
2.
Summary
of
components
v
alues
Component
V
alue
Unit
C
1
4.52
F
C
2
5.6
F
L
1
1350
H
L
2
87.9
H
R
O
1
20
R
O
2
20
4.
RESUL
TS
AND
DISCUSSION
Results
of
the
proposed
con
v
erter’
s
response
for
some
s
elected
steady-state
responses
of
the
con
v
erter
at
minimum
and
maximum
input
v
oltages
and
duty
ratios
are
sho
wn
in
Figure
4a
through
Figure
5b.
Figure
4a
and
Figure
4b
both
sho
w
its
response
at
V
g
=
10
b
ut
D
=
0.4
and
0.6
respecti
v
ely
while
Figure
5a
and
Figure
5b
both
sho
w
its
response
at
V
g
=
15
b
ut
D
=
0.4
and
0.6
respecti
v
ely
.
T
able
3,
4,
5,
6,
7
and
T
able
8
sho
w
the
a
v
erage
output
v
oltages
and
currents
along
with
their
percentage
ripples.
(a)
(b)
Figure
4.
Steady
state
simulation
response
of
the
proposed
con
v
erter
sho
wing
output
and
capacitor
v
oltages,
output
and
inductor
currents
for
(a)
V
g
=
10
V
and
D
=
0
:
4
(b)
V
g
=
10
V
and
D
=
0
:
6
Dual
output
DC-DC
quasi
impedance
...
(Muhammad
Ado)
Evaluation Warning : The document was created with Spire.PDF for Python.
3994
r
ISSN:
2088-8708
(a)
(b)
Figure
5.
Steady
state
simulation
response
of
the
proposed
con
v
erter
sho
wing
output
and
capacitor
v
oltages,
output
and
inductor
currents
for
(a)
V
g
=
15
V
and
D
=
0
:
4
(b)
V
g
=
15
V
and
D
=
0
:
6
(a)
(b)
Figure
6.
Plots
of
the
proposed
con
v
erter’
s
steady
state
a
v
erage
(a)
Output
v
oltages
ag
ainst
duty
ratio
for
dif
ferent
input
v
oltages
(b)
Output
currents
ag
ainst
duty
ratio
for
dif
ferent
input
v
oltages
T
able
3.
A
v
erage
output
v
oltages
and
currents
of
the
proposed
con
v
erter
with
their
percentage
ripples
at
V
g
=
10
V
with
D
v
aried
from
0.3
to
0.7
V
g
=
10
V
D
V
01
(V)
V
02
(V)
I
01
(A)
I
02
(A)
V
1
(%)
V
2
(%)
I
1
(%)
I
2
(%)
0.3
5.714
-4.2822
0.2857
-0.2141
0.0465
-0.8322
0.0465
-0.8322
0.4
3.3671
-6.6146
0.1684
-0.3307
0.0444
-0.9026
0.0444
-0.9026
0.5
0.1266
-9.7351
0.0063
-0.4868
3.9975
-2.2408
3.9975
-2.2408
0.6
-4.5964
-14.266
-0.2298
-0.7133
-0.0994
-3.6016
-0.0994
-3.6016
0.7
-11.942
-21.393
-0.5971
-1.0697
-0.0420
-4.9488
-0.0420
-4.9488
T
able
4.
A
v
erage
output
v
oltages
and
currents
of
the
proposed
con
v
erter
with
their
percentage
ripples
at
V
g
=
11
V
with
D
v
aried
from
0.3
to
0.7
V
g
=
11
V
D
V
01
(V)
V
02
(V)
I
01
(A)
I
02
(A)
V
1
(%)
V
2
(%)
I
1
(%)
I
2
(%)
0.3
6.2853
-4.7104
0.31426
-0.2355
0.0465
-0.8322
0.0465
-0.8322
0.4
3.7038
-7.2761
0.1852
-0.3638
0.0444
-0.9026
0.0443
-0.9026
0.5
0.1392
-10.71
0.0070
-0.5355
3.9987
-2.2405
3.9987
-2.2405
0.6
-5.0561
-15.693
-0.2528
-0.7846
-0.0994
-3.6016
-0.0994
-3.6016
0.7
-13.136
-23.532
-0.6568
-1.1766
-0.0420
-4.9488
-0.0420
-4.9488
Int
J
Elec
&
Comp
Eng,
V
ol.
10,
No.
4,
August
2020
:
3988
–
3998
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
3995
T
able
5.
A
v
erage
output
v
oltages
and
currents
of
the
proposed
con
v
erter
with
their
percentage
ripples
at
V
g
=
12
V
with
D
v
aried
from
0.3
to
0.7
V
g
=
12
V
D
V
01
(V)
V
02
(V)
I
01
(A)
I
02
(A)
V
1
(%)
V
2
(%)
I
1
(%)
I
2
(%)
0.3
6.8567
-5.1389
0.3428
-0.2569
0.0465
-0.8322
0.0465
-0.8322
0.4
4.0405
-7.9376
0.2020
-0.3969
0.0444
-0.9026
0.0443
-0.9026
0.5
0.1518
-11.684
0.0076
-0.5842
3.9987
-2.2405
3.9987
-2.2405
0.6
-5.5157
-17.119
-0.2758
-0.8560
-0.0994
-3.6016
-0.0994
-3.6016
0.7
-14.33
-25.672
-0.7165
-1.2836
-0.0420
-4.9488
-0.0420
-4.9488
T
able
6.
A
v
erage
output
v
oltages
and
currents
of
the
proposed
con
v
erter
with
their
percentage
ripples
at
V
g
=
13
V
with
D
v
aried
from
0.3
to
0.7
V
g
=
13
V
D
V
01
(V)
V
02
(V)
I
01
(A)
I
02
(A)
V
1
(%)
V
2
(%)
I
1
(%)
I
2
(%)
0.3
7.4282
-5.5669
0.3714
-0.2783
0.0464
-0.8323
0.0464
-0.8323
0.4
4.3772
-8.599
0.2187
-0.4300
0.0444
-0.9026
0.0444
-0.9026
0.5
0.1645
-12.658
0.0082
-0.6329
3.9987
-2.2405
3.9987
-2.2405
0.6
-5.9754
-18.546
-0.2998
-0.9273
-0.0994
-3.6016
-0.0994
-3.6016
0.7
-15.525
-27.811
-0.7762
-1.3906
-0.0420
-4.9488
-0.0420
-4.9488
T
able
7.
A
v
erage
output
v
oltages
and
currents
of
the
proposed
con
v
erter
with
their
percentage
ripples
at
V
g
=
14
V
with
D
v
aried
from
0.3
to
0.7
V
g
=
14
V
D
V
01
(V)
V
02
(V)
I
01
(A)
I
02
(A)
V
1
(%)
V
2
(%)
I
1
(%)
I
2
(%)
0.3
7.9997
-5.9951
0.4000
-0.2998
0.0464
-0.8322
0.0464
-0.83217
0.4
4.7139
-9.2605
0.2357
-0.4630
0.0443
-0.9026
0.0443
-0.9026
0.5
0.1772
-13.629
0.0089
-0.6815
3.9975
-2.2408
3.9975
-2.2408
0.6
-6.435
-19.973
-0.3218
-0.9986
-0.0994
-3.6016
-0.0994
-3.6016
0.7
-16.719
-29.95
-0.8360
-1.4975
-0.0420
-4.9488
-0.0420
-4.9488
T
able
8.
A
v
erage
output
v
oltages
and
currents
and
their
percentage
ripples
of
the
proposed
con
v
erter
at
V
g
=
15
V
with
D
v
aried
from
0.3
to
0.7
V
g
=
15
V
D
V
01
(V)
V
02
(V)
I
01
(A)
I
02
(A)
V
1
(%)
V
2
(%)
I
1
(%)
I
2
(%)
0.3
8.5711
-6.4233
0.4286
-0.3212
0.0465
-0.8323
0.0465
-0.8323
0.4
5.0506
-9.922
0.2525
-0.4961
0.0444
-0.9026
0.0444
-0.9026
0.5
0.19
-14.603
0.0095
-0.7301
3.9975
-2.2408
3.9975
-2.2408
0.6
-6.8947
-21.399
-0.3447
-1.07
-0.0994
-3.6016
-0.0994
-3.6016
0.7
-17.913
-32.09
-0.8957
-1.6045
-0.0420
-4.9488
-0.0420
-4.9488
Plots
of
these
a
v
erage
output
v
oltages
and
currents
ag
ainst
D
are
sho
wn
in
Figure
6a
and
6b
re
spec-
ti
v
ely
.
Results
of
Figure
4a
through
Figure
5b
confirmed
the
operation
of
the
proposed
con
v
erter
.
As
presented
in
[17],
the
output
v
oltage
and
current
of
port
1
(V
O1
and
I
O1
are
bipolar;
positi
v
e
for
D
<
0.5
and
in
v
erted
for
D
>
0.5).
This
is
captured
in
(9),
with
the
V
O1
e
xpected
to
be
null
at
D
=
0
:
5
.
Ho
we
v
er
as
sho
wn
in
T
able
3
through
T
able
8,
V
O1
at
D
=
0
:
5
is
slightly
greater
than
0
(zero)
with
it
s
magnitude
proportional
to
the
V
g
as
sho
wn
in
Figure
7.
All
these
v
alues
are
1.27
%
of
the
corresponding
V
g
.
The
ripples
for
output
port
1
(V
1
(%)
and
I
1
(%)
)
presented
in
T
able
3
through
T
able
8
are
minimal
e
xcept
at
D
=
0.5,
where
it
is
maximum
at
4
%
due
to
the
ideal
0
(zero)
output.
The
ripples
for
output
port
2
are
significantly
higher
than
the
corresponding
ones
for
output
1.
Reasons
for
the
wide
v
ariation
in
the
ripple
ratio
are:
(a)
The
design
equations
used
to
determine
the
components
v
alues
are
not
specifically
deri
v
ed
for
the
proposed
con
v
erter
b
ut
for
a
related
topology
with
a
single
output
in
which
the
output
w
as
tak
en
from
port
2.
(b)
The
components
used
for
C
1
and
L
1
are
o
v
ersized
because
the
design
equations
were
not
specifically
deri
v
ed
for
this
con
v
erter
.
Dual
output
DC-DC
quasi
impedance
...
(Muhammad
Ado)
Evaluation Warning : The document was created with Spire.PDF for Python.
3996
r
ISSN:
2088-8708
The
plots
of
a
v
erage
output
v
oltages
and
currents
of
the
proposed
con
v
erter’
s
simulation
responses
ag
ainst
duty
ratio
for
dif
ferent
input
v
oltages
sho
wn
i
n
Figure
6a
and
Figure
6b
respecti
v
ely
sho
w
that
the
shape
of
the
plot
is
identical
with
the
theoretical
g
ain
curv
e
of
the
con
v
erter
sho
wn
in
Figure
3.
The
a
v
erage
output
v
oltages
of
output
port
1
are
about
89.56%
to
101%
of
the
theoretical
v
alue
for
0
:
3
D
0
:
7
e
xcept
at
V
g
=
15
V
where
it
is
96%
to
108.2%.
F
or
port
2,
V
O2
is
91.7%
to
99.9%
of
the
theoretical
v
alue
with
the
ratio
proportional
to
D.
It
is
important
to
note
that
in
some
cases
the
simulation
output
for
some
parameters
are
abo
v
e
or
v
ery
close
to
the
theoretical
i
deal
v
alues
as
seen
abo
v
e.
This
is
due
to
the
ef
fect
of
dead-time/OC
that
e
xists
in
the
switching
signal
[6].
Figure
7.
Plot
of
V
O1
at
D
=
0
:
5
ag
ainst
V
g
5.
CONCLUSION
A
q-ZSC
with
tw
o
output
s
has
been
proposed.
The
g
ain
of
each
output
has
been
deri
v
ed.
The
oper
-
ations
of
the
con
v
erter
w
as
simulated
at
dif
ferent
input
v
oltages
and
duty
ratios
using
MA
TLAB
SIMULINK.
The
a
v
erage
steady-state
output
current
and
v
oltages
of
each
simulation
w
as
determined,
analyzed
and
their
ripple
ratios
determined.
Comparison
of
the
a
v
erage
output
v
oltages
of
the
tw
o
outputs
sho
w
agreement
with
the
theoretical
outputs
gi
v
en
by
their
ideal
g
ain
equations.
The
ripples
present
in
all
the
outputs
of
the
proposed
con
v
erter
were
lo
wer
than
5%.
REFERENCES
[1]
J.-H.
P
ark,
H.-G.
Kim,
E.-C.
Nho,
T
.-W
.
Chun,
and
J.
Choi,
“Grid-connected
PV
system
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–
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Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
3997
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2
O
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w
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the
ef
ficienc
y
and
electrical
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wer
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of
a
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PV
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”
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PES
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BIOGRAPHIES
OF
A
UTHORS
Muhammad
Ado
is
a
researcher
at
Uni
v
ersiti
T
eknologi
Malaysia
(UTM)
where
he
completed
his
Ph.D.
He
has
been
a
lecturer
with
Bayero
Uni
v
ersity
,
Kano,
Nigeria,
where
he
obtained
his
Bachelor
and
Master
de
grees
in
Electronics
in
2009
and
2016
respecti
v
ely
.
His
research
interest
s
include
po
wer
con
v
erters,
modelling
and
control,
artificial
intell
igence
and
semiconductor
ph
ysics.
He
is
af
filiated
with
IEEE
as
student
member
and
Nigerian
Institute
of
Ph
ysics
(NIP)
as
a
member
.
In
IEEE
Access,
IET
Po
we
r
Electronics,
International
journal
of
electronics
and
other
scientific
publications,
he
serv
es
as
in
vited
re
vie
wer
.
Dual
output
DC-DC
quasi
impedance
...
(Muhammad
Ado)
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