Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
9,
No.
6,
December
2019,
pp.
5046
5059
ISSN:
2088-8708,
DOI:
10.11591/ijece.v9i6.pp5046-5059
r
5046
Pr
oposal
and
design
methodology
of
switching
mode
lo
w
dr
opout
r
egulator
f
or
bio-medical
applications
K
enya
K
ondo
1
,
Hir
oki
T
amura
2
,
K
oichi
T
anno
3
1
Interdisciplinary
Graduate
School
of
Agriculture
and
Engineering,
Uni
v
ersity
of
Miyazaki,
Japan
2
Department
of
En
vironmental
Robotics,
Uni
v
ersity
of
Miyazaki,
Japan
3
Department
of
Electrical
and
System
Engineering,
Uni
v
ersity
of
Miyazaki,
Japan
Article
Inf
o
Article
history:
Recei
v
ed
Dec
22,
2018
Re
vised
Apr
25,
2019
Accepted
Jun
25,
2019
K
eyw
ords:
V
oltage
re
gulator
Lo
w
dropout
On-of
f
control
Bio-medical
Analog
front
end
ABSTRA
CT
The
switching
operation
based
lo
w
dropout
(LDO)
re
gulator
utilizing
on-of
f
control
is
presented.
It
consists
of
simple
circuit
elements
which
are
comparator
,
some
logic
g
ates,
switched
capacitor
and
feedback
circuit.
In
this
study
,
we
tar
get
the
applica-
tion
to
the
po
wer
supply
circuit
for
the
analog
front
end
(AFE)
of
bio-medi
cal
system
(such
as
daily-used
bio-monitoring
de
vices)
whose
re
quired
maximum
load
current
is
50
A.
In
this
paper
,
the
design
procedure
of
the
proposed
LDO
has
been
clarified
and
actual
circuit
design
using
the
procedure
has
been
done.
The
proposed
LDO
has
been
e
v
aluated
by
SPICE
simulation
using
1P
2M
0.6
m
CMOS
process
de
vice
parame-
ters.
From
simulation
results,
we
could
confirm
that
the
lo
w
quiescent
current
of
1
A
with
the
output
ripple
of
5
mVpp.
The
circuit
area
is
0.0173
mm
2
in
spite
of
using
0.6
m
design
rules.
The
proposed
circuit
is
suitable
for
adopting
to
the
light
load
and
lo
w
frequenc
y
applications.
Copyright
c
2019
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
K
oichi
T
anno,
Department
of
Electrical
and
System
Engineering,
Institute
of
Education
and
Research
for
Engineering,
Uni
v
ersity
of
Miyazaki,
1-1
Gakuenkibanadai-Nishi,
Miyazaki,
889-2192,
Japan.
Email:
tanno@cc.miyazaki-u.ac.jp
1.
INTR
ODUCTION
Recently
e
xpanding
demands
for
bio-medical
de
vices
ha
v
e
dri
v
en
e
xtensi
v
e
research
on
lo
w-po
wer
mix
ed-signal
inte
grated
circuit
technologies
[1-6].
The
b
uilding
blocks
of
the
analog
front-end
(AFE)
in
the
bio-medical
system-on-chip
(SoC)
lik
e
as
instrumentation
amplifier
(IA),
programmable
g
ain
amplifier
(PGA),
lo
w-pass
filter
(LPF)
and
analog-to-digital
con
v
erter
(ADC)
require
the
po
wer
supply
v
oltages
suitable
for
each,
therefore
the
multiple
lo
w
dropout
(LDO)
re
gulators
are
implemented
as
the
post-re
gulators
follo
wing
the
dc-dc
con
v
erters
to
achie
v
e
high-ef
ficienc
y
po
wer
management
solution
[5-6].
Although
the
con
v
entional
analog-LDOs
(ALDOs)
ha
v
e
some
adv
antages
lik
e
as
lo
w-noise,
high
po
wer
supply
rejection
ratio
(PSRR)
and
high
accurac
y
,
the
y
occup
y
the
lar
ge
circuit
area
due
to
po
wer
MOS
transistor
operated
in
saturation
re
gion
[7-9].
This
causes
the
circuit
area
increase
of
the
po
wer
management
unit
(PMU)
in
SoC,
therefore
the
importance
of
de
v
eloping
area-ef
ficient
LDO
is
gro
wing
up.
On
the
other
hand,
the
dynamic
range
and
frequenc
y
range
of
the
bio-potential
signals
are
limited
such
as
V
to
mV
in
the
dynamic
range
and
sub-1
Hz
to
a
fe
w
kHz
in
the
frequenc
y
[10].
In
the
bio-medical
signal
processing,
the
on-chip
or
of
f-chip
high-pass
and
lo
w-pass
filters
which
ha
v
e
the
v
ery
lo
w
cut-of
f
fr
equenc
y
are
often
used
to
eliminate
dc
v
oltage
(ac-coupling)
and
une
xpected
high
frequenc
y
noise
[3]–[6],[10].
On
the
signal
band
design
aspect,
since
AFE
eliminates
out-
of-band
noise
by
o
wn
LPF
,
the
po
wer
supply
noise
specification
at
high
frequenc
y
can
be
alle
viated.
Therefore,
the
swit
ching
po
wer
supply
circuit
li
k
e
as
digit
al-LDOs
(DLDOs)
can
be
applied
to
AFE
of
t
he
bio-medical
J
ournal
homepage:
http://iaescor
e
.com/journals/inde
x.php/IJECE
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
5047
SoC.
Ho
we
v
er
,
DLDO
has
a
complicated
system
architecture
and
its
circuit
design
becomes
dif
ficult.
As
an
ultra-lo
w
area
LDO,
the
switching
mode
LDO
util
izing
the
on-of
f
h
ysteretic
control
ha
v
e
been
proposed
in
[15].
Although
its
maximum
output
current
ability
is
small
as
100
A,
its
circuit
design
is
v
ery
simple
by
utilizing
on-of
f
h
ysteret
ic
control,
and
the
circuit
area
is
v
ery
small
as
0.001
mm
2
.
Thus,
this
is
v
ery
ef
fecti
v
e
method
for
area
minimization.
In
the
bio-medical
application,
since
the
amplifier
and
filter
used
in
AFE
treat
a
small
dynamic
range
and
lo
w
frequenc
y
band,
these
circuits
are
often
designed
by
using
the
subthreshold
re
gion
[4].
Therefore,
lar
ge
output
current
of
LDO
in
this
application
is
not
required.
Ho
we
v
er
,
since
its
output
ripple
v
oltage
is
lar
ge
as
47
mV
and
the
ripple
frequenc
y
(swit
ching
frequenc
y)
is
lo
w
a
s
a
fe
w
kHz,
its
output
ripple
may
interfere
with
the
signal
band
of
the
AFE
of
the
bio-medical
SoC.
Furthermore,
the
LDO
proposed
in
[15]
uses
the
Schmitt
trigger
in
v
erter
to
define
the
magnitude
of
the
output
ripple,
therefore
design
for
reducing
output
ripple
is
esse
ntially
dif
ficult.
Hence,
[15]
states
that
this
topology
is
suitable
only
for
circuits
with
lo
w
sensiti
vity
to
supply
v
oltage
ripples
such
as
digital
circuits.
In
order
to
enable
the
area-ef
ficient
switching
mode
LDO
application
to
bio-medical
AFE,
in
this
pa-
per
,
we
propose
a
method
to
control
the
ripple
v
oltage
and
switching
frequenc
y
with
circuit
delay
.
The
proposed
circuit
consists
of
comparator
,
logic
circuit,
switched
capacitor
and
feedback
circuit.
From
mathematical
anal-
ysis
of
the
switching
operation,
the
design
procedure
of
output
ripple
and
switching
c
ycle
time
of
the
proposed
re
gulator
can
be
clarified.
The
ripple
v
oltage
and
switching
frequenc
y
are
controlled
by
the
response
time
of
the
comparator
which
is
tuned
by
adjusting
the
tail
current
of
the
comparator
.
From
this
feasibility
study
,
we
confirmed
the
proposed
circuit
can
be
adopted
to
AFE
of
bio-medical
sys
tem
when
the
output
ripple
of
the
proposed
circuit
is
designed
to
eliminate
properly
by
LPF
in
the
AFE.
This
paper
consists
of
5
chapters.
Chapter
2
presents
the
basic
topology
and
detail
of
the
design
guideline
deri
v
at
ion
of
the
proposed
topology
.
Chapter
3
presents
the
practical
ci
rcuit
design
e
xample.
The
simulation
results
are
sho
wn
in
Chapter
4,
follo
wed
by
the
conclusion
in
Chapter
5.
2.
CONVENTION
AL
SWITCHING
MODE
LDO
Figure
1
(a)
and
(b)
respecti
v
ely
sho
w
the
circuit
s
chematic
and
the
conceptual
w
a
v
eform
of
con
v
en-
tional
switching
mode
LDO
which
consists
of
Schmitt
trigger
comparator
and
pass
switch
[15].
Schmitt
trigger
comparator
consists
of
Schmitt
trigger
in
v
erter
and
pre-amplifier
.
The
on/of
f
time
of
the
pass
switch
depends
on
the
h
ysteresis
v
oltage
V
hy
s
and
delay
time
T
del
ay
of
Schmitt
trigger
comparator
,
and
the
output
v
oltage
ripple
v
out
also
depends
on
them.
In
general,
the
h
ysteresis
v
oltage
of
Schmitt
trigger
in
v
erter
is
lar
ge
v
ariation
because
of
it
has
high
sensiti
vity
with
the
process
v
ariation
and
m
ismatch
of
the
transistor
,
and
it
is
dif
ficult
to
design
it
smaller
than
a
fe
w
tens
of
mV
.
Therefore,
design
for
reducing
output
ripple
of
the
con
v
entional
switching
mode
LDO
is
essentially
dif
ficult.
(
a
)
S
c
hm
i
t
t
t
r
i
g
g
e
r
C
om
pa
r
a
t
or
P
M
O
S
P
A
S
S
S
W
P
A
S
S
S
W
O
N
P
A
S
S
S
W
O
F
F
(
b
)
Figure
1.
Con
v
entional
switching
mode
LDO.
(a)
Circuit
schematic.
(b)
Conceptual
w
a
v
eform.
3.
CONCEPT
OF
PR
OPOSED
CIRCUIT
AND
DERIV
A
TION
OF
DESIGN
GUIDELINES
Figure
2
(a)
sho
ws
the
conceptual
circuit
model
of
the
proposed
circuit.
The
proposed
circuit
consist
s
of
switched
capacitor
circuit,
logic
circuit,
comparator
and
feedback
circuit.
The
switched
capacitor
circuit
as
the
output
stage
consists
of
the
PMOS
switch
with
on
resistance
R
out
and
decoupling
capacitor
C
L
.
V
D
D
is
the
Pr
oposal
and
design
methodolo
gy
of
switc
hing
mode
low
dr
opout...
(K
enya
K
ondo)
Evaluation Warning : The document was created with Spire.PDF for Python.
5048
r
ISSN:
2088-8708
po
wer
supply
v
oltage.
The
resistor
R
l
oad
means
the
load
resistor
,
and
I
l
oad
is
pro
vided
by
the
proposed
circuit.
The
logic
circuit
is
simple
logic
g
ate
lik
e
as
the
in
v
erter
and
N
AND
g
ate,
and
are
implemented
for
adjusting
size
of
the
output
PMOS
switch.
Its
total
propag
ation
delay
time
is
T
del
ay
.
The
feedback
circuit
senses
the
output
v
oltage
v
out
(
t
)
,
and
it
feedbacks
v
out
(
t
)
to
input.
The
feedback
f
actor
is
=
R
f
b
1
=
(
R
f
b
1
+
R
f
b
2
)
.
The
comparator
compares
the
v
oltage
between
the
reference
v
oltage
V
r
ef
and
v
out
(
t
)
,
and
it
controls
the
on/of
f
time
of
the
switched
capacitor
circuit.
The
equi
v
alent
circuit
of
the
comparator
can
be
modeled
by
the
ideal
quantizer
and
the
amplifier
which
has
the
finite
DC
g
ain
A
v
=
g
m
R
and
time
constant
R
C
as
sho
wn
in
top
left
of
Figure
2
(a).
Where
v
e
(
t
)
is
the
input
v
oltage
of
the
comparator
,
v
amp
(
t
)
is
the
output
v
oltage
of
the
amplification
stage,
v
comp
(
t
)
is
the
output
v
oltage
of
the
ideal
quantizer
,
g
m
is
the
transconductance,
R
is
the
equi
v
alent
output
resistance
of
the
transconductance
amplifier
,
C
is
the
parasitic
capacitance
which
is
total
capacitance
of
the
output
node
of
the
transconductance
amplifier
.
The
a
v
erage
output
v
oltage
V
out
in
the
steady
state
is
gi
v
en
as
follo
ws.
This
equation
is
identical
to
general
LDO.
V
out
=
A
v
1
+
A
v
V
r
ef
(1)
In
the
follo
wing
subsections,
the
circuit
operation
in
the
st
eady
state
is
analyzed
in
detail,
and
the
design
guidelines
of
the
circuit
parameters
with
re
g
ards
to
the
circuit
specification
are
defined.
(
a
)
(
b
)
(
c
)
1
a
mp
0
a
m
p
0
0
∆
∆
2
_
0
0
0
1
∆
0
∆
2
∆
2
a
mp
c
o
m
p
0
∆
2
0
0
a
mp
0
a
m
p
′
,
≅
≅
0
V
V
c
o
m
p
C
o
m
p
a
r
a
t
o
r
L
o
g
i
c
P
M
O
S
-
S
W
a
m
p
c
o
m
p
S
w
i
t
c
h
e
d
C
a
p
a
c
i
t
o
r
R
R
Figure
2.
Conceptual
models
of
the
proposed
circuit.
(a)
Circuit
model.
(b)
T
ypical
w
a
v
eforms
in
the
steady
state
under
the
condition
of
the
duty
ratio
50%.
(c)
T
ransient
ramp
response
of
the
comparator
.
3.1.
Design
Guideline
of
Output
Switched
Capacitor
Figure
2
(b)
sho
ws
the
typical
w
a
v
eforms
of
each
node
in
the
steady
state.
In
the
be
ginning,
we
analyze
the
char
ge
and
dischar
ge
operation
of
the
output
switched
capacitor
circuit
in
the
steady
state.
It
cl
arifies
the
design
guideline
of
the
output
PMOS
switch
R
out
when
the
design
parameters
V
out
,
V
D
D
,
R
l
oad
(
I
l
oad
)
are
Int
J
Elec
&
Comp
Eng,
V
ol.
9,
No.
6,
December
2019
:
5046
–
5059
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
5049
gi
v
en
as
a
specification.
The
char
ging
time
T
O
N
and
the
dischar
ging
time
T
O
F
F
are
automatically
controlled
by
the
ne
g
ati
v
e
feedback.
The
switching
c
ycle
time
T
cy
cl
e
is
gi
v
en
by
T
O
N
+
T
O
F
F
.
In
the
char
ging
period
(0
5
t
<
T
O
N
)
,
the
PMOS
switch
turns
on,
and
char
ge
operation
occurs
by
RC
step
response.
The
beha
vior
of
v
out
(
t
)
is
presented
by
dif
ferential
equation
(2).
R
l
oad
R
out
+
R
l
oad
V
D
D
=
C
L
R
0
out
dv
out
(
t
)
dt
+
v
out
(
t
)
(2)
where
R
0
out
=
R
out
R
l
oad
=
(
R
out
+
R
l
oad
)
,
and
the
current
of
the
feedback
circuit
I
f
b
=
V
r
ef
=R
f
b
1
is
ne-
glected
by
setting
R
0
out
R
f
b
1
+
R
f
b
2
.
The
solution
of
(2)
is
gi
v
en
as
follo
ws
by
fir
st
order
approximation
of
Maclaurin’
s
e
xpansion
and
assuming
as
T
O
N
C
L
R
0
out
.
v
out
(
t
)
=
R
l
oad
R
out
+
R
l
oad
V
D
D
n
1
e
t
C
L
R
0
out
o
+
v
out
(
t
=
0)
e
t
C
L
R
0
out
'
V
D
D
v
out
(
t
=0)
R
out
v
out
(
t
=0)
R
load
C
L
t
+
v
out
(
t
=
0)
(3)
In
the
dischar
ging
period
(
T
O
N
5
t
<
T
cy
cl
e
)
,
the
PMOS
switch
tur
n
s
of
f,
and
dischar
ge
operation
oc-
curs.
T
o
easily
calculation,
we
assume
as
t
=
T
O
N
!
t
0
=
0
.
The
beha
vior
of
v
out
(
t
)
and
its
solution
are
gi
v
en
as
(4)
and
(5)
in
the
same
w
ay
as
before
and
assuming
as
T
O
F
F
C
L
R
l
oad
.
0
=
C
L
R
l
oad
dv
out
(
t
0
)
dt
0
+
v
out
(
t
0
)
(4)
v
out
(
t
0
)
=
v
out
(
t
0
=
0)
e
t
0
C
L
R
load
'
v
out
(
t
0
=
0)
C
L
R
l
oad
t
0
+
v
out
(
t
0
=
0)
(5)
Ne
xt,
we
discuss
about
the
output
ripple
v
out
,
switching
duty
ratio
and
size
of
the
output
PMOS
switch.
The
first
terms
of
(3)
and
(5)
mean
the
sle
w
rate
of
char
ge
and
dischar
ge,
respecti
v
ely
.
Where
we
assume
approximately
as
v
out
(
t
=
0)
'
v
out
(
t
0
=
0)
'
V
out
about
these
first
terms,
and
we
define
as
I
out
=
(
V
D
D
V
out
)
=R
out
and
I
l
oad
=
V
out
=R
l
oad
.
Therefore,
the
beha
vior
of
v
out
(
t
)
at
one
c
ycle
operation
is
summarized
as
(6).
v
out
(
t
)
'
8
>
>
<
>
>
:
+
I
out
I
l
oad
C
L
t
+
v
out
(0)
=
K
1
t
+
v
out
(0)
(0
5
t
<
T
O
N
)
I
l
oad
C
L
(
t
T
O
N
)
+
v
out
(
T
O
N
)
=
K
2
(
t
T
O
N
)
+
v
out
(
T
O
N
)
(
T
O
N
5
t
<
T
cy
cl
e
)
(6)
where
K
1
=
(
I
out
I
l
oad
)
=C
L
and
K
2
=
I
l
oad
=C
L
are
the
char
ge
and
dischar
ge
sle
w
rate,
respecti
v
ely
.
The
output
ripple
v
oltage
v
out
of
each
c
ycle
and
the
duty
ratio
D
of
the
switching
gi
v
e
follo
wing
relations
by
focusing
transient
swing
of
v
out
(
t
)
.
v
out
=
K
1
T
O
N
=
K
2
(
T
cy
cl
e
T
O
N
)
=
K
2
T
O
F
F
(7)
D
=
T
O
N
T
cy
cl
e
=
K
2
K
1
K
2
=
I
l
oad
I
out
=
I
l
oad
V
D
D
V
out
R
out
(8)
From
(7)
and
(8),
follo
wing
relations
are
gi
v
en.
(
T
O
N
=
D
T
cy
cl
e
T
O
F
F
=
(1
D
)
T
cy
cl
e
(9)
v
out
=
K
1
D
T
cy
cl
e
=
K
2
(1
D
)
T
cy
cl
e
(10)
Equation
(8)
can
be
re
written
as
(11).
I
out
=
V
D
D
V
out
R
out
=
I
l
oad
D
(11)
Pr
oposal
and
design
methodolo
gy
of
switc
hing
mode
low
dr
opout...
(K
enya
K
ondo)
Evaluation Warning : The document was created with Spire.PDF for Python.
5050
r
ISSN:
2088-8708
The
drain-source
current
of
PMOS
transistor
in
linear
re
gion
is
I
ds
=
C
ox
K
p
f
(
V
g
s
V
th
)
V
ds
V
2
ds
=
2
g
,
where
is
the
carrier
mobility
,
C
ox
is
the
g
ate-oxide
capacitance,
K
p
is
the
aspect
ratio
(=
W
=L
)
of
the
output
PMOS
switch.
V
g
s
,
V
ds
and
V
th
are
the
g
ate-source
v
oltage,
the
drain-source
v
oltage
and
the
threshold
v
oltage,
respecti
v
ely
.
The
current
through
the
output
PMOS
switch
is
gi
v
en
as
follo
ws.
I
out
=
C
ox
K
p
f
(
V
D
D
V
th
)(
V
D
D
V
out
)
(
V
D
D
V
out
)
2
2
g
(12)
From
(11)
and
(12),
K
p
is
gi
v
en
as
follo
ws.
K
p
=
I
l
oad
max
C
ox
f
(
V
D
D
V
th
)(
V
D
D
V
out
)
(
V
D
D
V
out
)
2
2
g
D
(13)
where
I
l
oad
max
is
the
required
load
current
and
V
D
D
V
out
means
the
dropout
v
oltage.
The
size
of
the
output
PMOS
switch
can
design
based
on
(13).
3.2.
Deri
v
ation
of
Relationship
between
T
cy
cl
e
,
v
out
and
Cir
cuit
P
arameters
by
Theor
etical
T
ransient
Response
Analysis
Ne
xt,
the
output
v
olt
age
ripple
v
out
and
the
switching
c
ycle
T
cy
cl
e
are
analyzed
in
detail.
T
cy
cl
e
is
determined
by
the
delay
time
of
the
control
logic
T
del
ay
and
the
response
time
of
the
comparator
.
The
beha
vior
of
the
comparator
can
be
represented
by
the
ramp
response
as
sho
wn
in
Figure
2
(c),
where
V
th
comp
is
the
threshold
v
oltage
of
the
ideal
quantizer
,
and
v
0
is
the
initial
v
alue
of
the
input
ramp
w
a
v
eform.
When
K
is
the
sle
w
rate
of
the
input
ramp
w
a
v
eform,
the
input
v
oltage
of
the
comparator
can
be
gi
v
en
by
v
e
(
t
)
=
K
t
+
v
0
.
If
the
initial
v
alue
of
v
amp
(
t
)
is
defined
as
v
amp
(
t
=
0)
,
the
dif
ferential
equation
and
the
solution
of
v
amp
(
t
)
are
gi
v
en
as
follo
ws.
A
v
(
K
t
+
v
0
)
=
C
R
dv
amp
(
t
)
dt
+
v
amp
(
t
)
(14)
v
amp
(
t
)
=
A
v
K
n
t
C
R
(1
e
t
C
R
)
o
+
A
v
v
0
(1
e
t
C
R
)
+
v
amp
(
t
=
0)
e
t
C
R
(15)
By
using
(15),
the
beha
vior
of
v
amp
(
t
)
at
one
c
ycle
sho
wn
in
Figure
2(b)
can
be
analyzed
in
detail.
T
o
easily
calculation,
we
focus
on
the
magnitude
information,
and
define
D
=
50%
and
V
th
comp
=
0
.
In
this
condition,
the
output
v
oltages
at
the
inflection
points
can
be
e
xpressed
as
v
out
(
t
=
0)
=
V
out
v
out
=
2
and
v
out
(
t
=
T
O
N
)
=
V
out
+
v
out
=
2
.
T
1
and
T
2
are
the
response
time
which
v
amp
(
t
)
reaches
until
V
th
comp
in
on
and
of
f
period,
respecti
v
ely
.
(
T
1
=
T
O
N
T
del
ay
T
2
=
T
O
F
F
T
del
ay
(16)
A)
Char
ging
period
(0
5
t
<
T
O
N
)
In
the
char
ging
period
of
(0
5
t
<
T
1
)
,
the
initial
v
alue
of
v
e
(
t
)
is
v
1
=
+
v
out
=
2
in
case
of
focusing
on
the
magnitude
information,
and
the
final
v
alue
of
v
amp
(
t
)
is
v
amp
(
t
=
T
1
)
=
0
.
Using
these
conditions
and
Eq.
(15),
the
follo
wing
equation
is
gi
v
en.
v
amp
(
t
=
0)
=
A
v
+
v
out
2
(1
e
+
T
1
C
R
)
+
K
1
n
C
R
(
C
R
T
1
)
e
+
T
1
C
R
o
(17)
In
the
period
of
(0
5
t
<
T
O
N
)
,
v
amp
(
t
=
T
O
N
)
is
gi
v
en
by
using
(15)
and
(17)
as
follo
ws.
v
amp
(
t
=
T
O
N
)
=
A
v
+
v
out
2
(1
e
T
delay
C
R
)
+
K
1
(
C
R
T
O
N
)
(
C
R
T
1
)
e
T
delay
C
R
(18)
Int
J
Elec
&
Comp
Eng,
V
ol.
9,
No.
6,
December
2019
:
5046
–
5059
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
5051
B)
Dischar
ging
period
(
T
O
N
5
t
<
T
cy
cl
e
)
T
o
easily
calculation,
we
define
t
=
T
O
N
!
t
0
=
0
and
t
=
T
cy
cl
e
!
t
0
=
T
O
F
F
.
In
the
period
of
(0
5
t
0
<
T
2
)
,
the
initial
v
alue
of
v
e
(
t
0
)
is
v
2
=
v
out
=
2
,
and
the
final
v
alue
of
v
amp
(
t
0
)
is
v
amp
(
t
0
=
T
2
)
=
0
.
Using
these
condition
and
(15),
the
foll
o
wing
equation
is
gi
v
en.
v
amp
(
t
0
=
0)
=
A
v
v
out
2
(1
e
+
T
2
C
R
)
+
K
2
n
C
R
(
C
R
T
2
)
e
+
T
2
C
R
o
(19)
In
the
period
of
(0
5
t
0
<
T
O
F
F
)
,
v
amp
(
t
0
=
T
O
F
F
)
is
gi
v
en
by
using
(15)
and
(19)
as
follo
ws.
v
amp
(
t
0
=
T
O
F
F
)
=
A
v
v
out
2
(1
e
T
delay
C
R
)
+
K
2
(
C
R
T
O
F
F
)
(
C
R
T
2
)
e
T
delay
C
R
(20)
C)
Deri
v
ation
of
T
cy
cl
e
and
v
out
As
sho
wn
in
Figure
2(b),
since
the
initial
and
final
v
alues
of
v
amp
(
t
)
in
each
period
are
equal,
(21)
and
(22)
are
gi
v
en.
v
amp
(
t
=
0)
=
v
amp
(
t
0
=
T
O
F
F
)
(21)
v
amp
(
t
=
T
O
N
)
=
v
amp
(
t
0
=
0)
(22)
Equations
(23)
and
(24)
are
deri
v
ed
from
(17)
to
(22),
respecti
v
ely
.
+
v
out
2
(1
e
+
T
O
N
T
delay
C
R
)
+
K
1
C
R
(
C
R
T
O
N
+
T
del
ay
)
e
+
T
O
N
T
delay
C
R
=
v
out
2
(1
e
T
delay
C
R
)
+
K
2
(
C
R
T
O
F
F
)
(
C
R
T
O
F
F
+
T
del
ay
)
e
T
delay
C
R
(23)
v
out
2
(1
e
+
T
O
F
F
T
delay
C
R
)
+
K
2
C
R
(
C
R
T
O
F
F
+
T
del
ay
)
e
+
T
O
F
F
T
delay
C
R
=
+
v
out
2
(1
e
T
delay
C
R
)
+
K
1
(
C
R
T
O
N
)
(
C
R
T
O
N
+
T
del
ay
)
e
T
delay
C
R
(24)
From
(9)
and
(10),
(23)
and
(24)
are
the
function
of
T
cy
cl
e
.
Since
these
equations
are
transcendental,
the
y
are
dif
ficult
to
solv
e
algebraically
.
Therefore,
we
set
E
r
r
or
1
and
E
r
r
or
2
as
the
dif
ference
of
both
sides
of
(23)
and
(24),
and
numerically
solv
e
T
cy
cl
e
from
condition
that
E
r
r
or
1
and
E
r
r
or
2
become
zero.
E
r
r
or
1
and
E
r
r
or
2
are
gi
v
en
as
follo
ws
by
using
(23),
(24),
(9)
and
(10).
E
r
r
or
1
=
+
K
1
D
T
cy
cl
e
2
(2
e
+
D
T
cy
cle
T
delay
C
R
e
T
delay
C
R
)
+
K
1
C
R
(
C
R
D
T
cy
cl
e
+
T
del
ay
)
e
+
D
T
cy
cle
T
delay
C
R
K
2
(
C
R
(1
D
)
T
cy
cl
e
)
(
C
R
(1
D
)
T
cy
cl
e
+
T
del
ay
)
e
T
delay
C
R
=
0
(25)
E
r
r
or
2
=
K
1
D
T
cy
cl
e
2
(2
e
+
(1
D
)
T
cy
cle
T
delay
C
R
e
T
delay
C
R
)
+
K
2
C
R
(
C
R
(1
D
)
T
cy
cl
e
+
T
del
ay
)
e
+
(1
D
)
T
cy
cle
T
delay
C
R
K
1
(
C
R
D
T
cy
cl
e
)
(
C
R
D
T
cy
cl
e
+
T
del
ay
)
e
T
delay
C
R
=
0
(26)
Pr
oposal
and
design
methodolo
gy
of
switc
hing
mode
low
dr
opout...
(K
enya
K
ondo)
Evaluation Warning : The document was created with Spire.PDF for Python.
5052
r
ISSN:
2088-8708
0
.
0
0
0
1
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
0
.
0
1
0
.
1
1
1
0
1
0
0
v
o
u
t
[
m
V
]
f
a
m
p
[
M
H
z
]
f
a
m
p
-
v
o
u
t
(
I
l
o
a
d
_
m
a
x
=
1
m
A
,
T
d
e
l
a
y
=
1
n
s
)
C
a
l
c
.
S
i
m
.
0
.
1
F
1
F
1
0
F
0
.
0
0
1
0
.
0
1
0
.
1
1
0
.
0
1
0
.
1
1
1
0
1
0
0
T
c
y
c
l
e
[
s
e
c
]
f
a
m
p
[
M
H
z
]
f
a
m
p
-
T
c
y
c
l
e
(
I
l
o
a
d
_
m
a
x
=
1
m
A
,
T
d
e
l
a
y
=
1
n
s
)
C
a
l
c
.
S
i
m
.
0
.
1
F
1
F
1
0
F
C
a
l
c
,
S
i
m
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
0
.
0
0
0
1
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
T
c
y
c
l
e
[
s
e
c
]
C
L
[
F
]
C
L
-
T
c
y
c
l
e
(
f
c
a
m
p
=
1
M
H
z
,
T
d
e
l
a
y
=
1
n
s
)
0
.
1
m
A
1
m
A
1
0
m
A
1
0
0
m
A
C
a
l
c
.
S
i
m
.
C
a
l
c
0
.
1
m
A
1
m
A
1
0
m
A
1
0
0
m
A
L
a
r
g
e
e
r
r
o
r
i
s
d
u
e
t
o
1
s
t
o
r
d
e
r
a
p
p
r
o
x
i
m
t
i
o
n
o
f
s
w
i
t
c
h
e
d
-
c
a
p
a
c
i
t
o
r
.
0
.
0
1
0
.
1
1
1
0
1
0
0
1
0
0
0
0
.
0
0
0
1
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
v
o
u
t
[
m
V
]
C
L
[
F
]
C
L
-
v
o
u
t
(
f
c
a
m
p
=
1
M
H
z
,
T
d
e
l
a
y
=
1
n
s
)
0
.
1
m
A
1
m
A
1
0
m
A
1
0
0
m
A
C
a
l
c
.
S
i
m
.
L
a
r
g
e
e
r
r
o
r
i
s
d
u
e
t
o
1
s
t
o
r
d
e
r
a
p
p
r
o
x
i
m
t
i
o
n
o
f
s
w
i
t
c
h
e
d
-
c
a
p
a
c
i
t
o
r
.
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
0
.
0
0
0
1
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
T
c
y
c
l
e
[
s
e
c
]
C
L
[
F
]
C
L
-
T
c
y
c
l
e
(
f
a
m
p
=
1
M
H
z
,
T
d
e
l
a
y
=
1
n
s
)
0
.
1
m
A
1
m
A
1
0
m
A
1
0
0
m
A
C
a
l
c
.
S
i
m
.
C
a
l
c
0
.
1
m
A
1
m
A
1
0
m
A
1
0
0
m
A
L
a
r
g
e
e
r
r
o
r
i
s
d
u
e
t
o
1
s
t
o
r
d
e
r
a
p
p
r
o
x
i
m
t
i
o
n
o
f
s
w
i
t
c
h
e
d
-
c
a
p
a
c
i
t
o
r
.
0
.
0
1
0
.
1
1
1
0
1
0
0
1
0
0
0
0
.
0
0
0
1
0
.
0
0
1
0
.
0
1
0
.
1
1
1
0
v
o
u
t
[
m
V
]
C
L
[
F
]
C
L
-
v
o
u
t
(
f
a
m
p
=
1
M
H
z
,
T
d
e
l
a
y
=
1
n
s
)
0
.
1
m
A
1
m
A
1
0
m
A
1
0
0
m
A
C
a
l
c
.
S
i
m
.
L
a
r
g
e
e
r
r
o
r
i
s
d
u
e
t
o
1
s
t
o
r
d
e
r
a
p
p
r
o
x
i
m
t
i
o
n
o
f
s
w
i
t
c
h
e
d
-
c
a
p
a
c
i
t
o
r
.
(
a
)
(
b
)
Figure
3.
V
erification
results
of
T
cy
cl
e
and
v
out
(
D
=
50%
).
(a)
f
amp
dependence.
(b)
C
L
and
I
l
oad
max
dependence.
T
able
1.
Component
parameters
for
equi
v
alent
model
v
erification.
Component
name
(a)
f
amp
dependence
(b)
C
L
and
I
load
max
Unit
dependence
I
load
max
1
0.1,
1,
10,
100
mA
V
D
D
2
2
V
V
r
ef
0.5
0.5
V
A
v
1000
1000
-
=
R
f
b
1
R
f
b
1
+
R
f
b
2
500
k
ohm
500
k
ohm
+1300
k
ohm
500
k
ohm
500
k
ohm
+1300
k
ohm
-
V
out
1.8
1.8
V
R
out
200
2000,
200,
20,
2
ohm
D
50
50
%
C
L
0.1,
1,
10
0.0005,
0.001,
0.01,
0.1,
1,
10
F
f
amp
=
1
2
C
R
@
0.001,
0.01,
0.1,
1,
10,
100
1
MHz
T
delay
1
1
nsec
Equations
(25)
and
(26)
are
complicated,
b
ut
the
y
can
be
eas
ily
solv
ed
by
using
the
spreadsheet
softw
are.
Here,
(25)
and
(26)
deri
v
e
same
solution
T
cy
cl
e
on
the
condition
of
D
=
50%
.
The
dependence
analysis
of
the
v
arious
circuit
parameters
by
using
(25)
and
(10)
are
sho
wn
as
follo
ws.
Figure
3
sho
ws
the
comparison
between
calculated
and
simulated
(by
using
circuit
model
sho
wn
in
Figure
2(a))
v
alues
of
T
cy
cl
e
and
v
out
under
the
conditions
sho
wn
in
T
able
1.
Where
f
amp
=
1
=
(2
C
R
)
is
the
cut-of
f
frequenc
y
of
the
amplification
stage
of
the
comparator
.
From
Figure
3(a),
we
can
confirm
that
T
cy
cl
e
and
v
out
depend
on
f
amp
(also
depend
on
T
del
ay
,
b
ut
it
isn’
t
sho
wn),
and
v
out
can
reduce
by
adjusting
lar
ger
f
amp
and
selecting
lar
ger
C
L
.
f
amp
can
adjust
by
the
bias
current
of
the
comparator
,
and
T
del
ay
should
be
designed
t
o
minimize
the
number
of
g
ate
stages
of
the
logic
circuit.
T
o
minimi
ze
v
out
,
f
amp
should
be
high
(
T
cy
cl
e
should
be
small),
it
causes
increase
of
the
bias
current
of
the
comparator
and
the
switching
current.
Therefore,
v
out
has
trade-of
f
with
current
consumption.
From
Figure
3
(b),
we
can
confirm
that
v
out
depends
on
C
L
and
I
l
oad
max
.
W
e
can
find
the
dif-
ferences
between
calculati
on
and
simulation
results
when
C
L
and
I
l
oad
max
are
small
and
lar
ge,
respecti
v
ely
.
These
dif
ferences
are
caused
by
the
first
order
approximation
as
mentioned
in
deri
v
ation
of
(3)
and
(5).
Ho
w-
e
v
er
,
our
design
tar
get
is
smaller
range
of
I
l
oad
max
and
v
out
.
Thus,
we
can
estimate
circuit
characteristics
with
good
accurac
y
by
using
deri
v
ed
equations.
T
cy
cl
e
is
not
af
fected
C
L
and
I
l
oad
max
,
and
v
out
strongly
depends
on
C
L
and
I
l
oad
max
.
In
the
practical
design,
C
L
and
I
l
oad
max
are
gi
v
en
by
the
tar
get
specification.
Therefore,
we
should
design
v
out
by
adjusting
f
amp
.
3.3.
Curr
ent
Consumption
The
a
v
erage
current
consumption
of
the
proposed
circuit
is
sum
of
three
components
which
are
the
static
bias
current
of
the
comparator
I
comp
,
the
current
of
the
feedback
resistor
I
f
b
and
t
he
a
v
erage
switching
current
of
the
switching
parts
I
sw
.
I
D
D
=
I
comp
+
I
f
b
+
I
sw
=
I
comp
+
V
r
ef
R
f
b
1
+
X
i
C
i
V
2
D
D
T
cy
cl
e
(27)
where,
C
i
is
the
capacitance
of
each
switching
node
in
logic
circuit
and
the
g
ate
capacitance
of
the
output
PMOS
switch.
Int
J
Elec
&
Comp
Eng,
V
ol.
9,
No.
6,
December
2019
:
5046
–
5059
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
5053
3.4.
Design
Guideline
of
the
Pr
oposed
LDO
From
pre
vious
discussion,
we
sho
wed
that
the
circuit
characteristics
of
the
proposed
LDO
can
be
clarified
by
mathematical
analysis.
Therefore,
we
can
define
design
guideline
and
estimate
performance
of
the
proposed
circuit.
Firstly
,
the
size
of
output
PMOS
switch
is
desi
gned
by
using
(13).
Secondly
,
in
order
to
achie
v
e
the
required
v
out
,
the
relationship
between
T
cy
cl
e
,
v
out
and
circuit
parameters
is
estimated
by
(25)
or
(26).
Ne
xt,
f
amp
is
estima
ted
by
the
necessary
response
time
of
the
comparator
,
which
can
be
tuned
by
adjusting
the
tail
current
of
the
comparator
.
The
design
flo
w
is
sho
wn
in
Figure
4.
D
e
f
i
n
e
d
e
s
i
g
n
r
e
q
u
i
r
e
m
e
n
t
G
i
v
e
n
c
o
n
d
i
t
i
o
n
s
f
r
o
m
s
p
e
c
i
f
i
c
a
t
i
o
n
-
R
a
n
g
e
o
f
p
o
w
e
r
s
u
p
p
l
y
V
D
D
-
T
a
r
g
e
t
o
u
t
p
u
t
a
v
e
r
a
g
e
v
o
l
t
a
g
e
V
o
u
t
-
M
i
n
i
m
u
m
d
r
o
p
o
u
t
v
o
l
t
a
g
e
-
M
a
x
i
m
u
m
o
u
t
p
u
t
c
u
r
r
e
n
t
I
l
o
a
d
-
m
a
x
-
P
e
r
m
i
t
t
e
d
o
u
t
p
u
t
r
i
p
p
l
e
v
o
u
t
a
t
D
=
5
0
%
-
E
x
t
e
r
n
a
l
d
e
c
o
u
p
l
i
n
g
c
a
p
a
c
i
t
o
r
C
L
-
D
e
v
i
c
e
p
a
r
a
m
e
t
e
r
s
o
f
f
a
b
r
i
c
a
t
e
p
r
o
c
e
s
s
S
w
i
t
c
h
e
d
c
a
p
a
c
i
t
o
r
d
e
s
i
g
n
O
u
t
p
u
t
P
M
O
S
d
e
s
i
g
n
-
E
s
t
i
m
a
t
e
r
e
q
u
i
r
e
d
R
o
u
t
-
D
e
f
i
n
e
o
u
t
p
u
t
P
M
O
S
s
i
z
e
f
r
o
m
E
q
.
(
1
3
)
C
o
m
p
a
r
a
t
o
r
d
e
s
i
g
n
C
o
m
p
a
r
a
t
o
r
d
e
s
i
g
n
-
D
e
s
i
g
n
T
d
e
l
a
y
t
o
m
i
n
i
m
u
m
-
E
s
t
i
m
a
t
e
T
c
y
c
l
e
f
r
o
m
E
q
.
(
2
5
)
o
r
(
2
6
)
-
E
s
t
i
m
a
t
e
r
e
q
u
i
r
e
d
f
a
m
p
-
S
e
l
e
c
t
c
o
m
p
a
r
a
t
o
r
t
o
p
o
l
o
g
y
-
D
e
s
i
g
n
c
o
m
p
a
r
a
t
o
r
p
a
r
a
m
e
t
e
r
s
(
M
O
S
s
i
z
e
,
I
c
om
p
)
B
i
a
s
,
L
o
o
p
g
a
i
n
d
e
s
i
g
n
-
D
e
f
i
n
e
V
r
e
f
-
D
e
f
i
n
e
a
n
d
R
f
b1
,
R
f
b2
-
E
s
t
i
m
a
t
e
c
u
r
r
e
n
t
c
o
n
s
u
m
p
t
i
o
n
I
D
D
D
e
s
i
g
n
v
e
r
i
f
i
c
a
t
i
o
n
(
S
i
m
u
l
a
t
i
o
n
)
Figure
4.
Design
flo
w
of
proposed
LDO.
4.
CIRCUIT
IMPLEMENT
A
TION
The
complete
schematic
of
the
proposed
re
gulator
and
e
v
aluated
test
bench
are
sho
wn
in
Figure
5
(a).
The
circuit
surrounded
by
blue
dot
line
is
proposed
LDO.
In
this
st
u
dy
,
we
implemented
tw
o
functions
that
tw
o
selectors
for
the
output
current
ability
(OUTSEL[1:0])
and
po
wer
mode
(PMSEL).
The
func-
tion
tables
for
selectors
are
sho
wn
in
bottom
left
of
Figure
5
(a).
The
output
current
ability
selector
selects
the
number
of
acti
v
e
PMOS
switches
(
M
P
0
-
M
P
3
).
This
function
can
be
used
to
change
t
he
output
current
ability
by
sel
ecting
the
number
of
parallel
connection
of
PMOS
switches.
The
implementation
of
the
automatic
adjustment
of
this
function
is
future
w
ork.
The
po
wer
mode
selector
is
implemented
to
select
lo
w
po
wer
mode
(PMSEL=(0)
2
)
or
lo
w
ripple
mode
(PMSEL=(1)
2
)
depending
on
the
required
operation
mode.
In
detail,
it
adjusts
the
tail
current
of
the
comparator
I
T
AI
LC
O
M
P
.
If
the
required
noise
specification
of
the
load
circuit
of
LDO
is
se
v
erely
,
then
the
operation
mode
will
be
set
to
the
lo
w
ripple
mode
and
LDO
operates
on
smaller
output
ripple.
W
e
consider
the
parasitic
impedance
(inductance
L
P
and
resistance
R
P
)
model
lik
e
a
s
package
and
sock
et
surrounded
by
green
dot
line
in
Figure
5
(a)
for
estimating
practical
characteristics.
The
circuits
surrounded
by
red
dot
line
is
the
bio-medical
AFE
which
consists
of
IA
and
LPF
to
e
v
aluate
for
influence
of
LDO
output
ripple.
IA
architecture
consists
of
Fully
Balanced
Dif
ferential
Dif
ference
Amplifier
(FBDD
A)
and
Dif
ferential
Dif
ference
Amplifier
(DD
A)
proposed
in
[3].
The
LPF
is
3rd-order
gm-C
LPF
based
on
standard
PMOS
dif
ferential
amplifiers.
The
input
signal
V
I
N
is
sinusoidal
w
a
v
e
which
is
magnitude
of
10
V
pp
and
frequenc
y
of
500
Hz.
The
e
xternal
output
capaciti
v
e
load
(10
pF)
of
AFE
is
equi
v
alent
input
capacitance
of
the
oscill
o
s
cope.
Figure
5
(b)
sho
ws
the
schematic
of
comparator
.
W
e
selected
PMOS
input
dif
ferential
pair
and
lo
w
input
reference
v
oltage
V
r
ef
for
lo
wer
supply
v
oltage
operation.
The
ne
g
ati
v
e
resistance
circuit
in
the
comparator
is
implemented
to
enhance
the
transient
response
on
reasonable
lo
wer
bias
current.
The
feasibility
design
specifications
and
component
parameters
of
LDO
are
listed
in
T
able
2
and
3,
respecti
v
ely
.
In
this
study
,
we
use
1P
2M
0.6
m
CMOS
process
for
e
v
aluation
of
combination
with
our
e
xisting
AFE
circuits
[3].
The
output
PMOS
switch
is
sized
with
a
suitable
mar
gin
for
process,
v
oltage,
and
temperature
(PVT)
v
ariations
by
using
(
1
3)
.
The
def
ault
v
alue
of
OUTSEL[1:0]
is
(11)
2
in
this
design.
R
f
b
1
and
R
f
b
2
are
selected
lar
ge
v
alue
for
reducing
stat
ic
current
consumption.
As
mentioned
pre
viously
,
v
out
can
be
designed
by
adjusting
f
amp
,
it
means
that
the
tail
current
of
the
comparator
I
T
AI
L
C
O
M
P
should
be
selected
by
considering
the
de
vice
performance
of
MOS
transistors.
From
the
specification
of
test
design,
the
tail
currents
of
lo
w
po
wer
and
lo
w
ripple
mode
are
respecti
v
ely
set
0.25
A
and
2.25
A
in
order
to
consider
reasonable
performance
and
po
wer
consumption.
When
the
operation
mode
changed
to
lo
w
ripple
mode,
the
output
ripple
v
oltage
reduced
t
o
about
1
mV
instead
of
consuming
lar
ge
quiescent
current.
The
layout
diagram
is
sho
wn
in
Figure
5
(c).
From
this
layout
diagram,
the
circuit
area
is
about
0.0173
mm
2
in
spite
of
using
0.6
m
design
rules.
Pr
oposal
and
design
methodolo
gy
of
switc
hing
mode
low
dr
opout...
(K
enya
K
ondo)
Evaluation Warning : The document was created with Spire.PDF for Python.
5054
r
ISSN:
2088-8708
2
5
0
I
R
R
0
1
V
_
A
F
E
I
N
1
0
O
u
t
p
u
t
S
e
l
e
c
t
o
r
P
r
o
p
o
s
e
d
L
D
O
B
u
f
f
e
r
A
m
p
f
o
r
e
v
a
l
u
a
t
i
o
n
P
a
r
a
s
i
t
i
c
i
m
p
e
d
a
n
c
e
s
o
f
P
a
c
k
a
g
e
!
C
o
m
p
a
r
a
t
o
r
L
P
F
P
M
S
E
L
E
N
O
U
T
S
E
L
[
1
:
0
]
M
P
3
M
P
2
M
P
1
M
P
0
[
1
]
[
0
]
0
*
*
O
F
F
O
F
F
O
F
F
O
F
F
1
0
0
O
F
F
O
F
F
O
F
F
E
n
a
b
l
e
1
0
1
O
F
F
O
F
F
E
n
a
b
l
e
E
n
a
b
l
e
1
1
0
O
F
F
E
n
a
b
l
e
E
n
a
b
l
e
E
n
a
b
l
e
1
1
1
E
n
a
b
l
e
E
n
a
b
l
e
E
n
a
b
l
e
E
n
a
b
l
e
F
u
n
c
t
i
o
n
o
f
O
u
t
p
u
t
S
e
l
e
c
t
o
r
P
M
S
E
L
M
o
d
e
I
T
A
I
L
C
O
M
P
0
L
o
w
p
o
w
e
r
(
L
a
r
g
e
r
i
p
p
l
e
)
S
m
a
l
l
1
L
o
w
r
i
p
p
l
e
(
L
a
r
g
e
p
o
w
e
r
)
L
a
r
g
e
F
u
n
c
t
i
o
n
o
f
P
o
w
e
r
M
o
d
e
S
e
l
e
c
t
o
r
I
A
V
_
A
F
(
a
)
(
b)
(
c
)
Figure
5.
Designed
circuit,
simulated
test
bench
and
layout.
(a)
Ov
ervie
w
of
circuit
and
test
bench.
(b)
Schematic
of
comparator
.
(c)
Layout
diagram
of
LDO.
T
able
2.
Design
specifications
of
test
design.
Circuit
Item
v
alue
LDO
CMOS
Process
1P
2M
0.6
m
CMOS
T
emperature
range
–20
to
95
C
Po
wer
supply
V
D
D
1.9
V
-
2.2
V
Output
v
oltage
V
out
1.8
V
Minimum
dropout
v
oltage
V
do
min
0.1
V
Maximum
load
current
I
load
max
50
A
External
decoupling
capacitor
C
L
0.1
F
Permitted
output
ripple
v
oltage
10
mV
(
I
load
=
5
A
-
50
A)
Permitted
output
ripple
frequenc
y
10
kHz
(
I
load
=
5
A
-
50
A)
AFE
Po
wer
supply
v
oltage
1.8
V
Po
wer
supply
current
10
A
-
20
A
Minimum
input
signal
magnitude
10
Vpp
Input
signal
frequenc
y
range
1
kHz
T
otal
g
ain
68
dB
LPF
cutof
f
frequenc
y
2
kHz
PSRR
-60
dB
(
10
kHz)
Int
J
Elec
&
Comp
Eng,
V
ol.
9,
No.
6,
December
2019
:
5046
–
5059
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Elec
&
Comp
Eng
ISSN:
2088-8708
r
5055
T
able
3.
Component
parameters
of
LDO.
Component
name
Size
/
v
alue
Component
name
Size
/
v
alue
M
P
0
M
P
3
6
m
/
0.6
m,
m=1
R
f
b
1
1
Mohm
PMOS
of
in
v
erters
2.4
m
/
0.6
m,
m=1
R
f
b
2
2.6
Mohm
NMOS
of
in
v
erters
1.2
m
/
0.6
m,
m=1
C
I
N
0.1
F
PMOS
of
N
ANDs
2.4
m
/
0.6
m,
m=1
C
L
0.1
F
NMOS
of
N
ANDs
2.4
m
/
0.6
m,
m=1
R
L
10
mohm
M
P
M
1
2.4
m
/
0.6
m,
m=2
L
L
100
pH
M
P
M
2
2.4
m
/
0.6
m,
m=2
or
18
R
P
100
mohm
M
P
C
1
M
P
C
4
2.4
m
/
0.6
m,
m=4
L
P
2
nH
M
P
C
5
M
P
C
6
2.4
m
/
0.6
m,
m=1
V
r
ef
0.5
V
M
N
C
1
M
N
C
4
1.2
m
/
0.6
m,
m=4
I
B
I
AS
C
O
M
P
250
nA
M
N
C
5
M
N
C
6
1.2
m
/
0.6
m,
m=1
M
N
C
7
M
N
C
8
1.2
m
/
0.6
m,
m=3
5.
SIMULA
TION
RESUL
TS
The
proposed
circuit
has
been
e
v
aluated
by
using
SPICE
sim
ulator
with
1P
2M
0.6
m
CMOS
process
de
vice
parameters.
The
nominal
conditions
are
V
D
D
=
2
:
0
V
,
27
C
and
OUTSEL[1:0]=(11)
2
and
PMSEL=(0)
2
.
Figure
6
sho
ws
the
typical
w
a
v
eforms
when
the
load
current
is
changed
from
10
A
to
50
A,
and
the
operation
mode
is
also
changed
from
lo
w
po
wer
mode
to
lo
w
ripple
mode
at
0.6
msec
simultaneously
.
The
output
w
a
v
eform
sho
ws
no
ringing
and
o
v
ershoots
other
than
the
switching
ripple.
The
of
fset
v
oltage
of
V
out
between
tw
o
modes
is
enough
small
as
3.5
mV
.
Figure
7
sho
ws
the
load
re
gulation
and
po
wer
supply
v
oltage
dependence
at
nominal
condition.
From
Figure
7
(a),
the
load
re
gulation
is
less
than
1
mV
under
the
condition
that
the
range
of
I
l
oad
is
0
A
to
50
A.
The
line
re
gulation
is
about
10.3
mV/V
(0.57
%
/V)
under
the
condition
that
I
l
oad
is
50
A
and
V
D
D
is
from
1.9
V
to
2.2
V
.
The
quiescent
current
I
D
D
is
about
1
A
from
Figure
7
(b).
W
e
can
also
confirm
that
the
maximum
v
out
and
minimum
F
cy
cl
e
(=1/
T
cy
cl
e
)
are
5.2
mV
and
19
kHz,
respecti
v
ely
from
Figures
7
(c)
and
(d).
From
Figure
7
(e),
we
could
confirm
that
the
duty
ratio
increases
with
increasing
of
I
l
oad
.
The
current
ef
ficienc
y
is
also
increase
with
increasing
of
I
l
oad
from
Figure
7(f).
The
PVT
v
ariations
of
fundamental
perform
ances
are
sho
wn
in
Figures
8(a)
to
(f).
The
e
v
aluated
corner
conditions
are
TT
(typical
NMOS
and
PMOS),
SS
(slo
w
NMOS
and
slo
w
PMOS)
and
FF
(f
ast
NMOS
and
f
ast
PMOS).
V
D
D
and
temperature
ranges
are
from
1.9
V
to
2.2
V
and
from
–20
C
to
95
C,
respecti
v
ely
.
This
results
sho
w
rea
sonable
performance
with
satisfying
the
design
specification
sho
wn
in
T
able
2.
Figure
8
depicts
PVT
v
ariation
of
load
re
gulation
and
supply
v
oltage
dependence.
Figure
6.
T
ypical
transient
w
a
v
eform.
Pr
oposal
and
design
methodolo
gy
of
switc
hing
mode
low
dr
opout...
(K
enya
K
ondo)
Evaluation Warning : The document was created with Spire.PDF for Python.