Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
5, N
o
. 4
,
A
ugu
st
2015
, pp
. 69
5
~
70
0
I
S
SN
: 208
8-8
7
0
8
6
95
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Little Core Based
Syst
em on Ch
ip Platf
o
rm
for Int
e
rnet
of
Thing
San
g
Don Kim
an
d
Se
un
g Eun
Lee
Departement
of Electronic Engin
eerin
g
,
Seou
l National University of Sc
ience and Techno
log
y
,
Seo
u
l,
Korea
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Feb 5, 2015
Rev
i
sed
Ap
r
30
, 20
15
Accepted
May 25, 2015
Although the technolog
y
scalin
g has enab
led d
e
signers to integrate
a larg
e
number of hardware blocks onto a si
ngle chip
realizing S
y
stem on Chip
(SoC), problems arising
from leakage
curren
t
hav
e
made pow
er r
e
duction
an
im
portant issue.
The inte
rnet of
thi
ng (IoT) platform has restricted power
consumption because of
batter
y power. In
this
paper, we propo
se our little
core based IoT platform focusing on
the low po
wer and expand
ability
. Th
e
experimental res
u
lts dem
onstrate the feasibility
of
our proposal to
the Io
T.
Keyword:
B
l
uet
oot
h
Cortex
-M
0
FPGA
I
n
tern
et
o
f
Th
in
g (I
oT)
W
i
reless C
o
mm
u
n
i
catio
n
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Seun
g Eu
n Lee,
Depa
rt
em
ent
of El
ect
r
oni
c
En
gi
nee
r
i
n
g,
Seou
l Nation
a
l
Un
iv
ersity o
f
Scien
ce an
d Tech
no
log
y
,
2
1
9
C
h
an
gh
ak
Hall, Seo
u
l
Natio
n
a
l Un
iversi
ty o
f
Scien
ce an
d Tech
no
log
y
2
3
2
Go
ngn
eung
g
il,
Now
on-
gu
, Seou
l 1
39-
74
3,
Rep
u
b
lic
of
Kor
ea.
Em
a
il: seu
n
g
.lee@seou
ltech.ac.kr
1.
INTRODUCTION
Mo
d
e
rn In
ternet o
f
Th
ing
(IoT) allows th
at
o
b
j
ect is
o
r
g
a
nized
on
th
e n
e
t
w
ork u
s
i
n
g th
e sm
a
ll Io
T
pl
at
fo
rm
. The wi
rel
e
ss com
m
uni
cat
i
o
n i
s
us
ual
l
y
used as
a n
e
twork
of IoT, and
it tran
smits a
s
m
al
l p
ack
et
with a device s
t
atus. Eve
n
though th
e t
ech
no
l
ogy
scal
i
ng
ha
s enabl
e
d desi
gners to inte
grat
e a large num
ber of
har
d
ware bl
oc
ks, t
h
e u
n
n
ece
ssary
har
d
war
e
i
s
not
requi
red beca
use it increase
s
th
e leakage c
u
rrent
of the
process
o
r. The
low powe
r consum
ption is m
o
re im
portant
rather tha
n
hi
gh
perform
a
nce because m
o
st of IoT
platfo
rm
has r
e
stricted p
o
w
e
r b
u
dget f
o
r s
m
all batte
ry
.
The
Co
rtex
-M
0 pr
ocess
o
r has
l
o
w p
o
we
r pr
o
p
erties
wh
ich
u
s
e sm
aller g
a
te co
un
t.
M
ode
rn
Io
T s
y
st
em
and wea
r
abl
e
de
vi
ces
have
bee
n
st
u
d
i
ed usi
n
g
di
ve
r
s
e wi
rel
e
ss net
w
o
r
k
[
1
-
4
]
.
The dat
a
c
o
m
m
uni
cat
i
on am
ong
o
b
ject
s real
i
zes ubi
qui
t
o
us c
o
m
put
i
ng a
n
d va
r
i
ous
user e
x
p
e
ri
ence
appl
i
cat
i
o
ns [
5
-
1
0]
. O
n
t
h
e
s
e st
udi
es, t
h
e sens
or
no
de
usual
l
y
uses
a
m
i
cropr
oce
ssor
w
h
i
c
h i
n
cl
ude
s
restrictiv
e h
a
rdware
p
e
ri
p
h
e
ral. Th
e FPGA
h
a
s flex
ib
ility an
d
can
im
p
l
emen
t an
exp
a
nd
ab
le system
.
Also
,
core an
d pe
ri
p
h
eral
sy
st
em
have im
port
a
nt
pr
o
p
ert
i
e
s ab
o
u
t
l
o
w p
o
w
e
r c
ons
um
pt
i
on. T
h
e p
o
we
r effi
ci
ency
of
t
h
e sy
st
em
com
ponent
s a
n
d t
h
e
ot
he
r
peri
p
h
e
ral
s
ha
s
been
st
udi
e
d
f
o
r t
h
i
s
p
u
r
p
ose
[1
1-
1
4
]
.
In t
h
i
s
pa
pe
r, we im
pl
em
ent
an IoT
pl
at
fo
r
m
t
h
at
i
n
cl
ude
s a C
o
rt
ex-M
0
proc
esso
r,
A
H
B
-
Li
t
e
b
u
s
in
terface, m
e
mo
ry con
t
ro
ller,
RS-232
co
m
m
uni
cat
i
o
n m
o
d
u
l
e
, a
n
d
V
G
A
cont
rol
l
e
r.
Th
e r
e
st of
ou
r p
a
p
e
r
is or
g
a
nized
as f
o
llow
s
.
W
e
f
i
rst briefly in
tro
d
u
ces th
e
features of the Corte
x
-
M
0
DS ba
sed I
o
T pl
at
f
o
rm
i
n
sect
i
on 2
,
an
d prese
n
t
t
h
e ha
r
d
wa
re i
m
pl
ement
a
t
i
on o
f
o
u
r
prot
ot
y
p
e i
n
S
ect
i
o
n
3
.
Sectio
n
4
sho
w
s th
e exp
e
rimen
t
al resu
lt an
d Section
5
co
n
c
l
u
d
e
s th
is pap
e
r b
y
ou
tlin
in
g th
e d
i
recti
o
n
for
fu
t
u
re wo
rk
on
th
is
top
i
c.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 5
,
N
o
. 4
,
Au
gu
st 2
015
:
69
5
–
70
0
69
6
2.
IoT PL
ATFO
RM
Th
e Io
T
p
l
atform
co
n
s
ists o
f
th
e little co
re, th
e system
b
u
s
an
d
t
h
e
p
e
ri
p
h
erals. Th
e Cort
ex
-M
0
core
i
s
l
o
w
po
wer
32
bi
t
m
i
cropr
ocess
o
r t
h
at
h
a
s 1
2
K
gat
e
s
and t
h
e m
a
xi
m
u
m
operat
i
n
g f
r
eq
ue
ncy
i
s
un
de
r
10
0M
Hz
. T
h
i
s
co
re ca
nn
ot
c
onst
r
uct
t
h
e
Io
T pl
at
f
o
rm
by
o
n
esel
f.
T
h
e
sy
st
em
bus a
n
d t
h
e
peri
p
h
e
r
al
s are
requ
ired
to
sup
port th
e op
eratio
n
of th
e core. Most
of t
h
e IoT
syste
m
, the pe
ri
pherals
include t
h
e
network
i
n
t
e
rfaci
ng ha
r
d
wa
re f
o
r t
h
e
com
m
uni
cation
.
The wi
rel
e
ss com
m
uni
cat
i
on i
s
used
on t
h
e I
o
T sy
st
em
t
o
co
mm
u
n
i
cate
with
th
e o
t
h
e
r
d
e
v
i
ces. In
th
i
s
n
e
two
r
k
,
th
e ex
p
a
n
d
a
b
ility is
m
o
re i
m
p
o
r
tan
t
rath
er th
an
h
i
gh
spee
d c
o
m
m
uni
cat
i
on.
The Operating Syste
m
(OS) i
s
requ
ired
b
e
cau
s
e it is h
e
lp
fu
l for h
a
n
d
i
n
g
th
e p
ack
et to
th
e n
e
twork.
The Li
n
u
x
i
s
a gene
ral
p
u
r
p
ose o
p
e
r
at
i
ng
sy
st
em
t
h
at
has been
p
o
rt
ed
on
vari
ou
s p
r
o
cesso
rs. H
o
we
ver
,
i
t
req
u
ires a
hi
g
h
per
f
o
r
m
a
nce pr
ocess
o
r an
d
M
e
m
o
ry
M
a
n
a
gem
e
nt Unit
(M
M
U
)
ha
rd
w
a
re. T
h
e C
o
rte
x
-M
0
core is little core and it does
not cont
ain MM
U. The
r
efore,
our system
adopt
s a uC/OS-II
real tim
e
kerne
l
that
su
ppo
r
t
s
up
t
o
6
4
task
s.
I
n
add
itio
n
,
it supp
or
ts TCP/IP ether
n
et
p
a
ck
et lib
r
a
r
y
fo
r th
e
netw
or
k.
2.1.
Pr
ocess
o
r and Sys
t
em
Bus
AR
M
C
o
r
p
orat
i
on i
s
p
r
o
v
i
d
i
n
g t
h
e C
o
rt
ex
-
M
0 Desi
gn St
a
r
t
(C
o
r
t
e
x-M
0
DS) c
o
re, an
d i
t
operat
e
s at
50M
Hz fr
eq
ue
ncy
.
The
basi
c C
o
rt
ex
-M
0 co
re has va
ri
o
u
s
opt
i
o
ns f
o
r o
p
t
i
m
i
zati
on suc
h
as t
h
e perf
or
m
a
nce
of m
u
ltiplier, the
num
b
er of i
n
terrup
t, a
n
d t
h
e JTAG i
n
terface.
Howe
ver the C
o
rte
x
-M
0
DS c
o
re i
n
cludes the
si
m
p
lest hardware. M
u
ltiplier
takes
13 cloc
ks for each m
u
lt
iplications, t
h
e
num
b
er of
int
e
rrupt is fixe
d
at 32,
and
d
o
es n
o
t
u
s
e JTA
G
. T
h
e
C
o
rt
ex
-M
0
DS
has wea
k
ness
on
per
f
o
rm
ance opt
i
m
i
zati
on,
but
i
t
has a s
m
al
l
e
r
g
a
te coun
t rat
h
er th
an
t
h
e C
o
rtex
-M0 core. It
is su
itab
l
e
fo
r
sm
a
ll sized
low
p
o
wer pro
c
esso
r.
Also
, t
h
is littl
e co
re is syn
t
h
e
sizab
le in
an
FPGA and
it can
o
r
g
a
n
i
ze a p
r
o
c
essor th
at con
t
ain
s
flex
ib
le p
e
ripherals. Th
e FPGA en
ab
les co
nfig
uring
th
e
sy
st
em
bus and t
h
e peri
p
h
eral
ha
rd
ware
. The C
o
rt
e
x
-
M0 DS core us
es AMBA AHB-Lite syste
m
bus t
o
cont
rol
4GB a
d
dress s
p
ace and it enables only one
master
d
e
v
i
ce.
In
t
h
is syste
m
, arb
itratio
n
is no
t requ
ired
an
d i
t
i
s
hel
p
ful
t
o
re
d
u
ce po
wer c
o
ns
um
pt
i
on. Th
e Di
rec
t
Me
m
o
ry Acce
ss (DM
A
)
hardwa
re cannot be use
d
on the
syste
m
bus because the system bus does not allow
th
e m
a
ster
d
e
v
i
ce ex
cep
t th
e
Co
r
t
ex-
M
0
D
S
co
r
e
. Th
is is a w
eakn
e
ss i
n
ter
m
s o
f
d
a
ta pr
ocessin
g
ev
en
though
t
h
e I
o
T
pl
at
f
o
r
m
does n
o
t
dea
l
wi
t
h
bi
g
dat
a
.
2
.
2
.
P
e
r
i
p
h
e
ra
l Sy
s
t
em
Th
e p
e
riph
eral
syste
m
su
p
ports th
e o
p
e
ration
o
f
th
e co
re. Th
e Figu
re
1
illu
strates th
e b
l
o
c
k
d
i
agra
m
of the m
e
m
o
ry subsystem
.
The R
O
M is a
read-only area
that stores a
bi
nary
file. T
h
e
core
rea
d
s
the
code
fr
om
t
h
e R
O
M
,
and t
h
e t
e
m
porary
dat
a
i
s
st
ore
d
i
n
t
h
e
R
A
M
.
The
s
e
m
e
m
o
ri
es are im
pl
em
ent
e
d b
y
usi
n
g
i
n
t
e
rnal
m
e
m
o
ry
of
t
h
e F
P
G
A
t
o
s
u
pp
o
r
t
h
i
gh
per
f
o
r
m
a
nce. It
ha
s a d
e
pen
d
e
n
cy
o
n
t
h
e i
n
here
nt
st
r
u
ct
u
r
e o
f
the FPGA s
u
c
h
as a
m
e
m
o
ry size and a m
e
m
o
ry interf
ace. Th
e m
e
m
o
r
y
su
bsystem
u
s
es qu
ad 8 b
it me
m
o
r
y
bl
oc
ks beca
us
e t
h
e C
o
rt
ex
-
M
0 DS c
o
re
uses by
t
e
ad
d
r
essi
n
g
. T
h
e
wri
t
e
by
t
e
ena
b
l
e
si
gnal
i
s
assert
ed
according to the byte addres
s of AHB-Lite
write comma
nd
. On the other ha
nd the re
ad data returns
32 bit
s
and ignores
by
te address
.
T
h
e
core internally
uses
the
neces
sary bytes am
ong these
32
bits.
Th
e U
S
A
R
T uses RS-
232
p
r
o
t
o
c
o
l
an
d
it su
ppo
r
t
s up
to
1
152
00b
ps to
co
mm
u
n
i
cate
w
ith
th
e o
t
her
devi
ces
. It
col
l
ect
s a requi
re
d dat
a
fr
om
ot
her devi
ces
or t
r
a
n
sm
i
t
s
dat
a
t
o
the h
o
st
PC
. Th
e USAR
T h
a
s FIF
O
i
n
o
r
d
e
r t
o
e
n
hance
t
h
e
sl
o
w
c
o
m
m
uni
cat
i
on s
p
ee
d c
o
m
p
ared t
o
t
h
e
sy
st
em
bus.
Thi
s
c
o
m
m
unicat
i
on
har
d
ware ca
n
b
e
im
pl
em
ent
e
d o
n
F
P
G
A
.
O
n
t
h
e ot
her
ha
n
d
,
alm
o
st
of
wi
re
l
e
ss com
m
uni
cat
i
on
uses a
n
al
og
h
a
rdware, an
d wh
ich canno
t b
e
in
tegrated
o
n
th
e FP
GA. This
anal
og hardware
is a
v
a
ilable as a
n
external m
odul
e, and t
h
e
US
ART could
be
us
ed
for c
ont
rolling the m
o
dule.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Little Co
re Ba
sed
S
o
C
Pla
tfo
rm fo
r In
tern
et
o
f
Th
ing
(Io
T)
(
S
eu
ng
Eu
n
Le
e)
69
7
Fi
gu
re
1.
B
l
oc
k
di
ag
ram
of m
e
m
o
ry
su
bsy
s
t
e
m
Fi
gu
re
2.
B
l
oc
k
di
ag
ram
of V
G
A
co
nt
r
o
l
l
e
r
Fi
gu
re
3.
R
e
gi
s
t
er ba
n
k
of C
o
r
t
ex-M
0
D
S
c
o
r
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 5
,
N
o
. 4
,
Au
gu
st 2
015
:
69
5
–
70
0
69
8
Fi
gu
re
4.
Im
pl
em
ent
e
d I
o
T
pl
at
form
Ev
en
th
oug
h
th
e VGA contro
ller is n
o
t
an
essen
tial un
it o
n
th
e IoT syste
m
, i
t
su
ppo
rts th
e
visualization
of system
status (See
Fi
gure
2.). Th
e m
a
x
i
mu
m
reso
lu
tion
is 64
0
⨉
48
0 and
it su
ppo
r
t
s 24
b
it
true col
o
r. The VGA controller has
im
age buffe
r that stores eac
h im
a
g
e fram
e
. On
the IoT
platform
,
the
im
age buffe
r uses SRAM or
SDRAM
.
The
SDRAM is sl
o
w
er t
h
a
n
SR
A
M
, ho
we
ver i
t
has a hi
gh ca
paci
t
y
and c
h
ea
per than the ot
her me
m
o
ries. The i
m
age buffe
r si
ze should
be large
r
tha
n
fra
me size of an im
age
.
There
f
ore, the
minim
u
m
size
of
the im
age buffer is 900Kbytes.
2.
3.
Oper
a
t
i
n
g S
y
s
t
em
The
uC
/
O
S
-
I
I
i
s
a ki
n
d
of
real
-t
i
m
e OS t
h
at
has
bee
n
p
o
r
t
e
d
on
t
h
e v
a
ri
o
u
s
pr
ocess
o
rs
. T
h
i
s
ope
rat
i
n
g sy
st
em
uses a sm
al
l
ker
n
el
an
d i
t
does n
o
t
req
u
i
r
e
t
h
e M
M
U
. Th
e num
ber of m
a
xi
m
u
m
t
a
sk i
s
up t
o
64, a
n
d the
re
serve
d
tas
k
is
confi
g
ured ac
cording t
o
t
h
e
so
ft
wa
re a
ppl
i
cat
i
on. T
h
e i
m
pl
em
ent
e
d t
a
sk i
s
initialized whe
n
the start of
a
n
operating syste
m
. The task initializa
tion seque
nce should
be porte
d
accordi
ng
to the architec
t
ure of the co
r
e
. Fi
gu
re 3 sh
ows a re
gi
st
er
of t
h
e C
o
rt
e
x
-M
0 co
re. It
consi
s
t
s
o
f
1
3
gene
ral
purpose
re
gist
er a
n
d s
o
m
e
of s
p
ecial
re
gisters.
The
stack
of task is
have
to
pre
p
a
r
e the
m
e
m
o
ry space for
cont
e
x
t
s
w
i
t
c
hi
ng
.
Ho
we
ver,
i
n
case
o
f
C
o
rt
e
x
-M
0
DS c
o
re
,
t
h
e
gene
ral
pu
rp
ose
regi
st
e
r
8 t
o
1
2
i
s
n
o
t
u
s
ed i
n
t
h
e co
nt
e
x
t
sw
i
t
c
hi
ng.
It
i
s
i
m
port
a
nt
f
o
r
k
e
rnel
p
o
rt
i
n
g s
e
que
nce.
T
h
e
cont
e
x
t
s
w
i
t
c
h
i
ng
o
p
erat
i
o
n
has
t
o
pre
p
are
space
fo
r a
gene
ral
p
u
r
p
ose re
gi
st
er
regi
on
, w
h
i
c
h
i
n
cl
u
d
es f
r
o
m
0 t
o
7,
t
h
e s
p
e
c
i
a
l
pur
p
o
se
re
gi
st
er
regi
on
an
d
t
h
e st
ack poi
nt
er r
e
gi
o
n
.
3.
IMPLEME
N
TATION
We a
d
opt
t
h
e
Al
t
e
ra
DE
1
bo
ard
[
1
5]
f
o
r
i
m
pl
em
ent
a
t
i
on o
f
t
h
e
I
o
T
pl
at
f
o
rm
wh
ose
fea
t
ures
i
n
cl
u
d
e
Altera Cyclo
n
e II FPGA,
8MB SDRAM
.
Th
e im
p
l
e
m
e
n
te
d
ha
rdware
is available
for
downloa
d
a
s
a pre-
con
f
i
g
ure
d
Ve
ri
l
og
HD
L.
O
u
r sy
st
em
i
n
clude
s a C
o
rt
e
x
-
M
0 DS c
o
r
e
,
an AM
B
A
A
H
B
-Li
t
e
sy
st
em
bus
, a
m
e
m
o
ry
su
bsy
s
t
e
m
,
a US
AR
T an
d a
VG
A
co
nt
r
o
l
l
e
r
(Se
e
Fi
g
u
re
4
)
.
C
o
rt
e
x
-M
0
DS
core
i
s
pr
ovi
d
e
d
by
ARM, and
it d
o
e
s no
t su
ppo
rt
an
y h
a
rdware co
nfigu
r
ation
o
p
tion
s
su
ch
as
m
u
ltip
lier, n
u
m
b
er o
f
in
terrup
t an
d
JTAG interfac
e. AMBA
AHB-Lite syste
m
bus di
vide
s t
h
e 4GB a
d
dressing space t
o
support m
u
ltipl
e
slave
devi
ces
. The a
r
bi
t
r
at
i
on
har
d
ware i
s
n
o
t
re
q
u
i
r
e
d
beca
use
of s
u
p
p
o
rt
i
n
g
onl
y
o
n
e m
a
st
er de
vi
ce. The
m
e
m
o
ry
su
bsystem
co
n
t
ain
s
th
e
12
8
KB ROM and th
e
3
2
KB
RAM. Th
ese
me
m
o
ry cap
acities are adju
stab
le
depe
n
d
i
n
g
o
n
t
h
e i
n
t
e
r
n
al
m
e
m
o
ry
si
ze
of
t
h
e
FP
GA
. T
h
ere
are
t
w
o
com
m
uni
cat
i
on c
h
a
nnel
s
;
U
S
AR
T
1
tran
sm
its d
a
ta
th
roug
h
t
h
e
wireless m
o
d
u
le an
d
USAR
T2
is co
llecting
d
a
ta for tran
sm
issio
n
.
The VGA
co
n
t
ro
ller is v
i
su
alizin
g
t
h
e statu
s
o
f
system v
i
a ex
tern
al
LCD m
o
n
ito
r. Th
e
VGA con
t
ro
ller in
tegrates an
SDR
A
M
co
nt
r
o
l
l
e
r whi
c
h op
er
ates at 100M
H
z
fre
que
ncy.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Little Co
re Ba
sed
S
o
C
Pla
tfo
rm fo
r In
tern
et
o
f
Th
ing
(Io
T)
(
S
eu
ng
Eu
n
Le
e)
69
9
4.
E
X
PERI
MEN
T
AL RES
U
L
T
In
o
r
de
r t
o
pr
o
g
ram
t
h
e bi
nar
y
code
f
o
r C
o
r
t
ex-M
0
D
S
c
o
r
e
, a
pre
-
c
o
m
p
il
ed bi
nary
fi
l
e
i
s
req
u
i
r
e
d
t
h
at
i
n
cl
u
d
es t
h
e
uC
/
O
S
-
I
I
k
e
rnel
a
n
d t
h
e
a
ppl
i
cat
i
o
ns.
Fi
gu
re
5 s
h
ows
ou
r e
x
peri
m
e
nt
al
envi
ro
nm
ent
w
h
i
c
h
con
s
i
s
t
s
o
f
t
h
e
FP
GA
w
h
i
c
h
con
f
i
g
ure
d
I
o
T
pl
at
f
o
rm
, t
h
e
B
l
uet
oot
h m
o
d
u
l
e
, t
h
e
sen
s
o
r
m
odul
e, a
n
d
VG
A
connector. On the
test
application,
the IoT pl
atform
collects
the te
m
p
erat
ur
e and h
u
m
i
di
t
y
dat
a
from
ext
e
rnal
sen
s
o
r
s v
i
a t
h
e USART2
. Then
, t
h
e co
llected
d
a
ta is
p
a
ck
etized
an
d tran
sm
it
ted
th
ro
ug
h th
e
USAR
T1
and
wireless co
mmu
n
i
cation
m
o
du
le.
Op
tion
a
lly, th
e
VGA cont
ro
ller can
d
i
splay th
e im
ag
e o
n
a
VGA m
o
n
ito
r.
Howev
e
r, it tak
e
s abou
t 1
seco
nd
to
d
i
sp
lay an
i
m
ag
e b
e
cau
se th
e co
re
is to
o
slow.
If
th
is p
l
atform
d
o
e
s no
t
have
an
o
p
erat
i
ng sy
st
em
, di
spl
a
y
i
ng t
i
m
e of i
m
age
m
i
ght
be an obstacle
to real tim
e ap
plication.
However
data tra
n
sm
ission is sta
b
le be
cause t
h
e uC/OS-II kernel handles
each
ta
sk
i
n
real tim
e
.
T
h
ere
f
ore, this is an
app
r
op
riate pla
t
form
fo
r
real ti
m
e
ap
p
licatio
n
su
ch
as
d
a
ta
co
llectio
n
m
o
du
le of
IoT syst
e
m
.
Fi
gu
re 5.
P
hot
og
ra
ph
o
f
ou
r val
i
d
at
i
o
n
e
nvi
ro
nm
ent
5.
CO
NCL
USI
O
N
In
t
h
i
s
pape
r, we prese
n
t
ou
r
Io
T pl
at
fo
rm
whi
c
h
c
onsi
s
t
s
of
t
h
e
C
o
rt
e
x
-M
0 DS co
re, sy
st
em
bus
,
an
d
prin
cip
a
l
p
e
ri
p
h
e
rals
fo
cu
sing
o
n
lo
w
p
o
wer cap
a
b
ility an
d th
e exp
a
n
d
a
b
ility. Th
e USART
com
m
uni
cat
i
on m
odul
e c
o
l
l
ect
s a dat
a
an
d t
r
a
n
sm
i
t
s
dat
a
t
o
t
h
e
wi
rel
e
ss com
m
uni
cat
i
on m
odul
e
suc
h
as
B
l
uet
oot
h o
r
W
i
-Fi
.
T
h
i
s
sy
st
em
can be con
n
ect
ed t
o
I
o
T net
w
or
k, a
n
d use
d
as a f
u
ndam
e
nt
al
sy
stem
for
sens
or
no
de.
T
h
e i
m
pl
em
ent
e
d sy
st
em
cont
ai
ns t
h
e nec
e
ssa
ry
har
d
ware t
o
m
i
nim
i
ze l
eakage cu
rre
nt
, a
n
d t
h
e
FPGA sy
n
t
h
e
sizab
le AHB-Lite syste
m
b
u
s
en
ab
les
ad
d
ition
a
l h
a
rd
ware im
p
l
emen
tatio
n
to p
r
ov
id
e
expa
ndability. The uC/OS-II real
-ti
m
e kernel controls peri
pherals accordin
g to pri
o
rity. In the fut
u
re
, we plan
t
o
i
n
t
e
g
r
at
e m
o
re sy
nt
hesi
zabl
e
pe
ri
p
h
eral
s t
o
c
ont
rol
di
ve
r
s
e sens
o
r
net
w
or
ks.
ACKNOWLE
DGE
M
ENTS
Th
is stud
y w
a
s sup
por
ted
by th
e Resear
ch
Pr
og
r
a
m
f
und
ed
b
y
th
e
Seo
u
l
N
a
tio
nal U
n
i
v
er
sity of
Science a
n
d Te
chnology.
REFERE
NC
ES
[1]
X.
S.
Li
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t
.a
l.
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p
ac
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cto
r
P
W
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e-P
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S
SN
:
2
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08
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J
ECE Vo
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,
N
o
. 4
,
Au
gu
st 2
015
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69
5
–
70
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0
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e
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.
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c
om/education/univ/ma
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de1-board.h
tml
BIOGRAP
HI
ES OF
AUTH
ORS
Sang Do
n Kim
is M.S. student in the Depar
t
ment of
Electron
ic Engineeri
ng at
Seoul National
University
o
f
Scien
ce and Technolog
y
,
Seoul,
Korea. He has a B.S. degree in Electronic
Engineering fro
m Seoul National
University
of
Science
and T
echnolog
y
,
Seo
u
l, Korea. His
res
earch
in
teres
t
includ
es
com
put
er ar
chi
t
ec
ture
,
l
o
w power c
i
rcui
t
des
i
gn
and s
i
gn
al pro
ces
s
i
ng.
Se
ung Eu
n Le
e
is
an As
s
i
s
t
ant P
r
ofes
s
o
r in the Dept
. of El
ectron
i
c Eng
i
ne
ering at S
e
ou
l
National Univer
sity
of Scien
c
e and Technolog
y
.
He has a P
h
.D. degr
ee in
Electrical
and
Com
puter Engin
eering
from
the
Univers
i
t
y
of C
a
liforn
i
a,
Irvin
e.
His
curren
t
res
earch
int
e
res
t
s
includ
e com
pute
r
archi
t
ec
ture
,
m
u
lti-processor
s
y
stem
-on-chip
, low-power
and resili
ent
VLSI,
and hardware acceler
a
tion for emerging applicati
ons. Prior to joining Seoul Tech in 2010, he
s
p
ent 2
years
a
s
a platform
ar
chit
ect
at Int
e
l
Labs
, Hil
l
os
boro, OR, US
A and 6
years
as
a
res
earch
er at
Korea El
ectron
i
cs
Techno
log
y
Ins
t
i
t
ute
,
Kore
a.
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