Inter national J our nal of Electrical and Computer Engineering (IJECE) V ol. 7, No. 4, August 2017, pp. 2278 – 2286 ISSN: 2088-8708 2278       I ns t it u t e  o f  A d v a nce d  Eng ine e r i ng  a nd  S cie nce   w     w     w     .    i     a    e    s    j    o    u    r    n    a    l     .    c     o    m     A 300 GHz CMOS T ransmitter Fr ont-End f or Ultrahigh-Speed W ir eless Communications T uan Anh V u 1,2 and Minoru Fujishima 1 1 Graduate School of Adv anced Sciences of Matter , Hiroshima Uni v ersity , Japan 2 VNU Uni v ersity of Engineering and T echnology , Japan Article Inf o Article history: Recei v ed: Feb 25, 2017 Re vised: Jun 3, 2017 Accepted: Jun 19, 2017 K eyw ord: T ransmitter Doubler Po wer Amplifier 300 GHz Millimeter -W a v e ABSTRA CT This paper presents a 300 GHz transmitter front-end suitable for ultrahigh-speed wireless communications. The transmitter front-end realized in TSMC 40 nm CMOS consists of a common-source (CS) based doubler dri v en by a tw o-w ay D-band po wer amplifier (P A). Simulation results sho w that the tw o-w ay D-band P A obtai ns a peak g ain of 21.6 dB o v er a -3 dB bandwidth from 132 GHz to 159 GHz. It e xhibits a saturated po wer of 7.2 dBm and a po wer added ef ficienc y (P AE) of 2.3%, all at 150 GHz. The CS based doubler results in an output po wer of 0.5 mW at 300 GHz. The transmitter front-end consumes a DC po wer of 205.8 mW from a 0.9 V supply v oltage while it occupies an area of 2.1 mm 2 . Copyright c 2017 Institute of Advanced Engineering and Science . All rights r eserved. Corresponding A uthor: Name: T uan Anh V u Af filiation: Graduate School of Adv anced Sciences of Matter , Hiroshima Uni v ersity Address: 1-3-1 Kag amiyama Hig ashi-hiroshima, Hiroshima 7398530, Japan Phone: +81-82-424-7641 Email: anhvu@hiroshima-u.ac.jp 1. INTR ODUCTION According to the current trend, frequenc y used for wireless communication will reach terahertz band in 2020. Unallocated frequenc y re gion be yond 275 GHz with v ast bandwidth can be potentially utilized for ultrahigh-speed wireless communication. In particular , 300 GHz band is attracti v e since propag ation decay in air around 300 GHz is relati v ely lo w . Ho we v er , since studies on terahertz wireless communication including 300 GHz band are still in early stage when only a fe w transcei v ers operating abo v e 275 GHz were reported [1] [2] [3]. Since the maximum operating frequenc y or unity-po wer -g ain frequenc y , f max , of the n-type MOSFET e v en with adv anced CMOS process is belo w 300 GHz, realization of 300 GHz RF front-end is challenging. One solution is to use frequenc y multipliers. A 300 GHz CMOS RF front-end w as reported using a tripler [4]. Ho we v er , the tripler generates not only the desired RF signal b ut also the higher -order spurious. As a res ult, the RF signal may be distorted by a higher -order spurious. On the other hand, since quadratic nonlinearity of a MOSFET is stronger than its cubic counterpart, a doubler can generate higher output po wer than a tripler does. In this paper , we are going to present the designs and simulations of a 300 GHz transmitter f ront-end as illustrated in Fig. 1. It includes the CS based doublers (DBLs) dri v en by the tw o-w ay D-band P A. When the doubler is emplo yed, the 300 GHz output signal can be generated from the 150 GHz input one. The paper is or g anized as follo ws. Section 2 introduces the architectures of the proposed 300 GHz transmitter front-end including detailed descriptions of circuit topologies. The simulation results are presented in section 3 and conclusions are gi v en in the last section. 2. DESIGN OF 300 GHz TRANSMITTER FR ONT -END 2.1. T ransmission Lines and Rat-Race Balun The 300 GHz transmitter front-end is designed using TSMC 40 nm 1P10M CMOS GP process. Its back end consists of 10 copper layers and a top aluminum redi strib ution layer (RDL). The cross-vie w of grounded copla- nar w a v e-guide transmission lines (GCPW -TLs) are depicted in Fig. 2 [5]. The GCPW -TL with the characteristic J ournal Homepage: http://iaesjournal.com/online/inde x.php/IJECE       I ns t it u t e  o f  A d v a nce d  Eng ine e r i ng  a nd  S cie nce   w     w     w     .    i     a    e    s    j    o    u    r    n    a    l     .    c     o    m     ,  DOI:  10.11591/ijece.v7i4.pp2278-2286 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 2279 Figure 1. The proposed 300 GHz transmitter front-end. impedance of 50 (the 50 GCPW -TL) is used for shunt stubs and connecting to the output pad of the 300 GHz doubler . Its signal line consists of the RDL layer with a width of 9 µm. Ground (GND) w alls composed of the 6th to 10th metal layers with a width of 2.7 µm are placed on the both side of the signal line at the distance of 7.2 µm. The GCPW -TL with the characteristic impedance of 71 (the 71 GCPW -TL) is used for the shunt stubs of the P A ’ s matching netw orks, doubler’ s matching netw orks and the series stubs of rat-race baluns. The width of the top-layer signal line is 2.9 µm, and the GND w all placed at a distance of 7.6 µm from the signal line has the width of 1.8 µm. The 3nd to 5th metal layers are meshed and stitched together with vias to form the GND plane. Electromagnetic (EM) sim- Figure 2. The cross-vie w of the GCPW -TLs. ulation by ANSYS HFSS sho ws that the attenuation constant, , of the 50 and 71 GCPW -TLs is 1.0–1.4 dB/mm and 1.2–1.6 dB/mm at 100–150 GHz, respecti v ely . The shunt stubs of the inter -stage netw orks are arranged adjacent across a common GND w all, and t h e space between the GCPW -TLs is 17 µm. The near -end and f ar -end crosstalk simulated by EM simulation are belo w -30 dB and -34 dB at 100 GHz and 250 GHz, respecti v ely . It indicates that the cross-coupling between stubs is ne gligible. As illustrated in Fig. 3, the double rat-race balun composed of the 71 GCPW -TLs is designed for generating the dif ferential signal from the single-ended one. The length of the GCPW -TL unit of the double rat-race balun is 300 µm which is equi v alent to /4 at 150 GHz ( is the w a v e l ength). The compact design is realized by folding t he GCPW -TLs and sharing the GND w all. A 300 GHz CMOS T r ansmitter F r ont-End ...(T uan Anh V u) Evaluation Warning : The document was created with Spire.PDF for Python.
2280 ISSN: 2088-8708 Figure 3. The 150 GHz double rat-race balun. 2.2. T w o-W ay D-Band P o wer Amplifier The circuit schematic of the proposed D-band P A is sho wn in Fi g. 4. It includes an input matching netw ork, an output matching netw ork, three fully dif ferential amplifying stages and inter -stage matching netw orks. F or bandwidth enhancement, multi-stage matchings using capacitors and inducti v e GCPW -TLs are adopted. The series capacitors and shunt GCPW -TLs form 4th-order high-pass filters at the input ports. The outputs of the P A are directly matched to the inputs of the doubler . The inter -stage matching netw orks are based on PI netw orks for wideband performa n c e. All of the capacitors also act as coupling capacitors while the DC bias v oltages are applied across the GCPW -TLs. The bias v oltages are common to all amplifying stages. The shunt stubs composed of 71 GCPW -TLs are arranged re gularly with shari n g GND w alls. The connection between the MOSFETs, M OM capacitors and GCPW -TLs are made by the 8th to 10th metal layers. The lengths of the GCPW -TLs and the MOM capacitor v alues are determined by a nonmetric optimization process taking into account the models of MOSFETs, MOM capacitors and GCPW -TLs. The f ar end of each shunt stub is terminated by a wideband decoupling po wer line with v ery lo w characteristic impedance (the 0 TL). Figure 4. The proposed D-band P A. The internal ne g ati v e feedback path caused by the parasitic g ate-drain capacitor , C GD limits the po wer g ain and re v erse i solation, and potentially causes inst ability . In order to impro v e the stability without compromising the IJECE V ol. 7, No. 4, August 2017: 2278 – 2286 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 2281 g ain of the MOSFET , the internal feedback in the transistor has to be reduced. An el e g ant technique to accomplish this is to neutralize C GD in a dif ferential pair by using cross coupling capacitors [6]. Fig. 5a sho ws the core of the amplifier that is a fully dif ferential pair with capaciti v e neutralization. The cross coupling capacitor , whose v alue is 16.1 fF, is determined to obtain high g ain. Fig. 5b re v eals the parasi tics associated at each node of the amplifier core. The parasitic components are e xtracted using bond-based design which is a measurement-based design approach to a v oiding the dif ficulty associated with layout parasitics when ordinary layout parasiti c e xtraction (LPE) tools used for chip design do not e xtract inductances. Figure 5. Amplifier core (a) and its equi v alent circuit with e xtracted parasitics (b). The tw o-w ay P A is formed by connecting tw o D-band P As in parallel as depicted in Fig. 1. The dri v er amplifier (D A) at the input is emplo yed as the pre-amplifier before the input po wer is di vided by the double rat-race balun. The D A has a similar topology as the D-band P A does. It consists of four fully dif ferential amplifying stages with cross-coupling capacitors. Man y-stage amplifiers for terahertz frequencies tend to occup y a lar ge area since inter - stage matchi ng netw orks consist typically of se v eral passi v e de vices that are much lar ge than MOSFETs. T o realize cost-ef fecti v e chips, ar ea reduction is important. In order to reduce the area of the amplifier , we proposed the ”fishbone layout” [7]. In this technique, GCPW -TL stubs used in matching netw orks are arranged re gularly at narro w spacings, and the GCPW -TLs themselv es are designed to be narro w , thereby reducing the footprint. 2.3. 300 GHz CS Based Doubler As the name suggest, the 300 GHz CS based doubler e xploits the quadratic nonlinearity of the MOSFET . It upcon v erts the signal at the output of the D-band P A into RF signal at 300 GHz frequenc y band. The main reason using acti v e frequenc y doubler is that it can achie v e con v ersion g ain o v er broad bandwidth while getting also good DC to RF ef ficienc y . The complete circuit of the proposed doubler with all component v alues are gi v en in Fig. 6. The same as po wer a mplifiers, the acti v e frequenc y multipliers w ork in dif ferent classes. In this de sign, the doubler is biased to operate in an equi v alent class-AB po wer amplifier where it is v ery stable and ha v e good g ain, ef ficienc y and output po wer . The doubler generates harmonics by rectifying the sinusoidal input signals when is biased near its pinch-of f, and the input sinusoids t u r n the MOSFETs on o v er part of their c ycles. Due to the balanced topology , the e v en harmonics are generated in phase thus being summed up while the odd harmonics are generated out of phase thus being suppressed. The outputs are tuned to the second harmonic while other harmonics including the fundamental frequenc y are further suppressed by the output P I matching netw orks. The second harmonic signals leak ed through A 300 GHz CMOS T r ansmitter F r ont-End ...(T uan Anh V u) Evaluation Warning : The document was created with Spire.PDF for Python.
2282 ISSN: 2088-8708 the MOSFETs to the input ports are shorted by using /2 short stubs. The inputs of the doubler are conjug ate-matched to the optimal loads of the preceding D-band P A. Figure 6. The proposed 300 GHz CS based doubler . 3. SIMULA TION RESUL TS Simulation results of the 300 GHz transmitter front-end for TSMC 40 nm CMOS technology are achie v ed using the Cadence’ s V irtuoso Analog Design En vironment. Circuit design at v ery high frequencies in v olv es more detailed considerations than at lo wer frequencies when the ef fect of parasitic capacitances and inductances can impose serious constrains on achie v able performance. Thus, all components used for simulation are RF models pro vided by TSMC. 3.1. T w o-W ay D-Band P o wer Amplifier Fig. 7 sho ws the simulated S-parameters of the tw o-w ay D-band P A. S 11 remains belo w -7 dB while S 22 is less than -10 dB o v er the -3 dB bandwidth from 132 GHz to 159 GHz. Both input and output return loss indicate wideband performance. The D-band P A achie v es a peak g ain of 21.6 dB o v er the band of interest. The re v erse isolation is lo wer than -140 dB (not sho wn in the figure). A high re v erse isolation guarantees high stability for the P A. Fig. 8 and Fig. 9 plot the output po wer and P AE v ersus input po wer , respecti v ely . At 150 GHz, the designed P A obtains a saturated po wer of 7.2 dBm and a peak P AE of 2.3% at –6 dBm input po wer . The output referred 1 dB compression point (OP1dB) is 4 dBm. The tw o-w ay P A consumes a po wer of 199.4 mW from a 0.9 V supply v oltage. 3.2. 300 GHz T ransmitter Fr ont-End Fig. 10 sho ws the simulated S-parameter s of the 300 GHz transmitter front-end. As can be seen in this figure, both input and output return loss indicate good matchings. Fig. 11 and Fig. 12 sho w the output po wer of the transmitter v ersus input po wer and output frequenc y , respecti v ely . At 150 GHz input frequenc y , the transmitter e xhibits a saturated po wer of -2.2 dBm. It obtains an output po wer of -2.8 dBm which is equi v alent to 0.5 mW at 300 GHz and co v ers a -3 dB bandwidth from 274 GHz to 323 GHz. The harmonic po wer le v els are plotted in Fig. 13 where the odd harmonic le v els are v ery lo w due to the balanced structure of the CS bas ed doubler . Fig. 14 sho ws the layout of the 300 GHz transmitter front-end. It occupies an area of 2.1 mm 2 including probe pads. The transmi tter consumes a po wer of 205.8 mW from a 0.9 V supply v oltage. T able 1 summarizes the performance of the proposed design and compares it to other published transmitters operating in a similar frequenc y range. IJECE V ol. 7, No. 4, August 2017: 2278 – 2286 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 2283 Figure 7. The simulated S-parameter of the tw o-w ay D-band P A. Figure 8. The simulated output po wer v ersus input po wer of the tw o-w ay D-band P A. Figure 9. The simulated P AE v ersus input po wer of the tw o-w ay D-band P A. A 300 GHz CMOS T r ansmitter F r ont-End ...(T uan Anh V u) Evaluation Warning : The document was created with Spire.PDF for Python.
2284 ISSN: 2088-8708 Figure 10. The simulated S-parameter of the 300 GHz transmitter front-end. Figure 11. The simulated output po wer v ersus input po wer of the 300 GHz transmitter front-end. Figure 12. The simulated output po wer v ersus output frequenc y of the 300 GHz transmitter front-end. IJECE V ol. 7, No. 4, August 2017: 2278 – 2286 Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE ISSN: 2088-8708 2285 Figure 13. The simulated harmonics of the 300 GHz transmitter front-end. Figure 14. The layout of the 300 GHz transmitter front-end. T able 1. Comparison with the pre vious published transmitters Ref. T echnology Po wer cons. RF frequenc y Output po wer ( W ) ( GHz ) (dBm) [1] 0.25 µm InP – 300 – [2] 50 nm InP – 340 -17.5 [3] 40 nm CMOS 1.4 275–305 -14.5 [4] 65 nm CMOS 0.22 240 0 This w ork 40 nm CMOS 0.2* 274–323* -2.8* *Sim. results A 300 GHz CMOS T r ansmitter F r ont-End ...(T uan Anh V u) Evaluation Warning : The document was created with Spire.PDF for Python.
2286 ISSN: 2088-8708 4. CONCLUSIONS In this paper , we ha v e presented the designs and simulations of the 300 GHz transmitter front-end tar geted for ultrahigh-speed wireless communications. The tw o-w ay D-band P A obtai n s the peak g ain of 21.6 dB, the saturated po wer of 7.2 dBm and the P AE of 2.3%. The CS based doubler results in the peak output po wer of 0.5 mW at 300 GHz while co v ering the -3 dB bandwidth from 274 GHz to 323 GHz. Supplied by the 0.9 V supply v oltage, the transmitter front-end consumes the DC po wer of 205.8 mW while it occupies the area of 2.1 mm 2 . A CKNO WLEDGEMENT This w ork w as supported by the R&D on W ireless T ranscei v er Systems with CMOS T echnology in 300-GHz Band, as part of an R&D program on K e y T echnology in T erahertz Frequenc y Bands of the Ministry of Internal Af f airs and Communications, Japan. REFERENCES [1] H.-J. Song, J.-Y . Kim, K. Ajito, N. K ukutsu, and M. Y aita, 50-gb/s Direct Con v ersion QPSK Modulator and Demodulator MMICS for T erahertz Communications at 300 GHz, IEEE T ransactions on Micro w a v e Theory and T echniques , v ol. 62, no. 3, pp. 600-609, March 2014. [2] C. W ang, B. Lu, C. Lin, Q. Chen, L. Miao, X. Deng, and J. Zhang, 0.34-THz W ireless Link Based on High-Order Modulation for Future W ireless Loca l Area Netw ork Applications, IEEE T ransactions on T erahertz Science and T echnology , v ol. 4, no. 1, pp. 75-85, January 2014. [3] K. Katayama, K. T akano, S. Amaka w a, S. Hara, A. Kasamatsu, K. Mizuno, K. T akahashi, T . Y oshida, and M. Fujishima, A 300GHz 40nm CM OS T ransmitter with 32-QAM 17.5Gb/s/ch Capability o v er 6 Channels, 2016 IEEE International Solid-State Circuits Conference (ISSCC 2016) , pp. 342-343, February 2016. [4] S. Kang, S. V . Th yag arajan, and A. M. Niknejad, A 240GHz W ideband QPSK T ransmitter in 65nm CMOS, 2014 IEEE Radio Frequenc y Inte grated Circuits Symposium (RFIC 2014) , pp. 353-356, June 2014. [5] S. Hara, K. Katayama, K. T akano, I. W atanabe, N. Sekine, A. Kasamatsu, T . Y oshida, S. Amaka w a, and M. Fujishima, Compact 160-GHz Amplifier with 15-Db Peak Gain and 41-GHz 3-db Bandwidth, 2015 IEEE Radio Frequenc y Inte grated Circuits Symposium (RFIC 2015) , pp. 1-4, May 2015. [6] N. Deferm and P . Re ynaer , ”CMOS Front Ends for Millimeter W a v e W i reless Communication Systems, ” Springer International Publishing , 2015. [7] S. Hara, I. W atanabe, N. Sekine, A. Kasamatsu, K. Katayama, K. T akano, T . Y oshida, S. Amaka w a, and M. Fujishima, Compact 138-GHz Amplifier with 18-Db Peak Gain and 27-GHz 3-dB Bandwidth, 2015 IEEE Inter - national Symposium on Radio-Frequenc y Inte gration T echnology (RFIT 2015) , pp. 55-57, August 2015. BIOGRAPHIES OF A UTHORS T uan Anh V u recei v ed the B.S de gree and M.Sc de gree in Electronics and T elecommunications T echnology from Uni v ersity of Engineering and T echnology , V ietnam National Uni v ersity in 2006 and 2009, respecti v ely . In 2013, he recei v ed Ph.D de gree in the field of analog/mix ed-signal RF nanoelectronics from Uni v ersity of Oslo, Norw ay . Since 2014, he has been a lecturer at F aculty of Electronics and T elecommunications, VNU Uni v ersity of Engineering and T echnology . Dr . T uan Anh V u w as doing postdoc at Department of Semiconductor Electronics and Inte gration Science, Hiroshima Uni v ersity , Japan. His research interests are analog RF inte grated c ircuit designs includ- ing po wer amplifiers, lo w noise amplifiers, mix ers, frequenc y multipliers, etc. Minoru Fujishima recei v ed his B.E., M.E. and Ph.D. de grees in Electronics Engineering from the Uni v ersity of T ok yo, Japan, in 1988, 1990 and 1993, respecti v ely . He joined the f aculty of the Uni v ersity of T ok yo in 1988 as a research associate and w as a n associate professor of the School of Frontier Sciences, Uni v ersity of T ok yo. He w as a visiting professor at the ESA T -MICAS Lab- oratory , Katholiek e Uni v ersiteit Leuv en, Belgium, from 1998 to 2000. Since 2009, he has been a professor of the Graduate School of Adv anced Sciences of Matter , Hiroshima Uni v ersity . He is currently serving as a technical committee member of se v eral international conferences. His current research interests are in the design of lo w-po wer ultrahigh-speed millimeter - and short-millimeter - w a v e wireless CMOS circuits. He is a member of IEEE and JSAP . IJECE V ol. 7, No. 4, August 2017: 2278 – 2286 Evaluation Warning : The document was created with Spire.PDF for Python.