Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
6, N
o
. 1
,
Febr
u
a
r
y
201
6,
pp
. 90
~98
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
1.8
693
90
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
High Sp
eed P
o
wer Effi
ci
ent CM
OS Inverter Bas
e
d Current
Comparator in UMC 90 nm Technology
V
eepsa
Bha
t
i
a
*
,
N
e
et
a Pandey
**
, A
s
o
k
Bha
t
t
a
cha
r
yy
a**
*Indira
Gandh
i Delhi Techn
i
cal Univ
ersity
for
Women, Delhi, I
ndia
**Delhi
Tech
nological University
, Delh
i, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
J
u
l 31, 2015
R
e
vi
sed Oct
4,
2
0
1
5
Accepted Oct 20, 2015
A novel power-speed efficient current comp
arator is proposed i
n
this paper
.
It comprises of only
CMOS inv
e
rters in
its stru
cture
,
em
plo
y
in
g a sim
p
le
biasing method. The structur
e offers simp
licity
of
design. It posesses the ver
y
desirable featur
es of high speed a
nd low power dissipation
,
making this
structure
a highly
desir
a
ble one
for va
rious curr
ent mode applications.
The
simulations have been performed us
ing UMC 90
nm CMOS tech
nolog
y
and
the results demonstrate the propagation de
lay
of about 3.1 ns and t
h
e averag
e
power consumption of 24.3 µW for 300 nA
input current
at supply voltag
e
of
1V.
Keyword:
CMOS Inv
e
rter
Current C
o
m
p
arator
Po
wer di
ssi
pat
i
o
n
Pro
p
a
g
at
i
o
n de
l
a
y
Tran
sco
n
duct
a
nce
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Veepsa Bhatia,
Depa
rt
m
e
nt
of
El
ect
roni
cs
an
d C
o
m
m
uni
cati
on
En
gi
nee
r
i
n
g,
In
di
ra
Ga
nd
hi
Del
h
t
i
Tec
hni
c
a
l
Uni
v
ersi
t
y
f
o
r
Wom
e
n,
Kashm
e
re Gat
e
, Del
h
i,
In
dia.
Em
a
il: v
eep
sa@g
m
a
il.co
m
1.
INTRODUCTION
Current m
ode signal proce
ssing in
CMOS technology has
received
gr
ea
t interest in the past fe
w
decade
s
[1]-[9]. Of num
e
rous c
u
rre
n
t mode
building
bloc
ks t
h
at e
x
is
t, a c
u
rre
n
t com
p
arator
is one
fu
n
d
am
ent
a
l
bl
ock t
h
at
fi
nd
s usa
g
e i
n
va
ri
o
u
s a
ppl
i
cat
i
ons
s
u
ch
as t
e
m
p
erat
ur
e se
nso
r
s,
ph
ot
o
-
s
e
ns
ors
,
cu
rren
t Sch
m
i
tt Trig
g
e
rs, cu
rren
t
-
m
o
d
e
An
al
o
g
to
Di
g
ital co
nv
erters, o
s
cillato
rs,
cu
rren
t to
freq
u
e
n
c
y
con
v
e
r
t
e
rs,
ne
u
r
al
net
w
o
r
k
s
,
f
unct
i
o
n
ge
nera
t
o
rs et
c.
[
1
0]
-[
20]
For an e
fficie
n
t current c
o
m
p
arator
, th
e m
o
st i
m
p
o
r
tan
t
requ
irem
en
t is a fast ti
m
e
resp
onse fo
ll
o
w
ed
by its accurac
y
. Num
e
rous a
r
chitectures of curre
nt com
p
arators ha
ve been put fort
h i
n
the literature
but the
ear
liest k
n
o
w
n tr
u
e
CMO
S
cu
rr
en
t co
m
p
ar
ato
r
w
a
s pr
oposed
b
y
Fr
ietas an
d
C
u
rr
en
t in [
2
0
]
. Th
is stru
ctur
e
was
based
o
n
t
h
e u
s
e o
f
a si
m
p
le current
m
i
rror
fo
r c
u
r
r
e
nt com
p
ariso
n
p
u
r
p
o
se.
H
o
weve
r, it wa
s lim
i
ted by
its sp
eed of
o
p
eratio
n. To
imp
r
ov
e
u
pon
th
i
s
li
m
ita
tio
n
,
the curren
t
co
m
p
arat
o
r
s u
s
i
n
g
a no
n
lin
ear
positiv
e
feed
bac
k
we
re
pr
o
p
o
s
ed i
n
[
22]
-
[
23]
.
In
[
2
2]
t
h
e
first true lo
w i
n
pu
t i
m
p
e
dance current com
p
arator wa
s
p
r
op
o
s
ed
. Th
is circu
it u
s
ed
a sou
r
ce
fo
llo
wer inp
u
t
stag
e
to
ob
tain
low
in
pu
t resistan
ceb
u
t
it su
ffers
fro
m
lo
ng
er
resp
on
se ti
m
e
fo
r low
in
pu
t curren
t
s,
wh
ich
lim
i
t
s
i
t
s pe
rf
orm
a
nce.
[2
3]
P
r
o
p
o
sed
t
w
o C
M
OS c
u
r
r
en
t
co
m
p
arato
r
stru
ctures to
ob
tain
b
e
tter reso
lu
tion
and
offset th
an
th
at
attain
ed
with [22].
One
of these
stru
ctures u
tilizes cu
rren
t switch
i
n
g
as in
[2
2
]
to
ob
tain
a lin
ear tran
sien
t ev
o
l
u
tion
do
m
i
n
a
ted
b
y
a Miller
capacitance. Second structure,
the current steering c
o
m
p
arator a
n
alte
rnate principle to reduce Miller effec
t
ex
h
i
b
its b
e
tter tran
sien
t respon
se alon
g
with h
i
g
h
-reso
l
u
tion
.
Bu
t th
e po
si
tiv
e feedb
ack
ap
p
lied
at th
e
in
pu
t
led
to a lower sen
s
itiv
ity wh
ich
,
i
n
t
u
rn
, l
o
wered
the sp
eed
fo
r l
o
w
inp
u
t
lev
e
ls. Variou
s st
ru
ct
u
r
es
su
bsequ
e
n
tly w
e
r
e
pr
opo
sed in
[24
]
-
[
30
] to ov
er
co
m
e
th
e li
m
i
tatio
n
s
posed
b
y
th
e
p
r
ev
iou
s
stru
ctur
es, each
havi
ng i
t
s
o
w
n
respect
i
v
e m
e
ri
t
s
and
dem
e
ri
t
s
. In [
2
4]
, t
h
e st
ruct
u
r
e o
f
[2
2]
has
been
m
odi
fi
ed t
o
i
n
cl
ude
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 6
,
N
o
. 1
,
Febru
a
ry
2
016
: 9
0
–
98
91
class AB
o
p
er
at
i
on i
n
or
der
t
o
red
u
ce t
h
e
vol
t
a
ge
swi
n
g, t
h
us
resul
t
i
ng i
n
g
r
eat
er
spee
d at
sm
al
l i
n
p
u
t
currents
. T
h
e s
t
ructure
propos
ed i
n
[
25]
i
s
a
m
odi
fi
cat
i
o
n
of
[
22]
t
o
o
b
t
a
i
n
a fast
resp
ons
e t
i
m
e
al
on
g wi
t
h
l
o
w i
n
put
i
m
pedance
by
ap
pe
ndi
ng t
w
o i
n
ve
rt
ers t
o
t
h
e st
r
u
ct
ure o
f
[
22]
. F
u
rt
her, i
n
[2
6]
t
h
e st
ruct
u
r
e o
f
[2
2]
has
bee
n
m
odi
fi
ed
fo
r
re
duci
n
g
del
a
y
t
i
m
es. It
em
pl
oy
s
di
ode
-c
on
nect
ed
NM
O
S
a
n
d P
M
OS t
r
a
n
si
st
o
r
s t
h
a
t
rest
ri
ct
t
h
e i
n
p
u
t
t
r
a
n
si
st
or
s f
r
o
m
ent
e
ri
ng
de
ep s
ubt
hres
h
o
l
d
re
gi
on
o
f
ope
rat
i
o
n
.
Si
nce t
h
i
s
st
ruct
ure
re
q
u
i
r
es
t
w
o wi
de wi
dt
h di
o
d
e
-
co
n
n
e
c
t
e
d t
r
ansi
st
o
r
s
st
acked t
o
ge
ther, h
e
n
ce it lea
d
s to
th
e co
m
p
licatio
n
in
th
e circu
i
t
to
po
log
y
.
M
a
ny
st
ruct
ure
em
pl
oy
feed
b
ack
m
echanism in order t
o
reduce i
n
put
re
sistance, the
r
e
b
y increa
sing
t
h
e spee
d. S
u
c
h
st
ruct
ure
s
ha
ve bee
n
re
po
rt
ed i
n
[
27]
-
[
30]
. [2
7]
Em
pl
oys a resi
st
i
v
e fe
edbac
k
net
w
or
k i
n
a
current
-
source inve
rting
am
p
l
ifier at inpu
t st
ag
e
o
f
[22
]
in
o
r
d
e
r to red
u
ce th
e i
n
pu
t
resistan
ce. Th
is lead
s t
o
a
high s
p
eed curre
nt com
p
arat
or t
h
at offe
rs
low i
n
pu
t
re
sistance for increased
i
n
put
cur
r
ent
si
nki
n
g
a
n
d
so
urcing
cap
a
b
ilities. [28
]
Propo
ses a con
tin
uo
us-tim
e
cu
rren
t
co
m
p
arat
o
r
t
o
ach
i
ev
e
sh
ort respon
se d
e
lay
t
i
m
e
, l
o
w po
wer c
o
n
s
um
pt
i
on, sm
al
l
area and
pr
ocess
ro
bust
n
ess.
It
em
pl
oy
s a C
M
OS com
p
l
e
m
e
nt
ary
a
m
p
lifier two
resistiv
e-lo
ad
am
p
l
ifiers and
t
w
o CMOS i
nverters. A transistor
work
ing
i
n
lin
ear reg
i
on serv
es
as the negative
feedback resis
t
or of
th
e CMOS co
m
p
le
m
e
n
t
ary am
p
lifier
.
Th
e stru
ct
u
r
e o
ffers low in
pu
t and
out
put
i
m
pedance,
o
w
i
n
g
t
o
t
h
e resi
st
i
v
e feed
bac
k
. The
s
e
l
o
w
i
n
p
u
t
and
out
put
res
i
st
ances decre
a
se
t
h
e
v
o
ltag
e
swing
s
th
ereb
y redu
cin
g
th
e
resp
on
se ti
m
e
o
f
th
e ci
rcu
it.
[29
]
Em
p
l
o
y
s a feedb
a
ck
system
to
th
e in
pu
t
stage of [22] that allows
high-s
pee
d
operation at low curren
t
s
an
d al
so c
ons
um
es l
e
sser po
wer t
h
an
[2
2]
. T
h
e
cu
rren
t co
m
p
arato
r
in
[30
]
is d
e
v
e
lop
e
d by ap
p
l
yi
ng
positiv
e feedb
a
ck
co
n
c
ep
t arou
nd
an
activ
e b
l
ock
nam
e
ly CC-II
and gi
ves a
hi
gh s
p
ee
d re
sponse.
Furt
her
,
[3
1]
-[
34]
em
pl
oy
va
ri
o
u
s
bi
asi
n
g t
echni
que
s t
o
r
e
duce
i
n
p
u
t
i
m
peda
nce
an
d
h
e
nce ac
hi
ev
e
hi
g
h
er s
p
eed
s of o
p
e
r
at
i
on
w
h
i
l
e
m
a
i
n
t
a
i
n
i
ng l
o
we
r p
o
we
r
con
s
um
pt
i
on.
Speci
fi
cal
l
y
, si
m
p
l
e
bi
asi
ng
m
e
t
hod
i
s
use
d
i
n
[3
1]
and
[
33]
whe
r
e
a
s
[
32]
uses ne
gat
i
v
e
fe
edbac
k
sc
hem
e
at the transi
m
p
edance stage
with a
n
aim
to
ach
iev
e
a
very larg
e loo
p
-g
ain
wh
ile m
a
i
n
tain
ing
th
e tran
sform
e
d
v
o
ltag
e
sign
al g
a
in at th
e lo
west swing
in order t
o
ac
hi
eve s
p
ee
d
The
quest to
devel
o
p m
o
re
efficient st
ruct
ures
th
at m
eet the c
r
iteria
of hi
gh spe
e
d a
n
d acc
uracy
al
on
g
wi
t
h
a
d
di
t
i
onal
feat
u
r
es suc
h
as l
o
w
p
o
we
r
di
ssi
pa
t
i
on i
s
o
n
-
g
oi
n
g
.
A
u
t
h
ors
h
a
v
e
al
so
p
r
o
p
o
se
d t
w
o
su
ch
stru
ctur
es in
[3
4
]-[3
5
]
.
In
[34
]
, a curre
nt com
p
arator
com
p
rising a c
u
rrent
differe
n
ce stage, a
gai
n
stage
wi
t
h
no
n l
i
n
ea
r
feed
bac
k
a
n
d
an
out
put
st
a
g
e
has
bee
n
pr
o
p
o
se
d.
It
use
s
a
cur
r
ent
m
i
rro
r
st
ruct
u
r
e as
a c
u
r
r
ent
diffe
re
nce sta
g
e and a CM
OS inve
rter is
use
d
as t
h
e
outp
u
t
stag
e
for
rail to
rail swing
.
Fu
rt
h
e
r, in
[3
5
]
a low
po
we
r, hi
gh
sp
eed an
d
hi
g
h
r
e
sol
u
t
i
o
n c
u
r
r
e
n
t
com
p
arat
or
has bee
n
pr
o
p
o
se
d as an i
m
pro
v
em
ent
up
on
[2
2]
whe
r
ein the
ga
in stage
has
be
en m
odified leadin
g
to a si
g
n
i
fican
t im
p
r
ov
emen
t in
th
e d
e
l
a
y.
In t
h
i
s
pa
per
,
we ha
ve
pr
o
p
o
s
ed a hi
g
h
spee
d, l
o
w
po
wer c
u
r
r
ent
c
o
m
p
arat
or st
r
u
ct
u
r
e ep
l
o
y
i
ng
on
l
y
CMOS inv
e
rters as t
h
e
b
a
si
c bu
ild
ing
b
l
ock
s
.
A CM
OS in
v
e
rter is a fund
am
en
tal b
l
o
c
k
in th
e
d
i
g
ital
i
n
t
e
grat
e
d
ci
rc
ui
t
desi
gn t
e
c
h
ni
q
u
es.
It
fi
nd
s
wi
de
usa
g
e i
n
im
pl
em
ent
a
t
i
o
n
of
va
ri
o
u
s st
r
u
ct
u
r
es as
re
po
rt
ed i
n
[36]-[40], that are m
a
de exclusivel
y ou
t o
f
CMO
S
in
v
e
r
t
er
s th
us o
f
f
e
r
i
ng
symmetr
y o
f
str
u
ctur
e, endo
w
e
d
with
all
q
u
a
lities of t
h
e CMOS inv
e
rter. Th
e curren
t
co
m
p
arato
r
pro
p
o
s
ed in
t
h
is work has h
i
g
h
l
y
d
e
sirab
l
e
f
e
a
t
u
r
es
o
f
s
p
ee
d
an
d pow
e
r
ef
f
i
ciency with ease
of ope
ration
usi
n
g
UM
C
9
0
nm
C
M
OS t
echn
o
l
o
gy
.
2.
PR
OPOSED
C
URR
EN
T COM
P
AR
A
T
OR
The
pr
o
pose
d
hi
g
h
s
p
ee
d
and
l
o
w
po
w
e
r co
ns
um
pt
i
on c
u
r
r
ent
c
o
m
p
arat
or de
si
gn
base
d
o
n
con
v
e
n
t
i
onal
C
M
OS i
n
vert
e
r
i
s
sh
ow
n i
n
Fi
gu
re 1
.
The architecture
consists of
three stages of
CMOS
inve
rters: a bi
as stage (A
1
),
an input stage
(A
2
)
wh
ich
accep
ts th
e inp
u
t
cu
rren
t
p
u
l
se
an
d
tran
slates
it in
to
co
rresp
ond
ing
v
o
ltag
e
lev
e
l an
d an ou
tpu
t
st
ag
e
(A
3
) to ob
t
a
in
a
fu
ll swing
o
u
t
p
u
t
.
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISS
N
:
2088-8708
High
S
p
e
ed
Power
Efficien
t
CMOS
In
verter Ba
sed
C
u
rren
t
Co
mp
ara
t
o
r
i
n
UMC 90
n
m
…
(Veep
sa
Bhatia
)
92
(a)
(b
)
Fi
gu
re
1.
Pr
o
p
o
se
d C
M
OS
i
n
vert
er
B
a
sed
C
u
r
r
ent
C
o
m
p
arat
or
St
ruct
ure
(
a
) t
r
a
n
si
st
o
r
c
o
nfi
g
u
r
at
i
o
n
,
(b
) e
qui
val
e
nt
sym
bol
re
prese
n
t
a
t
i
o
n
The operational
concept of propose
d
curre
nt
c
o
m
p
arator design
ca
n
be
elucidated
as follows. A
1
com
p
ri
ses of a
sho
r
t
e
d
gat
e
d
r
ai
n C
M
OS i
n
vert
er
(M
1
-M
2
). Th
e prim
ary f
u
n
c
tion
o
f
th
is
stag
e is to
p
r
ov
id
e a
co
nstan
t
v
o
ltage b
i
as
of
ab
ou
t
V
DD
/
2
to
th
e
in
p
u
t
s
t
ag
e
A
2
.
Ar
ou
n
d
t
h
i
s
c
o
m
m
on m
ode v
o
l
t
a
ge
of
V
DD
/2
,
th
e
vol
t
a
ge si
gn
al
swi
n
g at
X ca
n be m
a
i
n
t
a
i
n
ed as sm
al
l as
pos
sible and si
tuated
exactly around the i
n
verter
t
h
res
hol
d vol
t
a
ge of A
2
.
This
ens
u
res
a
very high s
p
eed operation
of the
curre
n
t com
p
arator. T
h
e tra
n
sist
or
l
e
ngt
h
s
a
nd wi
dt
hs rat
i
o
s W
1
/L
1
and
W
2
/L
2
of
A
1
a
r
e set
i
n
o
r
de
r t
o
obt
ai
n t
h
e
req
u
i
r
e
d
bi
as. T
h
i
s
ca
n
be
veri
fi
e
d
by
eq
uat
i
n
g
t
h
e sat
u
rat
i
on
d
r
ai
n c
u
rre
nt
eq
uat
i
o
n
of
PM
OS
an
d
NM
OS
si
nce
b
o
t
h
M
1
and
M
2
b
e
i
ng
d
i
od
e co
nn
ected
MOSFETs
will o
p
e
rate i
n
the satu
ration
reg
i
on
o
f
op
erati
o
n.
22
21
11
n
o
x
g
s
t
n
d
s
p
o
x
sg
t
p
sd
WW
CV
V
V
C
V
V
V
LL
(1
)
2
1
2
2
1
1
no
x
g
s
t
n
d
s
po
x
s
g
t
p
s
d
W
CV
V
V
L
W
CV
V
V
L
(2
)
Fo
r sm
all ch
ann
e
l leng
th
s,
λ
(cha
n
n
el
m
odu
l
a
t
i
on c
o
ef
fi
ci
ent
)
ca
n
not
be i
g
n
o
r
ed
.
Hence
,
by
fi
xi
ng
t
h
e cha
nnel
l
e
ngt
h an
d su
bst
i
t
u
t
i
ng t
h
e t
y
p
i
cal
val
u
es of
t
echn
o
l
o
gy
de
pen
d
e
n
t
param
e
t
e
rs l
i
k
e
λ
, Vt and
k
ʹ
(µC
ox
), t
h
e a
s
pect
rat
i
o
s
of
t
w
o
devi
ces c
a
n be cal
c
u
l
a
t
e
d u
s
i
n
g eq
(1
) an
d (
2
). T
h
e
i
n
p
u
t
st
age
A
2
als
o
servi
n
g as t
h
e t
r
ansim
p
edanc
e
stage c
o
nsists
of M
3
-M
4
.
In th
is
n
o
v
e
l ap
pro
ach, the inpu
t curren
t
Ii
n
which
is
the diffe
re
nce
of signal and refe
re
nce current is in
j
e
cted
in
to
th
e d
r
ain
term
in
al o
f
in
pu
t stag
e. A
cor
r
es
ponding voltage
level
with res
p
ect to the input curr
ent pulse is ge
nerate
d at node X. Essentially; this
vol
t
a
ge l
e
vel
a
ppea
r
i
n
g at
X i
s
a pot
e
n
t
i
a
l
dr
op ac
r
o
ss r
o3
|| r
o4
whe
r
e
r
o3
and
r
o4
are
out
put resistances
of M
3
and M4 res
p
e
c
tively. This i
s
also
a m
eas
ure
of
net tra
n
sim
p
edance i
n
th
e circu
it.
No
te t
h
at an
o
u
t
p
u
t
resistance r
oi
is ap
pr
ox
im
atel
y in
v
e
r
s
ely pro
por
tio
n
a
l to
t
h
e dr
ain
cu
rr
en
t I
di
, i.e. r
oi
= l/ (
λ
I
di
) in
satu
ration
regi
on
of
ope
r
a
t
i
on. T
h
e key
poi
nt
here i
s
t
h
at
t
h
e I
in
sh
o
u
l
d
v
a
ry
t
h
e v
o
l
t
a
ge at
X by
a sm
al
l am
ount
onl
y
whi
c
h
ca
n be
sense
d
by
t
h
e
out
put
st
age.
Thi
s
e
n
s
u
res
t
h
e hi
g
h
s
p
ee
d ope
rat
i
o
n of
t
h
e
com
p
arat
o
r
ci
rcui
t
.
Di
m
e
nsi
ons o
f
M
3
-M
4
are chose
n
taking int
o
consi
d
eration the
i
nve
rse
r
e
l
a
t
i
onshi
p bet
w
een t
h
e
drai
n
cur
r
en
t
and r
oi
to ensure a large sen
s
itiv
ity o
f
V
x
with
resp
ect t
o
I
in
. Thus, eve
n
a
sm
all input
signal will cause
large
v
a
riation
s
in
t
h
e po
ten
tial at n
o
d
e
X. At t
h
e sam
e
t
i
m
e,
th
e ab
sen
ce
o
f
an
y in
pu
t sig
n
a
l will cause th
e
p
o
t
en
tial at X t
o
d
r
o
p
, th
ereby resu
lting
in a lo
w vo
ltag
e
lev
e
l at X.
Non
-
i
d
ealities in
th
e form
o
f
fin
ite
in
pu
t
im
pedance
o
f
out
put
st
age
wi
l
l
affect
t
h
e
pe
r
f
o
r
m
a
nce of
t
h
e ci
rcui
t
.
The v
o
l
t
a
ge ge
nerat
e
d at
nod
e X feeds
the transistors of
output stage (M
5
-M
6
). The tra
n
sistor pai
r
(M
5
-M
6
) se
nse
s
t
h
e di
st
i
n
ct
i
o
ns ap
pl
i
e
d i
n
t
h
e f
o
rm
of gat
e
vol
t
a
ge a
n
d
out
put
s
hi
g
h
o
r
l
o
w
v
o
l
t
a
ge a
s
l
ogi
c
‘1
’
or
lo
gic ‘
0
’
.
T
h
is in
verte
r
(A
3
) pro
d
u
ces
fu
ll swing
o
u
t
pu
t withou
t d
e
grad
ing
th
e sp
eed
o
f
th
e circu
it.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 6
,
N
o
. 1
,
Febru
a
ry
2
016
: 9
0
–
98
93
3.
R
E
SU
LTS AN
D ANA
LY
SIS
The p
r
op
ose
d
cur
r
ent
c
o
m
p
arat
or t
o
p
o
l
o
gy
base
d o
n
C
M
OS i
n
vert
e
r
s h
a
ve bee
n
de
si
g
n
ed
usi
n
g 9
0
nm
C
M
OS t
e
chn
o
l
o
gy
pa
ram
e
t
e
rs an
d A
n
al
og
Vi
rt
uos
o E
nvi
ro
nm
ent
of
t
h
e C
a
de
nce S
o
ft
ware.
The si
zes o
f
th
e tran
sistors
are listed
i
n
Tab
l
e
1
.
Th
e si
m
u
la
tio
n
s
are
p
e
rform
e
d
at a supp
ly vo
ltage (V
DD
) of
1
V. The
in
pu
t cu
rren
t varyin
g
b
e
tween 0
an
d
30
0
n
A
is in
j
ected
and
co
m
p
ared
. Fi
gu
re
2
illu
strates th
e tran
sien
t i
n
pu
t–
out
put
c
h
aract
eri
s
t
i
c
s of t
h
e
pr
o
pose
d
cu
rr
e
n
t
com
p
arat
or
al
on
g wi
t
h
t
h
e
i
n
st
ant
a
ne
ou
s po
we
r di
ssi
pat
i
on o
f
t
h
e st
r
u
ct
u
r
e.
A s
h
o
r
t
ave
r
a
g
e
pr
opa
gat
i
o
n
del
a
y
of
3
.
1 n
s
ec is
ob
serv
ed at th
e sp
ecified
inpu
t cu
rren
t
,
rei
n
st
at
i
n
g
t
h
e
ope
rat
i
n
g f
r
e
q
u
e
ncy
ra
n
g
e
of c
i
rcui
t
bet
w
een
20
0 M
H
z-
4
0
0
M
H
z.
Tabl
e 1.
T
r
a
n
si
st
or Si
zes
W
L
M
1
1.
32µ
0.
18µ
M
2
0.
2µ
0.
18µ
M
3
4.
5µ
1.
0µ
M
4
1.
5µ
2.
0µ
M
5
1.
32µ
0.
18µ
M
6
0.
2µ
0.
18µ
(a)
(b
)
Fi
gu
re
2.
Tra
n
s
i
ent
R
e
sp
on
se
sho
w
i
n
g
(a
) I
n
put
C
u
r
r
e
n
t
an
d
Out
put
V
o
l
t
a
ge a
n
d
(
b
)
I
n
st
ant
a
ne
ou
s P
o
w
e
r
Di
ssi
pat
i
o
n
of
t
h
e p
r
op
ose
d
st
ruct
ure
w
h
en
Ii
n =
3
0
0
n
A
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
High
S
p
e
ed
Power
Efficien
t
CMOS
In
verter Ba
sed
C
u
rren
t
Co
mp
ara
t
o
r
i
n
UMC 90
n
m
…
(Veep
sa
Bhatia
)
94
(a)
(b
)
(c)
Fi
gu
re
3.
Tra
n
s
i
ent
R
e
sp
on
se
sho
w
i
n
g
(a
) I
n
put
C
u
r
r
e
n
t
,
(
b
) O
u
t
put
V
o
l
t
a
ge a
n
d
(c
)
Inst
ant
a
ne
ou
s P
o
w
e
r
Di
ssi
pat
i
o
n
of
t
h
e p
r
op
ose
d
st
ruct
ure
w
h
en
Ii
n =
2 µ
A
.
Po
wer
di
ssi
pa
t
i
on f
o
r va
ri
o
u
s i
n
p
u
t
cu
rre
nt
s i
s
o
n
e
of the characteristics of this
circuit.
T
h
e
i
n
st
ant
a
ne
o
u
s
po
we
r di
ssi
pat
i
on o
f
t
h
e ci
rc
ui
t
i
s
sho
w
n
i
n
Figu
re
2
(
b
)
. Based
up
on
th
is ch
aracteristic, th
e
av
er
ag
e
p
o
w
e
r d
i
ssip
a
tion
is calcu
lated
to
b
e
24
.3
µW
at 1
V
f
o
r
300 n
A
i
n
pu
t curr
en
t. To
ex
h
i
bit th
e
perform
a
nce of the
circ
uit at
current
greater tha
n
,
1 µ
A
, the circuit
performance is e
v
aluated at
2 µ
A
a
n
d the
sam
e
is d
e
p
i
cted
in
Figure 3. Th
e sim
u
latio
n
resu
lts sho
w
that a six fol
d
increase i
n
current doesn’t esc
a
lates
t
h
e po
we
r co
nsum
pt
i
on
of
t
h
e ci
rcui
t
b
y
t
h
e sam
e
am
ount
. B
e
si
de
s, t
h
e pr
o
p
a
g
at
i
on del
a
y
re
duce
s
su
bstan
tially for cu
rren
ts
greater
tha
n
1 µ
A
t
h
ereby i
n
creasi
n
g the
s
p
eed of
com
p
arator
conside
r
ably.
The a
v
era
g
e
pr
opa
gat
i
o
n
del
a
y
of t
h
e ci
rc
ui
t
,
u
n
d
e
r
di
f
f
ere
n
t
i
n
put
c
u
r
r
en
t
s
are p
r
ese
n
t
e
d i
n
Fi
g
u
r
e
4
(
a) and
th
e variatio
n
of av
erag
e
p
r
o
p
a
g
a
ti
o
n
d
e
lay with
su
pp
ly vo
ltag
e
h
a
s b
e
en
illu
strated
in
Figu
re 4
(
b
)
.
As e
x
pected, the
delay dec
r
e
a
ses as t
h
e s
u
pply voltage
i
n
c
r
eases
beca
use
of increa
se in drain c
u
rre
n
t.
(a)
(b
)
Fi
gu
re 4.
Pr
o
p
a
gat
i
o
n
Del
a
y
vs. (a
)
I
n
put
C
u
r
r
ent
a
n
d (b
) Su
ppl
y
Vol
t
a
g
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 6
,
N
o
. 1
,
Febru
a
ry
2
016
: 9
0
–
98
95
Tem
p
erat
ure
v
a
ri
at
i
ons a
n
d
Pro
cess
param
e
t
e
rs ha
ve si
g
n
i
f
i
cant
i
m
pact
on t
h
e
per
f
o
r
m
a
nce of
CMOS circu
its. To
illu
strate th
e robu
stn
e
ss
o
f
pro
p
o
s
ed
arch
itectu
r
e, av
erag
e
p
r
o
p
a
g
a
tio
n
d
e
lay an
d
po
wer
di
ssi
pat
i
o
n ha
v
e
been cal
c
u
l
a
t
e
d f
o
r
va
ri
o
u
s
val
u
es
of t
e
m
p
erat
ure
ra
ngi
ng
fr
om
as l
o
w as -5
o
C
t
o
as
hi
gh a
s
15
0
o
C. From
F
i
gure 6(a), as t
e
m
p
erature inc
r
eases from
-5
o
C to
aro
und
roo
m
te
m
p
er
ature the delay
dec
r
eases
and t
h
en
dela
y increases al
m
o
st li
nearly with tem
p
erature
due t
o
d
ecrease i
n
drain c
u
rrent.
Sim
ilar
t
e
m
p
erat
ure
va
ri
at
i
ons
have
b
een si
m
u
l
a
t
e
d
fo
r p
o
we
r di
ss
i
p
at
i
on
of p
r
op
ose
d
cur
r
e
n
t
com
p
arat
or (
F
i
g
ure
6
(b)). In
th
ese si
m
u
latio
n
s
b
o
t
h
m
a
x
i
m
u
m an
d
m
i
n
i
mu
m
v
a
lu
es of p
o
wer h
a
v
e
b
een
illu
st
rated
.
Th
e
note
w
orthy as
pect of t
h
e
power m
odel is t
h
at ev
en
with
l
a
rg
e v
a
riatio
n
s
in
tem
p
eratu
r
e (-5
o
C to 150
o
C), t
h
e
po
we
r di
ssi
pat
i
on rem
a
i
n
s alm
o
st const
a
nt
.
Furt
he
rm
ore, t
h
e di
ffe
re
nce bet
w
ee
n m
a
xim
u
m
and
m
i
nim
u
m
pr
o
p
agat
i
o
n
de
l
a
y
i
s
not
m
o
re
t
h
an
2
n
s
.
Fi
gu
re
5.
A
v
er
age P
o
wer
Di
s
s
i
p
at
i
o
n
vs
.
In
p
u
t
C
u
rre
nt
(a)
(b
)
Fi
gu
re 6.
(a
) A
v
era
g
e Pr
opa
g
a
t
i
on Del
a
y
vs
.
Tem
p
erat
ure,
(b
)
P
o
wer Di
ss
i
p
at
i
on vs
.
Te
m
p
erat
ure
Fig
u
re
7
illu
strates th
e
v
a
riatio
n of
ou
tpu
t
voltag
e
with
tem
p
erat
u
r
e i
n
a mu
ch eloq
u
e
n
t
man
n
e
r.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
High
S
p
e
ed
Power
Efficien
t
CMOS
In
verter Ba
sed
C
u
rren
t
Co
mp
ara
t
o
r
i
n
UMC 90
n
m
…
(Veep
sa
Bhatia
)
96
Fi
gu
re 7.
Tra
n
s
i
ent
R
e
sp
on
se of
t
h
e O
u
t
p
ut
Vol
t
a
ge
o
f
Pr
o
pos
ed
C
u
rre
nt
C
o
m
p
arat
or fo
r vary
i
n
g
Tem
p
erature
To
furth
e
r ex
em
p
l
ify th
e functio
n
a
lity o
f
ci
rcu
it, t
h
e
p
r
op
osed
d
e
sign
h
a
s
b
een sim
u
lated
fo
r all th
e
pr
ocess
co
rne
r
s as s
h
o
w
n i
n
Fi
gu
re
8.
Fi
gu
re 8.
Tra
n
s
i
ent
R
e
sp
on
se of
t
h
e O
u
t
p
ut
Vol
t
a
ge
o
f
Pr
o
pos
ed
C
u
rre
nt
C
o
m
p
arat
or
at
vari
ous
P
r
oces
s
Co
rn
ers
The st
r
u
ct
ure
pr
o
pose
d
i
n
[
2
2]
i
s
one o
f
t
h
e pi
onee
r
i
n
g
wo
rk
s i
n
t
e
rm
s of t
h
e de
si
g
n
of a cur
r
e
n
t
com
p
arat
or. [
2
3]
-[
3
0
]
have re
po
rt
ed vari
ous cur
r
ent
c
o
m
p
arators that are a
m
odificati
on of [2
2]
.
O
f
al
l
t
h
ese,
[2
4]
gi
ves t
h
e
hi
g
h
est
s
p
ee
d a
n
d
l
o
west
p
o
we
r
di
ssi
p
a
t
i
on.
He
nce,
a com
p
ari
s
o
n
of t
h
e
per
f
o
rm
ance
param
e
t
e
rs of t
h
e pr
o
p
o
s
ed c
u
r
r
ent
com
p
ar
at
or t
o
t
hose
r
e
po
rt
ed i
n
[
22]
and [
24]
has
been
dra
w
n a
n
d sam
e
has
bee
n
rep
o
r
t
ed i
n
Tabl
e
2
.
It
can
be
see
n
t
h
at
t
h
e pr
opo
sed
stru
ctur
e
off
e
r
s
f
a
stest
r
e
sp
on
se and
r
easo
n
a
b
l
y
lo
w
p
o
wer d
i
ssip
atio
n
at th
e l
o
west sup
p
l
y vo
ltag
e
o
f
1
V
with
a m
u
ch
lo
wer inp
u
t
cu
rrent. Fig
u
re
9
illu
strates
th
e
ou
tpu
t
respo
n
s
e o
f
[2
2
]
wh
ile
th
at o
f
[2
4]
h
a
s b
een
illu
strated
in
Figure1
0.
Fi
gu
re 9.
O
u
t
p
ut
res
p
on
se of [2
2]
Fi
gu
re
10
. Out
p
ut
res
p
on
se of [2
4]
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 6
,
N
o
. 1
,
Febru
a
ry
2
016
: 9
0
–
98
97
Tabl
e
2. C
o
m
p
ari
s
o
n
of
Pr
o
p
o
se
d C
u
rre
nt
C
o
m
p
arat
or
wi
t
h
Po
p
u
l
a
r
Arc
h
i
t
ect
ures
[2
2]
a
n
d
[
2
4]
Pr
ocess
Supply
Voltage (V)
M
i
n
i
mu
m
I
nput Cur
r
e
nt
Avg Pr
opagation
Delay(
ns)
Power
Dissipation (
µ
W
)
Power-D
elay
Pr
oduct (
f
J)
No. of
Transistors
T
r
aff [21]
90 n
m
1
5 µA
3.
35
120.
2
112.
57
4
T
a
ng[23]
90 n
m
1
10 µA
4.
6
112.
57
517.
8
14
Pr
oposed
90 n
m
1
300 nA
3.
1
24.
3
93
6
4.
CO
NCL
USI
O
N
A fast
an
d
po
wer e
ffi
ci
ent
c
u
r
r
ent
c
o
m
p
arat
or ha
s bee
n
re
po
rt
ed c
o
m
p
ri
si
ng s
o
l
e
l
y
of C
M
OS i
n
vert
er
s
,
t
hus
of
feri
ng s
y
m
m
e
t
r
y
of st
r
u
ct
u
r
e. T
h
e p
r
op
ose
d
cu
rr
ent
com
p
arat
or
pr
ovi
des a com
m
e
nda
bl
e pe
rf
o
r
m
a
nce
in
co
m
p
arison to
th
e o
t
h
e
r
po
pu
larly u
s
ed
cu
rren
t co
m
p
arato
r
s as repo
rted
in
th
e literatu
re. Th
e
p
r
op
o
s
ed
st
ruct
u
r
e
has
b
een si
m
u
l
a
t
e
d on
9
0
nm
t
echnol
ogy
a
n
d
op
erat
es at
a s
u
pp
l
y
vol
t
a
ge
o
f
1
V
.
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BIOGRAP
HI
ES OF
AUTH
ORS
Veeps
a
Bha
tia
was born in 197
7. She r
eceived
B.E.
degr
ee in Electronics
and Communication
Engineering for Amravati University
, India in 19
99. She completed her Masters in Engineer
ing
from Delhi College of
Engin
eer
ing, Delhi Ind
i
a in 2005
and is
currently
pursuing Ph.D. from
Delhi T
echno
log
i
ca
l Universit
y
,
Delhi,
India
.
Sh
e
is
curr
entl
y wo
rking as
an As
s
i
s
t
ant P
r
ofes
s
o
r
in Depar
t
ment o
f
Electron
i
cs
an
d Communicatio
n
Engin
eering
at Indira Gandhi
Delhi
Techn
i
cal
Univers
i
t
y
for
W
o
m
e
n, Delhi,
I
ndia.
S
h
e has
a
t
each
ing and
ind
u
s
t
r
y
exper
i
enc
e
of 15
ye
ars
and
her areas of interest are curr
ent
mode circuits
, Analog to digital converters and
digital s
y
stem
design.
Neeta Pandey
w
a
s born in 1966. She did her M.
E.
in Microel
e
ctronics from
Birla Institut
e
of
Techno
log
y
and
Scien
ces, Pilan
i
and Ph. D.
fro
m Guru Gobind Singh Indrapr
a
stha University
Delhi. She has
served in Cent
ral El
ectron
i
cs
Engine
ering Re
search Institu
te
,
Pilani, Indi
an
Institute
of T
ech
nolog
y, De
lhi,
Pri
y
adarshin
i Col
l
ege of
Com
puter Scien
c
e
,
Noi
d
a and Bh
ara
t
i
Vid
y
ap
ee
th’s
C
o
lleg
e
of
Engin
eering
,
De
lhi
in
Various
c
a
pa
cit
i
es
. At
pres
en
t,
s
h
e is
As
s
i
s
t
ant
Professor in ECE departmen
t
,
Delhi Technolo
g
ic
al University. A life member of ISTE, and
member of IEEE, USA, she has published pap
e
rs
in Intern
at
io
nal, Na
tion
a
l Jo
urnals of reput
e
and conf
eren
ces
.
Her r
e
s
ear
ch in
t
e
res
t
s
ar
e
in Ana
l
og and
Digit
a
l
VLS
I
Des
i
gn.
Asok Bhattacha
r
yya ob
tain
ed
M. Tech
. and
Ph.D. degree fr
om
Institute of
Radio Ph
y
s
ics
,
Calcutta Univ
er
sity
, India in th
e
y
e
ar 1970 and
1981, respectiv
ely
.
He jo
ined D
e
lhi Colleg
e of
Engineering in
May
1974 and since th
en he
is with the same college and has worked in differ
e
nt
c
a
p
ac
itie
s of
Le
cture
r
, Assista
n
t
Profe
ssor,
Profe
ssor, Professor and Head of
the
Department
and
as Offici
ating
D
i
rec
t
or of
the
In
stitute
. Prof
. A.
Bhatta
char
yya
h
a
s worked
in di
fferent
fi
elds-
Digital S
y
s
t
em Design, Analog Sy
stem Design,
Easi
l
y
test
able a
nd diagn
o
sable Digital
s
y
stems/Fault to
leran
t
Computing and Medica
l Im
age P
r
oces
s
i
ng area
. Bes
i
de
s
his
reputed
research publ
ic
a
tions, he has aut
hored two rese
a
r
ch m
onographs. He is a fellow of IETE, lif
e
member of ISTE and sen
i
or member of
IEEE
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