Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
8,
No.
2,
April
2018,
pp.
926
–
932
ISSN:
2088-8708
926
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
A
60
GHz
CMOS
P
o
wer
Amplifier
f
or
W
ir
eless
Communications
T
uan
Anh
V
u
VNU
Uni
v
ersity
of
Engineering
and
T
echnology
,
V
ietnam
Article
Inf
o
Article
history:
Recei
v
ed
September
7,
2017
Re
vised
December
28,
2017
Accepted:
Jan
29,
2018
K
eyw
ord:
Po
wer
Amplifier
60
GHz
V
-band
W
ireless
Communication
Millimeter
-w
a
v
e
ABSTRA
CT
This
paper
presents
a
60
GHz
po
wer
amplifier
(P
A)
suitable
for
wireless
communications.
The
tw
o-stage
wideband
P
A
is
f
abricated
in
55
nm
CMOS.
Measurement
results
sho
w
that
the
P
A
obta
ins
a
peak
g
ain
of
16
dB
o
v
er
a
-3
dB
bandwidth
from
57
GHz
to
67
GHz.
It
archi
v
es
an
output
1
dB
compression
point
(OP1dB)
of
4
dBm
and
a
peak
po
wer
added
ef
ficienc
y
(P
AE)
of
12.6%.
The
P
A
consumes
a
total
DC
po
wer
of
38.3
mW
from
a
1.2
V
supply
v
oltage
while
its
core
occupies
a
chip
area
of
0.45
mm
2
.
Copyright
c
2018
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
Name:
T
uan
Anh
V
u
Af
filiation:
VNU
Uni
v
ersity
of
Engineering
and
T
echnology
Address:
144
Xuan
Thuy
Rd.,
Cau
Giay
Dist.,
Hanoi,
V
ietnam
Phone:
+84-4-3754-9338
Email:
tanhvu@vnu.edu.vn
1.
INTR
ODUCTION
W
ireless
communications
using
the
millimeter
-w
a
v
e
band
ha
v
e
been
gro
wing
in
the
past
fe
w
years
due
to
its
high
data-rate
transmiss
ion
capability
.
The
demands
for
high
data-rate
short
range
wireless
communication
ha
v
e
attracted
a
great
deal
of
interest
in
the
design
of
60
GHz
systems.
As
a
result,
the
Federal
Communications
Commission
(FCC)
of
the
United
States
has
of
ficially
appro
v
ed
the
spectrum
utilization
for
57
GHz
to
64
GHz
for
commercial
use.
CMOS
P
A
is
among
the
most
challenging
b
uilding
blocks
in
implementing
a
60
GHz
system.
The
main
purpose
of
a
P
A
design
is
to
pro
vide
suf
ficiently
high
output
po
wer
,
while
another
important
tar
get
is
to
achie
v
e
high
ef
ficienc
y
.
There
are
se
v
eral
obstacles
which
mak
e
the
implementations
of
a
P
A
v
ery
dif
ficult
in
CMOS
technology
.
The
use
of
submicron
CMOS
increases
the
dif
ficulty
of
implementation
due
to
technology
limitations
such
as
lo
w
breakdo
wn
v
oltage
and
poor
transconductance.
The
linearity
and
po
wer
ef
ficienc
y
are
lo
wer
than
other
technologies.
Ho
we
v
er
,
wit
h
the
trend
of
lo
wer
po
wer
transmitters
in
the
ne
xt
generation,
implementation
of
CMOS
P
As
with
good
ef
ficiencies
are
becoming
realistic
despite
steadily
declining
field-ef
fect
transistor
(FET)
breakdo
wn
v
oltages.
In
this
paper
,
we
are
going
to
present
the
designs
and
measurement
results
of
a
60
GHz
P
A
tar
geted
for
wireless
communications.
The
paper
is
or
g
anized
as
follo
ws.
Section
2
presents
fundamentals
of
po
wer
amplifiers.
Section
3
introduces
the
architecture
of
the
proposed
60
GHz
P
A
including
a
detailed
description
of
the
circuit
topology
.
The
measurement
results
are
presented
in
section
4
and
conclusions
are
gi
v
en
in
the
last
section.
2.
PO
WER
AMPLIFIER
B
ASICS
2.1.
P
A
Block
Diagram
The
general
design
concept
of
a
P
A
is
gi
v
en
in
Fig.
1.
The
tw
o
port
netw
ork
is
applied
in
the
design
consisting
of
tw
o
matching
netw
orks
that
are
used
on
both
sides
of
the
po
wer
transistor
.
Maximum
g
ain
will
be
real-
ized
when
the
matching
netw
orks
pro
vide
a
conjug
ate
match
between
the
source/load
impedance
and
the
transistor
impedances
[1].
Specifically
,
the
matching
netw
orks
transform
the
input
and
output
impedances
Z
0
to
the
source
and
J
ournal
Homepage:
http://iaescor
e
.com/journals/inde
x.php/IJECE
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
,
DOI:
10.11591/ijece.v8i2.pp926-932
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
927
T
able
1.
Conduction
angles
of
the
dif
ferent
current-mode
P
A
classes
Class
Conductance
Angle
A
2
AB
–2
B
C
0–
load
impedances
Z
S
and
Z
L
,
respecti
v
ely
.
Both
input
and
output
matching
netw
orks
are
designed
for
50
e
xternal
load.
Figure
1.
Block
diagram
of
a
P
A.
2.2.
Classification
of
P
As
There
are
generally
tw
o
types
of
P
As:
the
current
source
mode
P
A
and
the
switching
mode
P
A.
Dif
ferent
kinds
of
each
mode
of
P
As
and
their
functional
principles
are
introduced
in
detail
in
[2].
In
the
current
source
mode
P
A,
the
po
wer
de
vice
is
re
g
arded
as
a
current
source,
which
is
controlled
by
the
input
signal.
The
most
important
current
source
mode
P
As
are
class
A,
class
B,
class
AB
and
class
C.
The
y
dif
fer
from
each
other
in
the
operating
point.
Fig.
2
illustrates
the
dif
ferent
classes
of
the
current
source
mode
P
A
in
the
transfer
characteristic
of
a
FET
de
vice.
The
drain
current
I
D
e
xhibits
pinch-of
f,
when
the
channel
is
completely
closed
by
the
g
ate-source
v
oltage
V
GS
and
reaches
the
saturation,
in
which
further
increase
of
g
ate-source
v
oltage
results
in
no
further
increase
in
drain
current.
The
other
v
ery
important
concept
to
define
the
dif
ferent
classes
of
the
current
source
mode
P
A
is
the
conduction
angle
.
The
conduction
angle
depicts
the
proportion
of
the
RF
c
ycle
for
which
conduction
occurs.
The
conduction
angles
of
dif
ferent
classes
are
summarized
in
table
1.
Figure
2.
Operating
points
of
dif
ferent
current-mode
P
As
classes.
2.3.
P
A
Efficiency
Ef
ficienc
y
is
a
measure
of
performance
of
a
P
A.
The
performance
of
a
P
A
will
be
better
if
its
ef
ficienc
y
is
higher
,
irrespecti
v
e
of
its
definition.
The
P
A
is
the
most
po
wer
-consuming
block
in
a
wireless
transcei
v
er
.
Its
po
wer
60
GHz
CMOS
P
ower
Amplifier
Evaluation Warning : The document was created with Spire.PDF for Python.
928
ISSN:
2088-8708
ef
ficienc
y
has
a
direct
impa
ct
on
the
battery
life
of
mobile
de
vices.
Se
v
eral
definitions
of
ef
ficienc
y
are
commonly
used
with
P
As.
Most
widely
used
measures
are
the
drain
ef
ficienc
y
and
po
wer
added
ef
ficienc
y
.
The
drain
ef
ficienc
y
is
defined
as
=
P
OUT
P
DC
(1)
where
P
OUT
is
the
RF
output
po
wer
at
operating
frequenc
y
and
P
DC
the
DC
po
wer
consumption
of
the
P
A
output
stage.
It
re
v
eals
ho
w
ef
ficient
the
P
A
is
when
it
con
v
erts
the
po
wer
from
DC
to
A
C.
The
P
AE
is
gi
v
en
by
P
AE
=
P
OUT
P
IN
P
DC
(2)
where
P
IN
is
the
input
po
wer
fed
to
the
P
A
and
P
DC
the
total
DC
po
wer
consumption
of
the
P
A.
The
P
AE
gets
close
to
if
the
g
ain
of
the
P
A
is
suf
ficient
high
so
that
the
input
po
wer
is
ne
gligible.
3.
DESIGN
OF
60
GHz
PO
WER
AMPLIFIER
The
60
GHz
P
A
is
designed
using
55
nm
CMOS
process
pro
vided
by
Fuji
tsu
Ltd.
Its
back
end
consists
of
11
copper
layers
and
a
top
aluminum
redistrib
ution
layer
(RDL).
The
cross-vie
w
of
a
grounded
coplanar
w
a
v
e-guide
transmission
line
(GCPW
-TL)
is
depicted
in
Fig.
3
[3].
The
GCPW
-TL
with
the
characteristic
impedance
of
50
(the
5
0
GCPW
-TL)
is
used
for
shunt
and
series
stubs
of
the
matching
netw
orks
and
for
connecting
to
the
input
and
output
pads
of
the
60
GHz
P
A.
Its
signal
line
consists
of
the
RDL
layer
with
a
width
of
8
µm.
Ground
(GND)
w
alls
composed
of
the
6th
to
11th
metal
layers
with
a
width
of
9
µm
are
placed
on
the
both
side
of
the
signal
line
at
the
distance
of
11.5
µm.
The
3rd
to
5th
metal
layers
are
meshed
and
stitched
together
with
vias
to
form
the
GND
plane.
Figure
3.
The
cross-vie
w
of
the
50
GCPW
-TL.
The
complete
circuit
of
the
proposed
P
A
with
all
component
v
alues
are
gi
v
en
in
Fig.
4.
It
includes
an
input
matching
netw
ork,
an
output
matching
netw
ork,
tw
o
common-source
based
amplifying
stages
and
an
inter
-
stage
matching
netw
ork.
F
or
bandwidth
enhancement,
multi-stage
matchings
using
capacitors
and
GCPW
-TLs
are
adopted.
The
series
capacitors
and
GCPW
-TLs
form
4th-order
and
2nd-order
high-pass
filters
at
the
input
and
output
of
the
P
A,
respecti
v
ely
.
The
input
is
matched
to
50
for
measurement
purpose
while
the
load
is
optimized
for
maximizing
output
po
wer
using
load-pull
simulation.
The
inter
-stage
matching
netw
ork
is
based
on
the
PI
netw
ork
for
wideband
performance.
A
128
resistor
is
added
in
series
to
the
transistor’
s
g
ate
of
the
first
amplifying
stage
for
stabilization.
The
minimum-loss
cascade
stabilizing
resistor
v
alue
is
det
ermined
from
the
Smith
chart
by
finding
the
constant
resistance
that
is
tangent
to
the
appropriate
stability
circle
[4].
All
of
the
capacitors
also
act
as
coupling
capacitors
while
the
DC
bias
v
oltages
are
applied
through
t
he
shunt
GCPW
-TLs.
The
bias
v
oltages
are
common
to
all
amplifying
stages.
The
connection
between
the
MOSFETs,
MOM
capacitors
and
GCPW
-TLs
are
made
by
the
10th
and
11th
metal
layers.
The
lengths
of
the
GCPW
-TLs
and
the
MOM
capacitor
v
alues
are
determined
by
a
nonmetric
optimization
process
taki
ng
into
account
the
models
of
MOSFETs,
MOM
capacitors
and
GCPW
-TLs.
The
parasitic
components
are
e
xtracted
using
bond-based
design
which
is
a
measurement-based
design
approach
to
a
v
oiding
the
dif
ficulty
associated
with
layout
parasitics
when
ordinary
layout
parasitic
e
xtraction
(LPE)
tools
used
for
chip
design
do
not
e
xtract
inductances
[5].
The
f
ar
end
of
each
shunt
stub
is
terminated
by
a
wideband
decoupling
po
wer
line
with
v
ery
lo
w
characteristic
impedance
(the
0
TL)
[6].
IJECE
V
ol.
8,
No.
2,
April
2018:
926
–
932
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
929
Figure
4.
The
proposed
60
GHz
P
A.
4.
MEASUREMENT
RESUL
TS
In
order
to
v
erify
the
performance
of
the
60
GHz
P
A,
a
chip
prototype
w
as
f
abricated
in
55
nm
CMOS.
Fig.
5
sho
ws
the
die
microphotograph
of
the
P
A.
The
P
A
occupies
an
area
of
0.72
0.63
mm
2
including
probe
pads.
The
P
A
w
as
measured
by
means
of
on-chip
probings
using
a
probe
station.
The
RF
probe
pads
were
designed
for
ground-signal-ground
(GSG)
probes
with
750
µm
pitch.
The
Anritsu
37397D
VN
A
and
V
-band
frequenc
y
e
xtenders
were
used
for
measuring
small-signal
S-parameters.
Figure
5.
The
die
microphotograph
of
the
60
GHz
P
A.
Fig.
6
sho
ws
the
measured
and
simulated
S-parameters
of
the
60
GHz
P
A.
As
can
be
seen
in
this
figure,
the
measured
results
sho
w
good
agreements
with
the
simulated
ones.
Both
input
and
output
return
loss
indicate
wideband
performance
when
S
11
and
S
22
remain
belo
w
-10
dB
o
v
er
almost
of
the
-3
dB
bandwidth
from
57
GHz
to
67
GHz.
The
60
GHz
P
A
achie
v
es
a
peak
g
ain
of
16
dB
at
61
GHz.
The
re
v
erse
isolation
is
lo
wer
than
-20
dB
(not
sho
wn
in
the
figure).
A
high
re
v
erse
isolation
guarantees
high
stability
for
the
P
A.
Fig.
7
plots
the
output
po
wer
v
ersus
the
input
po
wer
.
A
K
e
ysight
E8244A
signal
generator
and
a
V
i
v
aT
ech
60
GHz
CMOS
P
ower
Amplifier
Evaluation Warning : The document was created with Spire.PDF for Python.
930
ISSN:
2088-8708
Figure
6.
The
measured
and
simulated
S-parameter
of
the
60
GHz
P
A.
VTXF
A-06-12
signal
module
were
used
for
generating
input
signal
at
60
GHz
while
a
VDI
PM5-305V
po
wer
sensor
w
as
used
to
measure
the
output
po
wer
.
Due
to
the
equipment
limitation
at
V
-band
in
our
laboratory
,
the
output
po
wer
can
only
be
measured
up
to
-3
dBm
of
the
input
po
wer
.
At
60
GHz,
the
designed
P
A
obtains
a
OP1dB
of
approximately
4
dBm.
Fig.
8
and
Fig.
9
sho
w
the
drain
ef
ficienc
y
and
P
AE
v
ersus
the
input
po
wers,
respecti
v
ely
.
The
designed
P
A
archi
v
es
a
peak
P
AE
of
12.6%
at
-3.5
dBm
input
po
wer
.
The
P
A
consumes
a
total
po
wer
of
38.3
mW
from
a
1.2
V
supply
v
oltage.
T
able
2
summarizes
the
performance
of
the
proposed
P
A
and
compares
it
to
other
published
ones
operating
in
the
similar
frequenc
y
range.
A
popular
figure-of-merit
(F
oM)
used
for
comparison
is
defined
as
the
g
ain
bandwidth
product
(GBWP)
di
vided
by
the
DC
po
wer
consumption
(
P
DC
).
Figure
7.
The
measured
and
simulated
output
po
wer
v
ersus
the
input
po
wer
of
the
60
GHz
P
A.
5.
CONCLUSIONS
In
this
paper
,
we
ha
v
e
presented
the
designs
and
measurement
results
of
the
60
GHz
P
A
tar
geted
for
wireless
communications.
The
proposed
P
A
obta
ins
the
peak
g
ain
of
16
dB
while
the
-3
dB
bandwidth
co
v
er
the
entire
of
the
IJECE
V
ol.
8,
No.
2,
April
2018:
926
–
932
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
931
Figure
8.
The
measured
and
simulated
drain
ef
ficienc
y
of
the
60
GHz
P
A.
Figure
9.
The
measured
and
simulated
P
AE
of
the
60
GHz
P
A.
T
able
2.
Comparison
with
pre
vious
published
P
As
operating
in
the
60
GHz
frequenc
y
band
P
arameter
RFIC’10
[7]
APMC’12
[8]
RFIT’15
[9]
T
-MTT’13
[10]
MWCL
’15
[11]
This
w
ork
CMOS
T
echnology
65
nm
65
nm
65
nm
65
nm
65
nm
55
nm
No.
of
Stages
3
2
3
4
3
2
Gain
(dB)
30
12.1
20
20
20
16
-3
dB
BW(GHz)
7
7
8
4.5
15
10
Peak
P
AE
(%)
18
11.1
14
6.6
9
12.6
Die
Area
(mm
2
)
0.06
0.61
0.56
2.25
0.7
0.45
OP1dB
(dBm)
6.8
4.5
10.4
13.5
5
4
Po
wer
Cons.
(mW)
65
45.8
93
480
60
38.3
GBWP/
P
DC
3.41
0.62
0.86
0.09
2.5
1.65
60
GHz
CMOS
P
ower
Amplifier
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932
ISSN:
2088-8708
60
GHz
frequenc
y
band.
It
e
xhibits
the
OP1dB
of
4
dBm
and
the
peak
P
AE
of
12.6%.
The
total
po
wer
consumption
of
the
P
A
is
38.3
mW
while
it
occupies
the
chi
p
area
of
0.45
mm
2
including
probe
pads.
The
performances
of
the
designed
P
A
are
competiti
v
e
to
other
state-of-the-art
P
As
in
CMOS.
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27-GHz
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2015
IEEE
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R.
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10
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W
ireless
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oshida,
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a
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e
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2015
IEEE
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w
a
v
e
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2015.
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M.
Boers,
A
60
GHz
T
ransformer
Coupled
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in
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Digi
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CMOS,
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Frequenc
y
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grated
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2010.
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R.
Minami,
K.
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K.
Okada,
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Matsuza
w
a,
A
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wer
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echnique,
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w
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v
e
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D.
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L.
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Y
.
W
ang,
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and
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orks
in
65-nm
CMOS,
2015
IEEE
International
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on
Radio-Frequenc
y
Inte
gration
T
echnology
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2015)
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130132,
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2015.
[10]
S.
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B.
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N.
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D.
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E.
K
erherv
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ain
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wer
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plifier
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a
v
e
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6,
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2013.
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H.
Zhang
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Q.
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CMOS
W
ideband
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ving
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Multi-Section
Coupled
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IEEE
Micro
w
a
v
e
and
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ireless
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ol.
25,
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9,
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600602,
September
2015.
BIOGRAPHY
OF
A
UTHOR
T
uan
Anh
V
u
recei
v
ed
the
B.S
de
gree
and
M.Sc
de
gree
in
Electronics
and
T
elecommunications
T
echnology
from
Uni
v
ersity
of
Engineering
and
T
echnology
,
V
ietnam
National
Uni
v
ersity
in
2006
and
2009,
respecti
v
ely
.
In
2013,
he
recei
v
ed
Ph.D
de
gree
in
the
field
of
analog/mix
ed-signal
RF
nanoelectronics
from
Uni
v
ersity
of
Oslo,
Norw
ay
.
Since
2014,
he
has
been
a
lecturer
at
F
aculty
of
Electronics
and
T
elecommunications,
VNU
Uni
v
ersity
of
Engineering
and
T
echnology
.
Dr
.
T
uan
Anh
V
u
w
as
with
Department
of
Semiconductor
Electronics
and
Inte
gration
Science,
Hiroshima
Uni
v
ersity
as
a
postdoctoral
researcher
for
one
year
.
He
is
no
w
doing
postdoc
at
Department
of
Electrical
and
Computer
Engineering,
Uni
v
ersity
of
California,
Da
vis
.
His
research
interests
are
analog
RF
inte
grated
circuit
designs
including
po
wer
amplifiers,
lo
w
noise
amplifiers,
mix
ers,
fre-
quenc
y
multipliers,
etc.
IJECE
V
ol.
8,
No.
2,
April
2018:
926
–
932
Evaluation Warning : The document was created with Spire.PDF for Python.