Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
Vol.
5, No. 6, Decem
ber
2015, pp. 1336~
1
346
I
S
SN
: 208
8-8
7
0
8
1
336
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
An SoC Architecture for Real-Time Noise Cancellation
System Using Variable Speech PDF Method
Trio A
d
ion
o
,
Adit
ya F.
Ar
d
y
ant
o
,
Nur
A
h
madi,
Idh
a
m
Hafiz
h
, Septi
a
n G.
P.
Pu
tra
School
of El
ectr
i
cal
Engin
eer
ing and
Inform
ati
c
s, Institut Tekno
lo
gi
Bandung
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Apr 14, 2015
Rev
i
sed
Sep
11
, 20
15
Accepted
Sep 29, 2015
This
paper pres
ents
the ar
chit
ec
ture
and implementation of s
y
stem-on-chip
(S
oC) for real
ti
m
e
nois
e
can
ce
l
l
ation
s
y
s
t
em
which exp
l
oits
v
a
riabl
e
s
p
ee
ch
probability
d
e
n
s
ity
function (
P
DF
) and maximum a posteriori (MAP)
estimation ru
le
as noise cancelling al
gor
ithm.
The h
a
rdware s
o
ftware
co-
des
i
gn approa
c
h
is
em
plo
y
ed
to ach
iev
e
re
al-tim
e p
e
rform
ance whi
l
e
considering
e
a
se of
im
plem
ent
a
tion
and
desig
n
flex
ibil
it
y.
T
h
e softwar
e
m
odule utilizes LEON SPARC-
v8 and FPU
co-
p
rosessor as pro
cessing unit
.
The AMBA based Hanning Filter and FFT
/IF
F
T
are uti
l
i
zed as
proces
s
i
ng
accelerator modules to incr
ease
s
y
st
em performance.
The FFT/IFFT module
emplo
y
s custom Radix-2
2
Single Delay
Feedback (R22SDF). I
n
order to
deliv
er high data transfer r
a
te b
e
tween
buff
e
r and hardware
acceler
ators, th
e
DM
A controller
is
incorporat
ed.
The ove
ra
ll s
y
s
t
em
im
plem
enta
tion util
iz
es
18,500 logic elements and consumes 21.
87 kB of
memory
. Th
e sy
stem tak
e
s
only
0
.
69 ms l
a
ten
c
y
which is appropria
t
e
for
real-t
im
e appli
cat
ion. An
FPGA Altera DE2-70 is used for prot
oty
p
ing
with both algor
ithms and the
noise cancellatio
n function h
a
ve
been v
e
rif
i
ed.
Keyword:
FPGA
LEON P
r
ocess
o
r
No
ise Can
cellatio
n
System
-on-Chi
p
V
a
r
i
ab
le Sp
eech
PD
F
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Trio
Ad
ion
o
,
Sch
ool
o
f
El
ec
t
r
i
cal
En
gi
neer
i
ng a
n
d
In
fo
rm
at
i
c
s,
Ban
dun
g In
stitu
te of Techn
o
l
o
g
y
,
Jl. G
a
n
e
sh
a
N
o
10
, Band
ung
40
132
,
In
don
esia.
Em
a
il: tad
i
o
n
o
@stei.itb
.ac.i
d
1
.
IN
TR
OD
UC
TI
ON
Noi
s
e i
s
a c
o
m
m
on p
h
en
om
eno
n
t
h
at
occ
u
rs i
n
t
h
e a
u
di
o
si
gnal
,
i
n
cl
udi
ng
t
h
e
v
o
i
ce si
gnal
,
w
h
i
c
h
may distort or conceals any
inform
a
tion contained i
n
the signal. T
h
ere
f
ore
,
the audio
signal enha
nce
m
ent
m
e
thods
continue
to
be
de
velope
d
ove
r ti
m
e
for a
wi
de
ra
nge
of
nois
e
types a
n
d a
pplication c
o
nditions
.
Seve
ral
m
e
thods exist on the literature
to deal with this
m
a
tter [1]. A spectral substraction (SS
)
m
e
thod
propose
d
by Boll [2] estim
a
t
es the spect
ral of clear
sp
eec
h si
g
n
al
by
s
u
bt
ract
i
n
g n
o
i
s
e
spect
ra
fr
om
noi
s
y
sp
eech
sp
ectra. Th
e sub
t
racti
o
n pro
c
e
ss
h
a
s to
b
e
carried ou
t carefu
lly to
avo
i
d an
y
d
i
sto
r
tion
.
To
o little
su
bstraction
will k
eep
th
e i
n
tefering
no
ise,
wh
ile too
m
u
ch
su
b
s
t
r
actio
n
will lead
to
imp
o
rtan
t info
rmation
bei
n
g rem
ove
d [
3
]
.
M
odi
fi
cat
i
on o
v
er S
S
m
e
t
hod cal
l
e
d as ge
neral
i
z
ed spect
ral
su
bst
r
act
i
o
n (
G
S
S
) was
pr
o
pose
d
t
o
i
m
pr
o
v
e n
o
i
s
e ca
ncel
l
a
t
i
on
per
f
o
rm
ance w
h
i
l
e
kee
p
i
n
g t
h
e
co
m
put
at
i
onal
si
m
p
li
ci
t
y
[4]
.
A
not
he
r
m
e
thod utilizing
a
m
i
nim
u
m
m
ean-s
qua
re error (MMSE)
of t
h
e s
h
ort-tim
e spectral am
plitude (S
TS
A)
wa
s
pr
o
pose
d
by
Ep
hrai
m
-
M
a
l
a
h [
5
]
w
h
i
c
h
p
r
o
v
i
d
es
an i
m
pr
o
v
ed
pe
rf
or
m
a
nce res
u
l
t
.
Lot
t
e
r a
n
d
Va
ry
[
6
]
pr
o
pose
d
a
n
effi
ci
ent
m
e
t
h
od
base
d o
n
m
a
xim
u
m
a p
o
st
eri
o
ri
(M
A
P
) est
i
m
at
i
on and s
upe
r-
G
a
ussi
a
n
st
at
i
s
t
i
cal
m
odel
,
whi
c
h
d
o
es
not
re
qui
re t
h
e use of
ta
bles for special com
p
licated functions as Ephraim
-
M
a
l
a
h m
e
t
hod
d
o
es.
A m
o
d
i
fi
ed M
A
P est
i
m
a
ti
on
usi
n
g
a vari
a
b
l
e
s
p
e
ech s
p
ect
ral
d
i
st
ri
but
i
o
n
was
al
so
p
r
op
o
s
ed
, wh
ich
ap
pro
x
i
m
a
te
n
o
i
se prob
ab
ility d
e
n
s
ity fu
n
c
tio
n
(PDF) m
o
re lik
e a Delta
fun
c
tion
[7
].
We
per
f
o
r
m
sim
u
l
a
t
i
on o
v
e
r
several
e
x
i
s
t
i
n
g m
e
t
hods
by
usi
n
g a
refe
re
n
ce so
un
d
sam
p
l
e
whi
c
h i
s
adde
d wit
h
Additive
White Gaussian
Noise
ove
r va
ri
ous S
N
R values
. The perform
a
nce of eac
h m
e
thod can
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
SoC Arc
h
itecture for
Re
al-Time
Noise C
ancellati
on Sys
t
em Usi
n
g
V
a
ri
able
Speech P
D
F… (Trio A
d
iono)
1
337
be see
n
by
c
o
m
p
ari
ng t
h
e
S
e
gm
ent
a
l
SNR
(Se
g
S
N
R
)
o
f
t
h
e
o
u
t
p
ut
si
gnal
.
Se
gS
NR
can
p
r
o
v
i
d
e
m
o
re
o
b
j
ectiv
e p
a
rameter to
co
m
p
are th
e so
und
q
u
a
lity with
the referen
ce, b
e
cau
se
Se
gSNR
p
e
rfo
r
m
s
calcu
lation
of a
v
era
g
e error
on eac
h segment [8].
Th
e
resu
lts of th
e si
m
u
latio
n
are sh
own
in
Figu
re 1
.
Th
e
wav
e
fo
rm
o
f
i
n
p
u
t
si
gnal
an
d p
r
oces
sed si
gnal
i
s
sh
ow
n
i
n
Fi
gu
re 2
.
The re
qui
re
d
pr
ocessi
n
g
t
i
m
e
i
s
al
so cal
cul
a
t
e
d t
o
com
p
are each
algorithm
perform
a
nce as s
h
own i
n
Ta
ble
1.
Th
e sim
u
latio
n
resu
lts sh
ow t
h
at th
ere is a ten
d
e
n
c
y of better p
e
rfo
r
m
a
n
ce b
y
u
s
ing
Vari
ab
le Sp
eech
PDF
using MAP
m
e
thod. T
h
is
m
e
thod el
im
inates alm
o
st all
noises in
non-
s
p
eech se
gm
ent, while m
a
intaining
good quality in speech se
gm
e
n
t as
shown in Figure 2. However, Vari
a
b
le Speec
h PDF using MAP algorithm
m
e
t
hod re
q
u
i
r
es t
h
e pr
ocessi
ng t
i
m
e about
t
w
i
ce of SS
or
GSS m
e
t
h
o
d
. T
h
u
s
, t
h
e
r
e
i
s
t
r
ade-
of
f b
e
t
w
een
SegS
NR
p
e
r
f
o
r
m
a
nce and
pr
ocessi
n
g
t
i
m
e. In t
h
i
s
case, s
eeki
n
g t
o
bet
t
e
r pe
rf
orm
a
nce
and c
o
nsi
s
t
e
nc
y
,
t
h
e
Vari
a
b
l
e
S
p
eec
h P
D
F
usi
n
g
M
A
P m
e
t
hod
wi
l
l
be
use
d
i
n
p
r
op
ose
d
Sy
st
em
-o
n-C
h
i
p
(S
oC
) arc
h
i
t
ect
ure
.
Fi
gu
re
1.
Se
gS
NR
c
o
m
p
ari
s
o
n
of
va
ri
o
u
s al
go
ri
t
h
m
s
Fi
gu
re
2.
The
out
put
si
g
n
al
u
s
i
n
g
va
ri
o
u
s
n
o
i
se cancel
l
a
t
i
on al
g
o
r
i
t
h
m
s
i
n
si
m
u
l
a
ti
on,
n
o
i
se SNR
5
dB
(
f
r
o
m
t
op
t
o
bot
t
o
m
:
n
o
i
s
y
speec
h,
out
put
SS,
o
u
t
put
GS
S, o
u
t
p
u
t
M
A
P, o
u
t
p
ut
m
-
M
A
P,
cl
ear speec
h)
Tabl
e
1.
Pr
oce
ssi
ng
t
i
m
e
i
n
si
m
u
l
a
t
i
on o
f
va
ri
o
u
s al
g
o
r
i
t
h
m
s
M
e
thod Pr
ocessing
T
i
m
e
(µ
ѕ
)
SS 17.
699
GSS 18.
782
M
A
P 35.
748
M
odified M
A
P
32.
191
No
ise can
cellatio
n
system
i
m
p
l
e
m
en
tatio
n
can
b
e
r
ealized usin
g har
d
ware o
r
s
o
ft
w
a
re. Har
d
ware
im
ple
m
entatio
n can res
u
lt in an extrem
ely
fast syste
m
perf
orm
a
nce; ho
weve
r the re
q
u
ire
d
tim
e
for sy
stem
desi
g
n
i
s
q
u
i
t
e
l
o
n
g
a
n
d
n
o
t
fl
exi
b
l
e
f
o
r al
go
ri
t
h
m
and t
uni
ng
pa
ram
e
ter
up
dat
e
.
I
n
cont
rast
t
o
ha
r
d
wa
re,
so
ft
ware
d
e
si
gn
im
p
l
e
m
en
tati
o
n
can b
e
acco
m
p
lish
e
d
qu
i
c
k
l
y with
h
i
gh flex
ib
ility, but sig
n
i
fican
tly slo
w
er
sy
st
em
perfo
r
m
ances [9]
.
I
n
or
de
r t
o
t
a
k
e
adva
nt
ages
of b
o
t
h
m
e
t
h
o
d
s an
d re
duce
t
h
ei
r dra
w
ba
ck, we
i
n
co
rp
orat
e
ha
r
d
wa
re-
s
o
f
t
w
a
r
e co
-desi
g
n
i
n
t
h
e
pr
o
pose
d
sy
st
em
desi
gn
an
d i
m
pl
em
ent
a
t
i
on
.
Th
e
r
e
st
o
f
th
is p
a
p
e
r is
o
r
g
a
nized
as
fo
llo
w
s
. Section
2
explain
s
th
e
pr
oposed
al
g
o
r
ith
m
w
h
ich
u
s
es
Variab
le Sp
eech
PDF with
MAP Estim
a
t
i
o
n. Sectio
n 3
descri
bes t
h
e
pr
op
ose
d
S
o
C
archi
t
ect
ure
whi
c
h
incorporates s
e
veral m
odule
s
suc
h
as input/output buffer, window
filte
r, FF
T/IFF
T
,
AHB c
o
nnecti
o
n, and
soft
ware
desi
g
n
. T
h
e FP
G
A
im
pl
em
ent
a
t
i
on a
n
d pe
rf
or
m
a
nce eval
uat
i
on i
s
gi
ve
n i
n
Sect
i
o
n 4
.
Fi
nal
l
y
,
concl
u
si
o
n
s a
r
e d
r
aw
n i
n
Sec
t
i
on
5.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE
Vol. 5, No. 6, D
ecem
ber
2015 :
1336 –
1346
1
338
2
.
PROPOSE
D
NOISE
CANCELLATION ALGORIT
H
M
We propose
d
variable
speech probability
density
function (PDF) with
m
a
xim
u
m
a
poste
riori (MAP)
estim
a
tion as
noise ca
ncell
i
ng algorithm [6].
In a
speech se
gm
ent, the PDF
of spectral
distribution
approaches
Ra
yleigh de
nsity, while
in
a
non
-sp
eech
seg
m
en
t, it appro
a
ch
es ex
pon
en
tial fun
c
tion
.
Th
e PDF
param
e
t
e
rs of
speec
h spect
ra
l
di
st
ri
but
i
o
n a
r
e de
duce
d
f
r
o
m
l
a
rge am
ount
s of
ob
ser
v
at
i
ons
. B
a
sed o
n
PDF
,
noi
se
cancel
l
a
t
i
on ca
n
be a
c
hi
eved
by
usi
n
g
M
A
P est
i
m
ati
on.
Aft
e
r
o
b
t
a
i
n
i
n
g
noi
se
p
o
w
er
spect
r
a
l
de
nsi
t
y
fr
om
est
i
m
a
t
e
d
noi
se
spe
c
t
r
a, a
p
r
i
o
ri
and a
posteriori
shou
ld
b
e
cal
cu
lated
.
(
1
)
The v
a
l
u
e o
f
cann
o
t
be
de
ri
ve
d st
rai
g
ht
-
f
o
r
wa
r
d
l
y
, so
a pri
o
ri
val
u
e
m
u
st
be est
i
m
at
ed.
Est
i
m
a
t
i
on i
s
d
one
u
s
i
n
g
deci
si
on
-di
r
ect
ed
m
e
t
hod
p
r
o
p
o
s
e
d
by
E
p
rai
m
dan M
a
l
a
h
[
5
]
(
2
)
Wi
t
h
α
i
s
f
o
r
g
et
t
i
ng fact
or
b
e
t
w
een
0 a
n
d
1. M
A
P
est
i
m
a
t
i
on i
s
use
d
t
o
est
i
m
at
e reconst
r
uct
i
o
n
gai
n
. B
a
se
d
on obse
rvations of m
a
ny spe
ech sam
p
les, s
p
eech m
odel is cha
r
acterized
with s
p
ectral
distribution PDF
p
(
S
)
and
p
(
∠
S
)
(
3
)
Joi
n
t
M
A
P
Est
i
m
a
t
o
r t
h
en
gi
v
e
s gai
n
G a
n
d
pha
se f
u
nct
i
o
n
G
whi
c
h
pr
o
v
i
d
es s
p
eec
h am
pl
i
t
ude a
n
d
p
h
a
se sp
ectra t
h
at can m
a
x
i
mize co
nd
ition
a
l jo
in
t PDF
p
(
S
,
∠
S|X
).
(
4
)
Whe
n
µ
=
3.
1,
= 1,
a
n
d v v
a
ri
es
[
5
]
,
peak
am
pl
it
ude of
p
(
S
) is
v
e
ry small if
υ
→
0,
w
h
i
c
h i
s
sui
t
a
bl
e f
o
r
no
n-s
p
eec
h se
gm
ent
t
o
el
i
m
i
n
ate n
o
i
s
e.
On
t
h
e ot
he
r
han
d
,
peak
am
pl
i
t
ude of
p
(
S
)
a
p
p
r
oache
s
larg
e v
a
lu
e
when
υ
→
2
:
0
,
wh
ich
is su
itab
l
e li
m
i
ted
p
a
rameter th
at is
u
s
ed
to d
e
fin
e
υ
.
Wi
t
h
R
(
n
) i
s
r
a
t
i
o
bet
w
ee
n i
n
p
u
t
p
o
w
er
sp
ect
ra an
d
noi
s
e
po
we
r s
p
ect
ra, a
nd
F
(
k
) is weigh
ting
factor.
R
(
n
)
i
s
obt
ai
ne
d by
:
Wi
t
h
β
i
s
f
o
rg
et
t
i
ng fact
o
r
b
e
t
w
een
0 a
nd
1. C
onst
a
nt
s u
s
ed i
n
si
m
u
l
a
tion c
o
m
e
s fro
m
[5]
wi
t
h
a
litt
le
m
o
d
i
ficatio
n
b
a
sed
on
trial an
d
error,
wh
ich
are
α
=
0.
95
,
β
= 0.50
,
µ
= 3.
1,
an
d
F
k
=
1.
3.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
SoC Arc
h
itecture for
Re
al-Time
Noise C
ancellati
on Sys
t
em Usi
n
g
V
a
ri
able
Speech P
D
F… (Trio A
d
iono)
1
339
3
.
SYSTEM
-ON-
CHIP A
R
C
H
ITEC
TURE
Based
on
Va
riable Speech PDF
noise
canc
e
llation m
e
thod,
we ca
n
dra
w
the
propose
d system
block
d
i
agram
as illu
strated
i
n
Fi
g
u
re
3
.
Sin
c
e th
e
n
o
i
se can
cel
ati
o
n pro
cessing
i
s
carried ou
t in frequ
en
cy domain
,
t
h
e 64
p
o
i
n
t
s
FFT/
I
F
F
T i
s
u
s
ed t
o
co
n
v
ert
audi
o si
gnal
i
n
t
o
f
r
eq
ue
ncy
dom
ai
n. B
e
fo
r
e
han
d
, t
h
e
ha
nni
ng
filter is u
tilize
d
to
refi
n
e
th
e
FFT inp
u
t
signal. Non
-
sp
eech au
d
i
o
si
g
n
a
l is assu
m
e
d
to
b
e
in
first 4
frames o
f
th
e inp
u
t
sign
al (
ϰ
(
n
,
l
)). Th
e
first
4
fram
es of th
e inp
u
t
signal w
ill
b
e
p
r
o
c
essed
b
y
h
a
lf ov
erlap
p
i
n
g
, h
a
n
n
i
n
g
filter, FFT,
n
o
ise sp
ectral esti
m
a
to
r,
and
IFFT.
After the first
4
frames, no
ise esti
mato
r will g
e
n
e
rate
an
avera
g
e
d
estimated noise spec
tra. The
proces
s that occurs in the next
f
r
am
e i
s
hal
f
ove
rl
ap
pi
n
g
, T
h
e Ha
n
n
i
n
g
filter, FFT
, Va
riable S
p
eech
PDF m
e
thod a
s
noise suppre
s
s
or, and
IFFT
.
In t
h
e propose
d system
, we use hal
f
o
v
e
rlap
m
e
th
od
,
h
e
n
ce th
e
first 3
2
sam
p
les o
f
th
e
ou
tpu
t
sig
n
a
l is co
m
b
ined
with
th
e last
3
2
sam
p
les fro
m
th
e
pre
v
i
o
us
fram
e
. T
h
ere
f
o
r
e t
h
e
o
u
t
p
ut
si
g
n
al
i
s
ge
nerat
e
d a
n
d
has c
o
r
r
el
at
i
o
n
wi
t
h
t
h
e
nei
g
h
b
o
ri
ng
f
r
am
es.
In
o
r
d
e
r to ach
iev
e
real-ti
m
e p
e
rforman
ce wh
ile
m
a
in
tain
in
g th
e flex
ib
ility o
f
syste
m
i
m
p
l
e
m
en
tatio
n
,
th
e
n
o
i
se can
celatio
n
system is p
a
rtiti
o
n
e
d
in
to
h
a
rd
ware an
d
so
ft
ware
[10
]
. Th
e
p
a
rtitio
n
i
ng
i
s
based
on
pr
ocessi
n
g
t
i
m
e
of t
a
s
k
s i
n
v
o
l
v
ed i
n
t
h
e sy
st
e
m
. The pr
oces
si
ng t
i
m
e
i
s
ob
t
a
i
n
ed by
p
r
ofi
l
i
ng o
f
each tas
k
using syste
m
sim
u
la
tion
m
odels as
shown in Ta
ble 2.
Fi
gu
re 3.
Pr
o
p
o
se
d
system
srchitecture
Tab
l
e 2
.
Pro
f
ilin
g
calcu
lation
resu
lt
T
a
sk
Pr
ocessing T
i
m
e
(m
s
)
Per
centage
Noise Sam
p
ling (D)
0.
0175
0.
0139%
Noise Cancellation (
N
)
0.
0296
0.
0235%
FFT +
Hanning Filte
r 63.10
49.9847%
I
FFT 63.
09
49.
977
9%
(a) SoC
arc
h
itecture
(b
) Tim
i
ng dia
g
ram
Fi
gu
re
4.
The
SoC
a
r
chi
t
ect
u
r
e (a
) a
n
d t
h
e
t
i
m
i
ng di
a
g
ram
(b
)
of
t
o
p-l
e
vel
sy
st
em
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE
Vol. 5, No. 6, D
ecem
ber
2015 :
1336 –
1346
1
340
Tab
l
e
2
sho
w
s th
at th
e FFT/IFFT and
Hannin
g
Filter
h
a
v
e
th
e l
o
ng
est
pro
cessing ti
m
e
co
m
p
ared
t
o
o
t
h
e
r task
s. The FFT/IFFT and
H
a
n
n
i
n
g
Filter p
r
o
cess are
alw
a
ys ex
ecu
t
e
d
du
e to
conversion
b
e
t
w
een ti
me
an
d frequ
e
n
c
y do
m
a
in
in
no
ise can
cellatio
n algo
r
ith
m
.
Mo
reov
er, th
e FFT/
IFFT and
Hann
ing Filter
com
put
at
i
on c
onsi
s
t
o
f
si
m
p
le and re
g
u
l
a
r s
t
ruct
u
r
es t
h
at
are sui
t
a
bl
e f
o
r
har
d
ware i
m
plem
ent
a
t
i
on. O
n
t
h
e
cont
rary
,
ot
he
r
pr
ocessi
n
g
i
n
vol
ves com
p
l
e
x an
d i
r
r
e
g
u
l
a
r o
p
erat
i
o
ns,
s
u
ch as
di
vi
si
o
n
s, e
x
p
o
n
ent
i
a
l
s
, and
lo
g
a
rith
m
s
th
at
are su
itab
l
e fo
r so
ft
ware imp
l
em
en
tati
on. B
a
sed o
n
t
h
o
s
e consi
d
erat
i
o
ns, t
h
e F
F
T/
IF
FT an
d
Hanning
Filter are im
plem
en
ted in
hardware as acceler
ator m
odules.
On the ot
her ha
nd, t
h
e noise s
p
ectrum
esti
m
a
t
i
o
n
and n
o
i
se can
cellatio
n
are im
p
l
e
m
en
ted
in
soft
ware. In
add
itio
n, th
e h
a
rd
ware software app
r
o
a
ch
h
a
s th
e flex
ib
ility th
at a
llo
ws fu
ture system p
e
rform
a
n
ce i
m
p
r
o
v
e
m
e
n
t
b
y
in
tro
d
u
c
ing
m
o
re ad
v
a
n
c
ed
no
ise
cancelation algorithm
s
.
Th
e
pr
opo
sed
So
C ar
ch
itectu
r
e is
d
e
si
g
n
e
d u
s
i
n
g LEO
N
SPA
RC-V
8
32
-b
it pro
cessor
as a
h
o
st
process
o
r a
s
illustrated i
n
Figure
4(a
)
. T
h
e
host pr
oce
ssor c
o
m
m
unicates
with ot
her m
odules t
h
rough
AMBA
AHB/APB bu
s. Th
e no
ise can
celatio
n
tim
in
g
d
i
ag
ram
is ill
u
s
tr
ated in
Fi
gu
r
e
4(
b)
.
I
t
is sh
own
th
at
f
o
r
8
kH
z
sam
p
lin
g
au
d
i
o
frequ
e
n
c
y, th
e av
ailab
l
e ti
me to
p
r
o
cess th
e aud
i
o
strea
m
in
g
d
a
ta from Han
n
i
n
g
Filter to
IFFT
is
4 m
s
.
3.
1. Th
e In
put Buffer,
Outp
ut Bu
ffer
,
and
Wind
ow Filte
r
Module
In
ou
r p
r
op
ose
d
desi
gn
, b
u
ffe
rs are
neede
d
i
n
i
n
put
a
nd
o
u
t
put
si
de
, t
o
b
r
i
dge t
h
e
ga
p b
e
t
w
een t
h
e
l
o
w cl
ock
fre
q
u
ency
of
au
di
o
C
odec
m
odul
e
,
an
d
hi
g
h
cl
oc
k f
r
e
que
ncy
o
f
t
h
e p
r
ocess
o
r.
There
are t
w
o
ki
n
d
s
of
buffe
rs
nee
d
to be desi
gned: a buffer to receive
the input
data from
the A
udi
o Codec (input buffe
r) a
nd
bu
ffe
r t
o
se
nd
t
h
e
pr
ocesse
d
d
a
t
a
t
o
t
h
e
A
u
di
o C
odec
(
out
p
u
t
b
u
ffe
r).
The FF
T m
odule re
quire
s 64 input data tha
t
is sent
serially. Because the
clock
fre
que
ncy of a
udi
o
C
odec i
s
m
u
ch
sl
owe
r
t
h
a
n
t
h
e p
r
ocess
o
r,
t
h
e i
n
put
dat
a
need
s t
o
be
bu
ffe
red
be
fo
re i
t
i
s
sent
i
n
t
o
t
h
e FF
T
m
odule. It utilizes three 32
words
RAM with
16-bit widt
h ports to im
plem
ent
dual cloc
k buffer
function. The
main
id
ea o
f
this b
u
f
fer is to
co
n
tinuo
usly sen
d
6
4
word
s of d
a
ta wh
ile receiv
in
g
32
wo
rds o
f
n
e
w
d
a
ta fro
m
audi
o C
odec
.
The com
put
at
i
on re
sul
t
of I
F
FT pr
ocess wi
l
l
be sent
back
t
o
audi
o C
o
d
ec. The o
u
t
p
ut
buf
fer
s
are
neede
d
t
o
com
b
i
n
e
hal
f
-
o
verl
appe
d
dat
a
i
n
t
o
seri
al
o
u
t
p
ut
dat
a
. T
h
e o
u
t
p
ut
b
u
f
f
ers c
o
ns
i
s
t
of t
h
ree 3
2
wo
rd
s
R
A
M
,
t
w
o R
A
M
s
wi
t
h
di
f
f
ere
n
t
dual
cl
ock a
nd
one
R
A
M
(cal
l
e
d R
A
M
t
a
i
l
)
as FIFO
del
a
y
bl
oc
k t
o
im
pl
em
ent
hal
f
o
v
erl
a
p m
e
t
hod.
W
i
nd
owing
Filter and
th
e half ov
erlap
op
eration
s
are u
s
ed
to
allev
i
ate d
i
scon
tinuities at th
e
end
p
o
i
n
t
s
o
f
e
ach o
u
t
p
ut
bl
o
c
k an
d i
n
c
r
eas
e rel
a
t
i
ons
hi
p
bet
w
ee
n f
r
am
es [1
1]
. I
n
t
h
i
s
pr
op
ose
d
de
s
i
gn,
h
a
nn
ing
w
i
ndow
is u
s
ed
. Th
e h
a
nn
ing
w
i
ndow
is
sp
ecif
i
ed
as:
(
7
)
3.2. FFT/IFF
T
Module
The F
F
T/
IF
FT
m
odul
e i
s
de
si
gne
d
usi
n
g a
radi
x
2
2
wi
t
h
si
ngl
e
-
pat
h
d
e
l
a
y
feedback architecture.
R
a
di
x 2
2
i
s
an
al
t
e
rnat
i
v
e fo
r
m
of radi
x
-
4.
R
a
di
x-
4 i
s
ch
o
s
en beca
use o
f
l
e
ss nont
ri
vi
al
ope
rat
i
on i
n
c
ont
rast
w
ith
rad
i
x-2
,
b
u
t
t
h
e bu
tterfly stru
cture i
s
still si
m
p
le
en
ough
to
be i
m
p
l
e
m
en
te
d
in
h
a
rdw
a
re [12
]
.
Co
m
p
ariso
n
of n
o
n
-
t
r
iv
ial op
eration
i
n
v
a
riou
s
FFT
al
go
r
ith
m
s
is show
n in Ta
b
l
e 3, wh
ile th
e
b
u
tterfly
st
ruct
u
r
e i
s
des
c
ri
be
d i
n
Fi
g
u
r
e
5
(
a) a
n
d
5(
b)
.
Tab
l
e
3
.
Th
e ad
d
ition
an
d m
u
ltip
licatio
n
o
f
real n
o
n
t
ri
v
i
al op
erand
in v
a
riou
s
DFT N-po
int co
m
p
u
t
atio
n
N
Real Multiplicatio
ns
Real Additions
Radix-2 Radix-4 Ra
dix-8 Split
Radix
Radix-2
Ra
dix-4 Radix-8
Split
Radix
16
24
20
20
152
148
148
32
88
68
408
388
64
264
208
204
196
1032
976
972
964
128
712
516
2504
2308
256
1800
1392
1284
5896
5488
5380
512
4360
3204
3076
1356
6
1242
0
1229
2
1024
1024
8
7856
7172
3072
8
2833
6
2765
2
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
SoC Arc
h
itecture for
Re
al-Time
Noise C
ancellati
on Sys
t
em Usi
n
g
V
a
ri
able
Speech P
D
F… (Trio A
d
iono)
1
341
(a)
(b
)
Fig
u
r
e
5
.
Bu
tter
f
l
y stru
ctur
e
of
r
a
d
i
x 22
The Single-path Delay Feedback (S
DF) arc
h
itecture is us
ed in th
e propose
d syste
m
b
ecause it has
less
m
u
ltip
lier, less
m
e
m
o
ry
b
its, easier butterfly stru
ctu
r
e co
n
t
ro
l, and n
o
ord
e
ri
n
g
i
n
in
pu
t sign
al. Th
e
com
p
ari
s
on
o
f
R
2
2
S
D
F
wi
t
h
ot
her a
r
c
h
i
t
ect
ure i
s
s
h
o
w
n i
n
Ta
bl
e 4. T
h
e R
2
2
SDF arc
h
itecture
can
be
descri
bed i
n
F
i
gu
re 6. Si
nce
t
h
e FFT p
r
oc
essi
ng i
s
car
ri
ed o
u
t
i
n
ha
rd
ware a
nd t
o
o
p
t
i
m
i
ze t
h
e uti
l
i
zed
h
a
rdware
resou
r
ces, th
e
d
a
ta sig
n
a
l sh
ou
ld
be represen
te
d
i
n
fix
e
d-po
in
t
nu
m
b
er with
a limited
b
it wid
t
h. Th
e
det
e
rm
i
n
at
i
on of
bi
t
wi
dt
h i
s
per
f
o
r
m
e
d b
y
usi
ng si
m
u
l
a
t
i
on o
f
bi
t
p
r
eci
si
on FF
T
m
odel
.
B
a
sed on t
h
e
si
m
u
latio
n
resu
lts, th
e d
i
sto
r
t
i
o
n
of sp
eech
is d
i
fficu
lt to
b
e
reco
gn
ized
when
th
e u
tilized
b
it wid
t
h
in
mo
d
e
l is
1
0
b
it
fraction
a
l. Thu
s
, we use th
e
n
u
m
b
e
r
form
at o
f
Q1
.1
0
(1 b
it sign
ed
,
1 b
it in
teger, and
1
0
b
it
fraction
a
l).
Tab
l
e
4
.
Th
e co
m
p
ariso
n
of
resou
r
ce
u
tilizatio
n
i
n
v
a
ri
o
u
s
FFT
arch
itectures
Architecture
# Multiplier
# Adder
Me
m
o
ry Size
Control
Signal
R2MDC 2(log
4
N
– 1)
4 log
4
N
3
N
=2 – 2
sim
p
le
R2SDF 2(log
4
N
– 1)
4 log
4
N
N
– 1
sim
p
le
R4SDF log
4
N
– 1
8 log
4
N
N
– 1
m
e
diu
m
R4MDC 3(log
4
N
– 1)
8 log
4
N
5
N
=2 – 4
sim
p
le
R4SDC log
4
N
– 1
3 log
4
N
2
N
– 2
co
m
p
lex
R22SDF log
4
N
– 1
4 log
4
N
N
– 1
sim
p
le
Fi
gu
re
6.
The
R
22S
DF
6
4
-
p
o
i
nt
FFT
arc
h
i
t
ect
ure
Usi
n
g t
h
e
Q
1
.
1
0
f
o
rm
at
, t
h
e o
b
t
a
i
n
ed
PS
N
R
bet
w
ee
n i
n
p
u
t
an
d
out
put
si
gnal
i
s
77
.0
8
dB
. T
h
e
bi
t
width of signal
m
u
st be
m
odified be
fore e
n
tering
FFT/
I
FF
T
m
odule to
pre
v
ent
ov
erflow whe
n
doi
ng
addition
or m
u
ltiplication in each sta
g
e of F
F
T. The broa
de
ning of
bit width is adjuste
d
with am
ount of stage
,
henc
e
the num
b
er format used is
Q7.10.
3.3.
The AHB
-
connecte
d
Modules
The m
odul
es
whi
c
h are
di
re
ct
l
y
connect
e
d
t
o
t
h
e
A
H
B
b
u
s a
r
e A
H
B
R
A
M
i
n
put
a
n
d
DM
A
o
u
t
p
ut
.
The
A
H
B
R
A
M
i
n
p
u
t
has
1
2
8
wo
r
d
s
de
pt
h,
32
-
b
i
t
wi
de
, a
n
d a
n
i
n
t
e
rface
t
o
t
h
e
AHB
b
u
s
as
AHB
sl
ave
.
The
RAM has s
u
ch specification
because in the
fre
que
ncy domain
, the system has 128 data t
h
at consist of
64
rea
l
dat
a
an
d
64 i
m
agi
n
ary
dat
a
,
wh
ose
wi
dt
h
of t
h
e dat
a
fol
l
ows t
h
e wi
dt
h
of t
h
e A
H
B
bus
. T
h
e
AHB
R
A
M
m
odules play
a role to buffe
r FFT out
put da
ta before accessed by
the host proce
ssor.
W
i
th the help of AHB
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE
Vol. 5, No. 6, D
ecem
ber
2015 :
1336 –
1346
1
342
RAM
m
odule
,
the host
proc
essor ca
n easily access the
FFT output dat
a
by accessing a
m
e
m
o
ry address
mapped
by the AHB inte
rfa
ce. T
h
e
host
proces
sors
sta
r
t accessing R
A
M imm
e
diately after
receivi
ng an
in
terru
p
t
sign
al fro
m
AHB R
A
M,
as illu
strated
in
Figu
re 7.
(a) I
n
p
u
t pr
oce
ss
(b
)
T
r
an
sfe
r
pr
ocess
Fi
gu
re 7.
The
AHB
b
u
f
f
er
i
n
put
p
r
oces
s
a
n
d DM
A
t
r
ans
f
e
r
pr
ocess
In
t
h
e
ne
xt
st
e
p
, t
h
e
ho
st
p
r
ocess
o
r
pe
rf
or
m
s
si
gnal
pr
oc
essi
ng
i
n
t
h
e
f
r
eq
ue
ncy
d
o
m
a
i
n
.
Once
a
p
r
o
cesso
r
fin
i
sh
ed
t
h
e d
a
ta
pro
cessing
, th
e
p
r
o
cesso
r
will te
m
p
o
r
arily sto
r
e th
e
d
a
ta in th
e SDR
A
M at th
e
st
at
i
c
address s
p
eci
fi
ed i
n
t
h
e
soft
ware
. The
speci
al
pu
r
pos
e DM
A i
s
desi
gne
d i
n
or
der t
o
be a
b
l
e
t
o
pe
rf
orm
hi
g
h
sp
eed
b
u
r
st
dat
a
t
r
a
n
sf
er fr
om
SDR
A
M
m
e
m
o
ry
to t
h
e
out
put
b
u
f
f
er a
n
d f
r
o
m
i
nput
b
u
ffe
r t
o
t
h
e
SDRAM as illustrated i
n
Figure
7(b)
. The
DMA m
odule
acts as an AHB Mast
er that has privilege a
ccess to
th
e SDRAM,
with
ou
t th
e help
o
f
th
e
ho
st pro
cesso
r.
Th
e ou
tpu
t
buf
f
e
r
con
s
ists of
du
al 6
4
-
w
ord
s
RA
M. Th
e RA
M b
u
f
f
e
r
ou
tpu
t
is co
nn
ected
as A
P
B
Slave, which
receives the re
ad data and transm
it DM
A interrupt enabl
e
. The DM
A process is carried out
th
ro
ugh
a
seri
es of task
s. After t
h
e
p
r
o
cesso
r p
e
rfor
m
s
writing
d
a
ta t
o
SDR
A
M,
p
r
o
cesso
rs g
i
v
e
s en
ab
le
signal through
APB, which tri
gge
rs DM
A to start work
ing.
After ac
qui
ring and
locki
ng
access from
the AHB
arb
iter, DM
A starts to
read
d
a
ta fro
m
SDRAM an
d
t
h
e d
a
ta is sto
r
ed
in
t
h
e RAM ou
tpu
t
bu
ffer. After
read
ing
all d
a
ta in on
e
fram
e
, th
e i
n
terru
p
t
sign
al is
sen
t
to th
e processor to ind
i
cate th
e
d
a
ta
b
e
g
i
n
s
to b
e
pro
c
essed at
t
h
e IFFT m
o
d
u
l
e
. The
bu
ffe
r uses
dual
R
A
M
beca
use i
n
t
h
e IF
FT m
o
d
u
l
e
, t
h
e real
and i
m
agi
n
ary
i
nput
s
sho
u
l
d
be
p
r
o
v
i
d
e
d
si
m
u
l
t
a
neou
sl
y
.
I
n
a
d
d
i
t
i
on, t
h
e
ena
b
l
e
si
gnal
i
s
di
s
a
bl
ed t
o
di
sm
iss an
d
rel
ease
DM
A
access to
SDR
A
M to
wait for the
next
fram
e
.
3.4. The Software
Design
The f
r
e
que
ncy
dom
ai
n si
gn
al
pr
ocessi
n
g
i
n
si
de
pr
ocess
o
r i
s
do
ne
by
usi
n
g C
-
base
d s
o
ft
wa
re
p
r
og
ram
.
In
the p
r
op
o
s
ed
SoC h
o
s
t
p
t
o
cesso
r, th
e arith
m
e
tic o
p
e
ration
s
can
use bo
th fi
x
e
d
po
in
t arit
hmetics
an
d
flo
a
ting
poin
t
u
n
it GRFPU-Lite cop
r
o
c
esso
r. Th
e
u
tilizatio
n
of co-processor d
e
p
e
nd
s o
n
th
e co
m
p
u
t
atio
n
com
p
l
e
xi
t
y
. The com
p
l
e
x o
p
erat
i
o
n s
u
ch
as di
vi
si
o
n
a
n
d sq
ua
re r
oot
app
r
oxi
m
a
t
i
on are com
put
ed
usi
n
g
flo
a
ting
po
in
t co
pro
cesso
r.
On th
e o
t
h
e
r
h
a
nd, sim
p
le o
p
e
ratio
n
su
ch
as add
itio
n
an
d
m
u
ltip
licatio
n
is don
e in
fi
xe
d
poi
nt
ari
t
hm
ati
c
s.
Whe
n
usi
n
g
fi
xed
p
o
i
n
t
,
s
o
m
e
app
r
o
x
i
m
at
i
on m
u
st
be
do
ne t
o
gi
ve
sim
i
l
a
r resul
t
com
p
ared t
o
fl
oat
i
n
g
poi
nt
ope
rat
i
o
n,
fo
r
exam
pl
e i
n
t
h
e l
oga
ri
t
h
m
i
c
ope
rat
i
o
n.
In
o
r
de
r t
o
eval
uat
e
t
h
e l
o
gari
t
h
m
of a
fi
xe
d p
o
i
n
t
n
u
m
ber,
ϰ
,
we fi
rstly d
i
v
i
d
e
d
it in
to
m
a
n
tissa,
m
, and
expon
en
t,
e
, th
at is si
milar to
flo
a
ting
-
po
in
t
represen
tatio
n
as:
(
8
)
The l
oga
ri
t
h
m
i
c val
u
e
o
f
ϰ
ca
n
be e
x
p
r
esse
d
i
n
t
e
rm
s of
m
an
d
e
as
[
13]
:
(
9
)
The ex
p
one
nt
i
s
a si
gne
d i
n
t
e
ger a
nd i
t
i
s
ex
act
l
y
t
h
e i
n
t
e
ger pa
rt
of
y
. Sin
ce th
e ex
pon
en
t is to
b
a
se
2,
m
is a
fix
e
d-po
in
t
v
a
lu
e i
n
th
e rang
e of [1
:0
;
2
:
0
)
. Th
en, its lo
g
a
rith
m
i
c v
a
lu
e is i
n
the rang
e
o
f
[0
:0; 1
:
0
)
,
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
SoC Arc
h
itecture for
Re
al-Time
Noise C
ancellati
on Sys
t
em Usi
n
g
V
a
ri
able
Speech P
D
F… (Trio A
d
iono)
1
343
i
.
e.,
t
h
e fract
i
onal
part
of
υ
. Th
e
fin
a
l log
a
rith
m
i
c o
u
t
pu
t is si
m
p
ly t
h
e su
m
o
f
th
e in
teg
e
r
p
a
rt an
d
t
h
e
fraction
a
l p
a
rt.
Sin
ce th
e lo
g
a
rith
m
i
c v
a
lu
e o
f
mis a
l
ways in
t
h
e rang
e of [0
:0
; 1
:
0
)
, lo
g
2
m
can be ex
pre
s
s
e
d i
n
bi
na
ry
fo
rm
at as:
(
1
0
)
Whe
r
e
b
–
i
=
f0; 1
g
fo
r all in
teg
e
r i >
0
.
Th
e
weigh
tin
g of each
b
it
b
–
i
is
2–
i
. Math
em
atic
ally, th
e b
i
n
a
ry
v
a
lu
e
can
be e
x
p
r
ess
e
d
by
t
h
e e
q
uat
i
on a
s
f
o
l
l
o
ws:
(
1
1
)
Tak
i
ng
t
h
e an
ti-log
a
rith
m
,
we
h
a
v
e
:
(
1
2
)
Th
e al
g
o
rith
m
is to
fi
n
d
ou
t the b
its,
b
–
i
,
by
i
t
e
rat
i
ons
st
art
i
n
g
fr
om
b
–
1
, t
h
e
n
b
–
2
and
so
on
.
Fi
xed
p
o
i
n
t
co
m
put
at
i
on has
l
e
ss com
put
i
ng t
i
m
e
i
n
add,
subt
ract
, an
d
m
u
lt
i
p
l
y
opera
t
i
on,
whi
l
e
GR
FP
U Li
t
e
has l
e
ss com
put
i
ng t
i
m
e i
n
di
vi
de a
n
d sq
uare
ro
ot
o
p
er
at
i
on. T
h
ere
f
o
r
e, i
n
or
der t
o
red
u
c
e
pr
ocessi
ng
t
i
m
e
i
n
so
ft
wa
re, t
h
e
pr
o
p
o
s
ed
de
si
gn
us
es
hy
b
r
i
d
m
ode.
T
h
e
p
r
o
p
o
sed
desi
g
n
feat
u
r
es
fi
xe
d
poi
nt
m
e
thod i
n
add, subtract, m
u
ltiply, and l
oga
rithm
i
c opera
tion, and
GRFP
U Lite in di
vi
de and s
q
uare
root
ope
rat
i
o
n.
4
.
IM
PLEM
EN
TA
TION
AN
D PER
F
ORM
ANC
E EVALU
A
T
ION
4.1. FPGA
Im
plementati
on
In o
r
der t
o
m
a
ke su
re t
h
at
t
h
e pro
p
o
se
d n
o
i
se cancel
l
a
t
i
on sy
st
em
can
be im
pl
em
ent
e
d i
n
FP
GA
Altera
DE2-7
0
, co
m
p
ilatio
n
an
d v
e
rification are
p
e
rfo
rm
ed. T
h
e system
im
ple
m
entation on FPGA is c
a
rrie
d
o
u
t
i
n
sev
e
ral
step
s. Th
e aud
i
o cod
ec setting
s
u
s
ed
in
FPGA are 1
6
-b
it wid
t
h
ADC,
8
kHz sam
p
lin
g
p
e
ri
od
. In
the first test, we still only used bypa
ssing with no algori
thm
used. T
h
is
is done to te
st system
capability
whet
her it can
be by
passe
d
by an audio si
gnal in a
real
-t
i
m
e
m
a
nner wi
t
h
a cert
a
i
n
sam
p
l
i
ng
rat
e
an
d
obs
er
ve
whet
her si
gni
f
i
cant
di
st
ort
i
o
n ap
pear
s o
r
n
o
t
.
The a
u
di
o
codec i
n
p
u
t
i
s
t
a
ken f
r
om
t
h
e M
I
C
chan
ne
l
,
wi
t
h
bypass
from
LINE IN and MIC SIDET
ONE
is
deact
ivated. Tools
arra
ngem
ent use
d
i
n
the
syste
m
im
pl
em
ent
a
t
i
o
n i
s
s
h
ow
n i
n
F
i
gu
re
8.
Fi
gu
re
8.
To
ol
s
arra
n
g
em
ent
The
out
put
wa
vef
o
rm
fr
om
FPG
A
rec
o
r
d
e
d
on t
h
e
Au
daci
t
y
soft
wa
re as
wel
l
as t
h
e i
n
p
u
t
wa
vef
o
rm
can be c
o
m
p
ar
ed. T
h
e si
g
n
al
reco
rde
d
fr
om
FPG
A are
by
p
a
ssi
ng a
u
di
o c
odec
si
g
n
al
, by
passi
n
g
i
n
p
u
t
-
out
put
bu
ffe
r si
gnal
,
b
y
p
assi
n
g
F
F
T-
I
FFT si
gnal
,
an
d
by
passi
ng
L
E
ON
si
g
n
al
.
T
h
e
resul
t
i
s
s
h
o
w
n
i
n
Fi
g
u
re
9
.
Qu
alitativ
ely, th
ere are still small o
b
s
erv
a
b
l
e d
i
strac
tion
in sp
eech
sign
al. Th
is
o
ccurs
du
e to
t
h
e
u
s
e
of noisy signal
source or
noi
sy audio recei
ver cha
n
nel.
T
h
e ne
xt test, we load th
e processor with Variable
Speec
h P
D
F
al
go
ri
t
h
m
.
The t
e
st
i
ng
of
n
o
i
s
e
cancel
i
n
g al
g
o
r
i
t
h
m
on F
P
G
A
i
s
do
ne i
n
se
veral
way
s
,
usi
n
g
f
u
l
l
fix
e
d
p
o
i
n
t
, fu
l
l
FPU u
tilizatio
n, an
d h
y
b
r
i
d
ap
pro
ach to
com
p
are p
r
o
cessi
n
g
un
it p
e
rforman
ce and
time u
s
i
n
g
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE
Vol. 5, No. 6, D
ecem
ber
2015 :
1336 –
1346
1
344
the algorithm
.
The
perform
a
nce is
m
easured
by
su
bject
i
v
e l
i
s
t
e
ni
ng t
e
st
an
d usi
ng t
i
m
est
a
m
p
s. The res
u
l
t
s
are
sho
w
n i
n
Ta
bl
e 5.
Fig
u
re
9
.
Co
mp
ariso
n
of i
n
put an
d ou
tpu
t
si
g
n
a
l
fro
m
FPGA
with
ou
t
n
o
i
se can
cellatio
n (fro
m
to
p
to
bo
tto
m:
Bypass Codec, Bypass B
u
ffer & C
o
nverte
r,
Bypass FF
T-IF
FT, Bypa
ss LE
ON, Clear
Spe
ech)
Tabl
e
5.
Pr
oce
ssi
ng
t
i
m
e
usi
n
g
di
ffe
re
nt
co
m
put
at
i
on t
ech
ni
q
u
es
Co
m
putation T
ech
nique
Pr
ocessing T
i
m
e
(m
s
)
Relative T
i
m
e
Decr
ease
Fixed Point
3400
1.
000
Floating Point
>4000
not feasible in r
eal-
t
im
e)
Hy
br
id
1600
2.
125
Tabl
e 5 s
h
ows
t
h
at
t
h
e fre
qu
ency
d
o
m
a
i
n
pr
ocessi
ng i
s
f
a
st
est
whe
n
us
i
ng
bot
h FP
U
and
A
L
U
fun
c
tion
,
wh
ile th
e
d
i
fferen
ces in
qu
ality is uno
b
s
erv
a
b
l
e b
y
h
u
m
an
ears. It is also sho
w
n
t
h
at th
e
Hyb
r
i
d
fl
oat
i
n
g p
o
i
n
t
and
fi
xe
d
p
o
i
n
t
com
put
at
i
on m
e
t
hod s
i
gni
fi
ca
nt
l
y
reduce
d
t
h
e
p
r
ocessi
n
g
t
i
m
e whi
l
e
main
tain
in
g
si
g
n
a
l
qu
ality. Th
e si
g
n
a
l
qu
ality o
u
t
p
u
t
of syste
m
is sh
own in
Fi
g
u
re
10
.
Fi
gu
re
1
0
. C
o
m
p
ari
s
on
of
i
n
put
(B
y
p
ass
C
odec
)
a
n
d
out
p
u
t
si
g
n
al
(
A
ft
er
M
A
P M
e
t
h
o
d
)
.
Fr
om
t
op t
o
b
o
t
t
o
m
:
Noise
Only 10
dB, Speec
h +
Nois
e
10 dB, Speech
+ Noise
0 dB
4.
2. Perf
orm
a
nce
E
v
al
u
a
ti
o
n
Th
e m
easu
r
emen
t of
p
e
rfo
r
m
a
n
ces, su
ch
as
resource
u
tiliz
atio
n
o
f
log
i
c ele
m
en
ts, m
e
mo
ry
b
its, and
m
u
lt
i
p
l
i
e
rs, and m
a
xim
u
m
wo
rki
n
g fre
qu
ency
can be o
b
t
a
i
n
ed i
n
t
h
e
repo
rt
of d
e
s
i
gn com
p
i
l
a
t
i
on. Th
e
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
An
SoC Arc
h
itecture for
Re
al-Time
Noise C
ancellati
on Sys
t
em Usi
n
g
V
a
ri
able
Speech P
D
F… (Trio A
d
iono)
1
345
l
a
t
e
ncy
i
s
obt
a
i
ned
by
di
vi
di
ng
t
h
e am
ou
nt
of
re
qui
red
cy
cl
es fo
r
pr
oces
si
ng
o
f
o
n
e
fra
m
e
usi
n
g
m
a
xim
u
m
fre
que
ncy
.
T
h
e
am
ount
o
f
cy
cl
es can be cal
cul
a
t
e
d by
o
b
ser
v
i
n
g t
i
m
i
ng i
n
R
TL sim
u
l
a
t
o
r. The o
v
eral
l
s
y
st
em
per
f
o
r
m
a
nce i
s
sh
ow
n i
n
Ta
bl
e 6.
Table 6. Param
e
ters
of overall
syste
m
performance
Co
m
ponents Am
ount
T
o
tal L
ogic Elem
e
n
ts (
T
LE
)
18,
500
Co
m
b
inational Fu
nctions
17,
050
Register
s 5,
152
M
e
m
o
ry
Bits
181,
23
2
E
m
bedded Multipl
i
ers
26
Fm
ax
59.
48
M
H
z
Beside the
ove
r
all syste
m
, we also a
n
alyze the
pe
rform
a
nce of each bl
ocks.
The
detailed re
source
utilization, s
u
c
h
as
LEs a
n
d
m
e
m
o
ry bits
, on eac
h m
odule
is shown i
n
Ta
ble 7.
Table 7.
Resource utili
zation of each bl
ok
Block
TLE
Me
m
o
ry
Bi
ts
L
E
ON3
Pr
ocessor 11,
565
(
62.
5%)
145,
66
4
FFT
/I
FFT 1,
708
(
9
.
23%)
4,
464
Hanning W
i
ndow
54 (
0
.
29%)
0
AHB RAM
I
nput
143 (
0
.
77%)
4,
096
DM
A Output
238
(
1
.
28%)
2,
304
I
nput Buf
f
er
s
98 (
0
.
529%)
1,
152
Output Buf
f
er
s
94 (
0
.
508%)
1,
536
Audio Codec
442 (
2
.
38%)
5,
632
Othe
r m
odule
s
that
utilize rem
a
ining res
o
urces
are
clock ge
nerator, AHB
and
AP
B controller,
SDR
A
M
co
nt
r
o
l
l
e
r, t
i
m
er, D
e
bu
g
Su
p
p
o
r
t
Uni
t
,
a
n
d
UA
R
T
co
nt
r
o
l
l
e
r
fo
r
pr
o
g
ram
m
i
ng
p
u
r
p
o
se.
P
r
op
ose
d
FFT/
I
F
F
T m
odul
e per
f
o
r
m
a
nce i
s
al
so co
m
p
ared t
o
ot
her F
F
T bl
oc
ks f
r
o
m
Quart
u
s M
e
gaC
o
re f
unct
i
o
n. T
h
e
co
m
p
ariso
n
is
sh
own
on
Tab
l
e 8
.
Th
e Tab
l
e 8
shows th
at ou
r d
e
si
g
n
u
tiliz
es sign
ifican
tly less LEs co
m
p
ared
with
Qu
artu
s Meg
a
Core
IP.
Tab
l
e
8
.
C
o
m
p
arison
o
f
resource
u
tilizatio
n
o
n
v
a
riou
s
FFT b
l
o
c
k
s
Blocks
LEs
Multipliers
Me
m
o
ry
Our
custo
m
FFT
/
IFFT
1,
708
16
4,
464
FFT
fro
m
Quartus MegaCore
function
with 4
m
u
ltipliers
4,373 24
9,984
FFT
fro
m
Quartus MegaCore
function
with 3
m
u
ltipliers
4,915 18
9,984
5. CO
N
C
L
U
S
I
ON
The propose
d noise ca
ncellation S
o
C system
arch
itecture
using varia
b
l
e
speech P
D
F
m
e
thod is
desi
g
n
e
d
by
u
s
i
ng
har
d
ware
-so
f
t
w
a
r
e c
o
-
d
esi
gn a
p
pr
oac
h
. T
h
e t
i
m
e
dom
ai
n si
gnal
pr
ocessi
ng
s
u
ch a
s
Hann
ing
filter and
FFT/IFFT are im
p
l
e
m
en
ted
i
n
h
a
rd
ware t
o
sp
eed up
th
e
pro
c
essin
g
ti
m
e
, wh
ile th
e
f
r
e
q
u
e
n
c
y-do
main
sign
al pr
ocessin
g
, su
ch
as MAP estimatio
n
,
is im
p
l
emen
ted
in
so
ft
ware t
o
in
crease th
e
flexibility of future algorithm
update. T
h
e
desi
gn of
S
o
C which
base
d on the LE
ON proces
sor a
nd utilized
FPU c
o
pr
ocess
o
r
,
si
g
n
i
f
i
cant
l
y
im
prove
sy
st
em
perf
orm
a
nc
e. The
S
o
C
us
es cust
om
AM
B
A
bas
e
d
FFT
/
I
FFT
wi
t
h
R
2
2SD
F
archi
t
ect
u
r
e. T
h
e sy
st
em
ut
i
lizes 18
,5
0
0
l
o
g
i
c el
em
ent
s
, 181,
23
2 m
e
m
o
ry bi
t
s
, and ca
n be
r
u
n
in real-tim
e on 59.4
8 MHz
s
y
ste
m
clock. T
h
e SoC
has
be
en s
u
cces
s
f
ull
y
im
ple
m
ented and ca
n
run i
n
real-
t
i
m
e
on FP
G
A
Al
t
e
ra
DE2
-
70
usi
n
g
speec
h
s
i
g
n
a
l inpu
t su
bj
ected
with Gau
ssian no
ise.
REFERE
NC
ES
[1]
JS Lim,
AV Opp
e
nheim.
Enhancement and band
width compression of noisy speech
. Proceedings
of the I
EEE. 197
9;
67(12): 1586-16
04.
[2]
S Boll. Suppression of acousti
c n
o
ise in speech u
s
ing spectral sub
t
rac
tion.
I
EEE T
r
ansactions on Acousti
cs, Spee
c
h
and Signal Processing
. 1979; 27
(2): 113–120.
[3]
AR Fukane, SL
Sahare.
Differ
e
n
t
appro
ach
es of s
p
ectr
a
l subtr
a
ction me
thod for
enhancing
the speech sign
al in no
is
y
environments.
In
ternational Jour
nal of Scie
ntific &
E
ngineering Research
. 1997;
2(5).
Evaluation Warning : The document was created with Spire.PDF for Python.