Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
Vol
.
4
,
No
. 5, Oct
o
ber
2
0
1
4
,
pp
. 64
8~
65
7
I
S
SN
: 208
8-8
7
0
8
6
48
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Digit
a
l E
n
coder Desi
gning
for Mobile Robot Control
Alirez
a
Rez
a
e
e
*, Rez
a
Afs
h
ar*
*
*Depar
tm
ent of system
and
M
echatr
o
nics E
ngineer
ing,
Faculty
of
New Sciences and T
echnologies,
Univer
sity
of T
e
hr
an,
T
e
hr
an, I
r
a
n,
a
rre
za
ee
@ut
.
a
c
.
i
r
** Depar
t
m
e
nt of
E
l
ectr
i
cal E
ngine
er
ing,
M
i
y
a
neh Br
anch,
I
s
lam
i
c Azad
Univer
sity
, M
i
y
a
n
e
h,
I
r
a
n
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
May 27, 2014
Rev
i
sed
Sep 4, 20
14
Accepted
Sep 14, 2014
In this pap
e
r we present
the d
e
sign of
a quad
r
atu
r
e decode
r/counter interface
IC (ASIC) that performs the decoding,
coun
ting
,
and bus interface function
in digital motor control s
y
stems,
emplo
y
in
g an Altr
a FLEX 10KA,
2s150fg456 Xilinx device. The ASIC contai
ns a pair of digit
a
l fil
t
ers,
a
quadratur
e deco
der, an up/down counter
, a
latch and inhibit circu
it, and an 8-
bit bus interface to a digital pro
cessing s
y
stem. The design of digital of th
e
digita
l fi
lt
er is
based on
the
finit
e
sta
t
e
m
achin
e m
odel
with dat
a
pa
th
(FSMD). A nov
el scheme for detecting
th
e m
o
tor rotation dir
e
c
tion is als
o
proposed. Th
e
ASIC can be
applied
to
a dig
ital motor control s
y
stem
forgetting the ro
tation sp
eed or p
o
sition
of the motor, which
is quipped with
an opti
c
a
l
e
n
co
der.
The
dat
a
a
c
quisition
c
a
n b
e
ex
tended
to
1
6
-bit in
teg
e
r
format b
y
two
continuos readin
g cy
cl
es.
Simulation and e
xper
imental tests
are shown
to ver
i
f
y
th
e ASIC fun
c
tion
properly
.
Keyword:
C
ont
r
o
l
CPLD
Decode
r/count
er
Interface ic
Mo
to
r
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Alireza Rezaee
,
Depa
rt
m
e
nt
of
sy
st
em
and M
e
chat
r
oni
cs
En
g
i
neeri
n
g,
Fac
u
l
t
y
of
Ne
w sci
e
nces a
n
d t
ech
n
o
l
o
gi
es,
Uni
v
ersity of
Tehra
n
, Te
hra
n
,
Ira
n
Em
a
il: arrezaee@ut.ac
.
ir
1.
INTRODUCTION
In
hi
g
h
-
pe
rf
or
m
a
nce di
gi
t
a
l
m
o
t
o
r cont
rol
sy
st
em
s wi
t
h
wi
de s
p
ee
d c
o
nt
r
o
l
ra
nge
,cer
t
a
i
n
i
n
t
e
rfac
e
in
teg
r
ated
circu
it (ICs) are st
ill req
u
i
red thro
ugh
wh
ich
t
o
g
e
t t
h
e m
o
to
r
feedb
a
ck
p
o
s
it
io
n
or sp
eed
si
g
n
a
ls,
although se
nsorless control has got m
u
ch attention
recentl
y [1]. Tac
hom
eter
s, potenti
o
meters, resol
v
ers, a
n
o
p
tical en
cod
e
r, for g
e
tting
t
h
e m
o
to
r ro
tatio
n
ang
l
e or speed
. am
o
n
g
the
m
, th
e op
tical en
cod
e
r is th
e
m
o
st
comm
only used
because its output si
gnal is
digital with hi
gh
noise
imm
u
n
ity and
high
re
solution.
There
are t
h
ree types
of optical encoder C
o
mm
only used in m
o
tion control. They are
l
o
ck
wi
se/
c
o
unt
ercl
oc
kwi
s
e,
(
C
W
/
C
C
W
)
,
p
u
l
s
edi
r
ect
i
on (
pul
se/
D
IR
) a
n
d q
u
ad
rat
u
re (
A
/
B
phase
).
Am
ong
th
em
, th
e last on
e is t
h
e m
o
st p
opu
lar
b
ecau
s
e it can
p
r
od
u
c
e 4-ti
m
e
rate reso
lu
tion
.
Ov
er th
e
p
a
st two
d
ecad
e
s, mo
stly th
e d
i
g
ital
m
o
t
o
r co
nt
r
o
l
was d
o
n
e by
u
s
i
ng m
i
crop
roc
e
ssor
s
[
2
]
,
as sh
ow
n i
n
Fi
gu
re
1.
Som
e
int
e
rface
IC
s,
s
u
ch
as
HP
HC
TL2
00
0 a
n
d H
C
TL2
01
6,
f
o
r
qua
d
r
at
ure
dec
o
d
i
n
g
and c
o
u
n
t
i
n
g t
h
e o
u
t
p
ut
si
gn
al
of t
h
e
optical encoder are
also
available in comm
ercial
ar
k
e
ts [3
].
H
o
w
e
ver,
the construction of whole c
o
ntrol syst
e
m
is c
o
m
p
lex and the cost is not
cheap. Recently,
the progress i
n
VLSI
t
echn
o
l
o
gy
has
m
a
de possi
bl
e
t
h
e u
s
e o
f
c
o
m
p
l
e
x
pr
o
g
ram
m
abl
e
l
ogi
cde
v
i
ces (C
P
L
D
)
of
fi
el
d
pr
o
g
ra
m
m
a
bl
e
gat
e
d ar
ray
s
(
FPG
A) f
o
r t
h
e desi
gn
of di
gi
t
a
l
cont
r
o
l
l
e
r, i
n
t
e
rfa
ce IC
, or ot
her ap
p
l
i
cat
i
on-sp
eci
fi
c IC
s
(ASICs) in th
e sam
e
ch
ip
Alth
oug
h th
e
desi
gn of t
h
e
quadrature
decoder/
coun
ter in
terface IC i
n
Literatu
re i
s
not lacking [7], the work
was
done in
transi
stor level.In this paper, we
present the design
of inte
rface IC in
ate an
d
reg
i
ster lev
e
l, em
p
l
o
y
in
g
an
Altra FLEX
10
KA an
d
2
s
1
5
0
Xilinx
d
e
v
i
ce [8
]. Using
th
e sch
e
me, th
e
i
m
ple
m
entatio
n of the circuit is eas
ier than the pr
evi
o
us work. The
interface
IC can pe
rform
flitering,
q
u
a
dratu
r
e eco
d
i
n
g
,po
s
ition
i
n
g
cou
n
t
i
n
g
an
d
bu
s in
terfa
ce fun
c
tion
.
Si
m
u
la
tio
n
and
ex
p
e
rim
e
n
t
al t
e
sts are
sh
own
to
v
e
rify th
e fu
n
c
tion
o
f
th
e in
terface IC p
r
op
erly. Th
e circu
it can b
e
in
teg
r
ated
as a p
a
rt o
f
circu
it o
f
an a
ppl
i
cat
i
o
n-
speci
fi
c
di
gi
t
a
l
co
nt
r
o
l
IC
fo
r
m
o
ti
on c
ont
rol
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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088
-87
08
I
J
ECE Vo
l. 4
,
N
o
. 5
,
O
c
tob
e
r
20
14
:
648
–
6
57
64
9
Figu
re
1.
A
m
i
cro
p
r
o
cess
o
r-
b
a
sed m
o
tor c
o
n
t
rol sy
stem
.
2.
THE REQUIRED
FUNCTION
Figure
2 s
h
ows the system
func
tion
bl
ock
diagram
of the interf
ace IC
, which
has
an two-phas
e
interface to a
n
optical encoder and
an 8-bit interface to a standard m
i
c
r
oprocess
o
r or application-s
p
ecific
digital system
.
The
re
quired
functio
n
of the
interface IC
a
r
e
descri
bed a
s
follows.
Since m
a
ny
m
o
tors a
r
e
u
s
ually work
i
n
g
in no
isy env
i
ron
m
en
ts, wh
ich
m
i
g
h
t
in
trod
u
c
e unwan
ted no
ise in
t
h
e en
cod
e
r's o
upu
t
d
u
e
to
electro
m
a
g
n
e
tic co
up
lin
g
o
r
vib
r
ation
.
A p
a
ir o
f
d
i
g
ital filters, on
e fo
r th
e
ch
ann
e
l A and
th
e o
t
h
e
r on
e fo
r th
e
ch
ann
e
l B, are requ
ired
t
o
filter o
u
t
th
e
n
o
i
se o
n
th
e
incomin
g
sig
n
a
ls. A u
a
d
r
at
u
r
e
deco
d
e
r circu
it is also
requ
ired
t
o
d
e
co
d
e
th
e in
co
m
i
n
g
filtered
si
g
n
als fo
r
d
e
term
i
n
ing
t
h
e m
o
to
r ro
tatio
n d
i
rectio
n and
m
u
ltip
ly th
e
resol
u
t
i
o
n
o
f
t
h
e i
n
put
si
gnal
s
by
a fact
or
o
f
f
o
u
r
.
A
p
o
si
t
i
on c
out
e
r
i
s
t
h
en ne
ede
d
t
o
u
p
o
r
do
w
n
co
u
n
t
t
h
e
resulting dec
o
ded pulse
according
to
the rotation direction
i
ndication fr
om one
of the
de
c
ode
r outputs.
Figure
2. System
functio
n bl
ock
of interface
IC.
After th
e
p
u
l
ses b
e
en
co
un
ted, th
e system
ca
n
u
tili
ze th
e cou
n
t
er in
t
w
o
ways. First, t
h
e
1
6
-b
it latch
and i
nhi
bit logic on the c
h
ip
allows access t
o
16 bits
of count re
quire
d
, a
sim
p
le 8-bit m
ode is vailable by
d
i
sab
ling
th
e in
h
i
b
it lo
g
i
c.
Th
e inh
i
b
it log
i
c o
n
th
e ch
ip
i
n
h
i
b
its th
e tran
sfer
o
f
d
a
ta fro
m
th
e co
un
ter to
the
p
o
s
ition
d
a
ta latch
du
ri
n
g
the ti
m
e
in
terv
al th
at th
e latch
o
u
t
p
u
t
are
b
e
in
g read
. Th
e i
n
h
i
b
it lo
g
i
c all
o
ws the
micro
p
r
o
cessor
o
r
d
i
g
ital syste
m
to
firstly read
th
e lo
w
o
r
der
b
y
te form
th
e latch
.
Meanwh
ile, t
h
e coun
ter can
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Di
gi
t
a
l
E
n
c
ode
r Desi
gni
ng
f
o
r Mo
bi
l
e
R
o
b
o
t
C
o
nt
rol
(Alireza Re
zaee)
65
0
cont
i
n
ue t
o
ke
ep t
r
ac
k
of
t
h
e
qua
d
r
at
ure
dec
ode
r st
at
es
fr
o
m
t
h
echan
nel
-
A a
n
d
cha
n
nel
-
B
i
n
put
si
g
n
al
. I
n
t
h
e
fo
llowing
,
o
n
l
y th
e d
e
sig
n
s
for th
e d
i
g
ital filters Qu
ad
rat
u
re
d
ecod
e
r, an
d
inh
i
b
it lo
g
i
c are d
e
scri
b
e
d
.
Th
e
p
o
s
ition
cou
n
t
er an
d latch
circu
it, wh
ich ar
e v
e
ry
co
mm
o
n
,
are n
o
t
d
e
scribed
h
e
re.
3.
DESIGN OF THE
INTERFACE IC
3.
1. Di
gi
tal
Fi
l
t
er
Th
e
d
e
sign
o
f
t
h
e
d
i
g
ital filters is b
a
sed
o
n
the fi
n
ite state mach
in
e m
o
d
e
l
with
d
a
tap
a
th (FSMD) [9
].
Figure
3 shows the circ
uit architectur
e
of
digital filter which consists of
cont
rol unit
a
nd data
path on
each
ch
ann
e
l. Th
e co
n
t
ro
l un
it is reco
gn
i
zer t
h
at checks if the i
n
put from
th
e opt
i
cal
enc
ode
r has s
h
ort
d
u
r
at
i
on
pul
ses
,
an
d a D fl
i
p
fl
op
. If t
h
e i
n
p
u
t
l
e
vel
has sam
e
val
u
e (
1
or
0)
on
at least th
reeconsec
utive cloc
k cycles,
th
en
t
h
e inpu
t is no
t con
s
i
d
ered
as a no
ise.
In th
is cas
e t
h
e
output of the
re
cognizer
is activ
e
h
i
gh
,wh
i
ch
th
en
allo
ws th
e inpu
t d
a
ta t
o
fl
ow throug
h th
e d
a
tap
a
t
h
. Th
e d
a
ta v
a
l
u
e thu
s
b
eco
m
e
s th
e n
e
w ou
tpu
t
o
f
filter.
Oth
e
rwise t
h
e i
n
pu
t is con
s
id
ered as a
no
ise an
d th
e
d
a
tapath ou
tpu
t
of t
h
e filter rem
a
in
th
e sam
e
Fig
u
re 3
.
Im
p
l
e
m
en
tatio
n
o
f
d
i
g
ital
filter.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 4
,
N
o
. 5
,
O
c
tob
e
r
20
14
:
648
–
6
57
65
1
Fig
u
re
4
.
Desi
g
n
of t
h
e recogn
izer
o
f
d
i
g
italfilte
r: (a) state d
i
agram
(b
)
n
e
x
t
state/o
upu
t tab
l
e,
(c) ex
citatio
n
t
ab
le, ex
citatio
n
an
d ou
tpu
t
eq
uatio
n
s
.
We assu
m
e
th
a
t
th
e d
e
sign
of
co
n
t
ro
l un
it fo
llo
ws th
e
fin
ite state
m
ach
in
e (FSM) m
o
d
e
l, co
n
s
isiti
ng
of
ne
xt
-st
a
t
e
l
o
gi
c, a
st
at
e re
gi
st
er, a
n
d
an
o
u
t
put
l
ogi
c
[
9
,
1
0
,
1
1
]
.
C
onst
r
uct
i
o
n o
f
t
h
e m
odel
st
art
s
wi
t
h
t
h
e
g
e
nerat
i
o
n o
f
st
at
e di
agram
and/
o
r
ne
xt
st
at
e and
out
put
tables. Figure
4(a
)
shows the
state diagram
of the
r
ecognizer which cont
ains se
ve
n optimized states,
whe
r
e
each
state has diffe
re
nt
ne
xt
state or output
for
eve
r
y input. T
h
e
c
o
rrec
p
onding
next
-s
tate/output tabl
e with
appropriate state encoding is
show
n
in
Figure
4(b). After co
m
p
letin
g
th
e
process
o
f state
m
i
nim
i
za
tion and
state encoding, we a
r
e
ready
to choo
se t
h
e
pr
o
p
er t
y
pe
o
f
fl
i
p
fl
o
p
f
o
ri
m
p
l
e
m
e
nt
at
i
on of
t
h
e
FSM
m
odel
.
Si
nce D
fl
i
p
fl
ops
re
qui
red
fe
wer c
o
nnet
i
o
ns
, t
h
ey
are c
hos
en f
o
r
o
u
r
desi
gn
. T
h
e exci
t
a
t
i
on t
a
bl
e,
exci
t
a
t
i
o
n
and
o
u
t
p
ut
equ
a
t
i
ons by
usi
n
g
t
h
e D fl
i
p
fl
op
s act
ed as
the s
t
ate register are shown
in
Figu
re
4
(
c). Th
e dig
ital
filter circu
it an
d
si
m
u
latio
n
resu
lt are sh
own in
fig
u
re 5
(
a)
an
d
(b), resp
ectiv
ely. As can
b
e
seen
fro
m
Fig
u
re
5(
b)
, t
h
e s
h
ort
-
du
rat
i
o
n n
o
i
s
e
on t
h
e i
n
put
si
gnal
(x
) i
s
re
je
ct
ed o
n
t
h
e
o
u
t
put
(d
fo
ut
) at
t
h
e ex
pe
nse
of
t
h
ree
cl
ocks
t
i
m
e
del
a
y
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Di
gi
t
a
l
E
n
c
ode
r Desi
gni
ng
f
o
r Mo
bi
l
e
R
o
b
o
t
C
o
nt
rol
(Alireza Re
zaee)
65
2
3.
2. Qu
adr
a
t
u
er
Dec
o
der
The a
q
adrature
decode
r section consisits of a
direc
tion
d
e
cod
e
r and
a 4-time rate circu
it. It sam
p
les
th
e two
qu
ad
ratu
re sign
al from th
e d
i
g
ital fi
lters o
u
t
pu
ts an
d
o
b
serv
es chan
g
e
s in
th
ese
o
u
t
p
u
t
s
o
n
th
erisin
g
cl
ock e
d
ge. T
h
e t
w
o
q
u
ad
rat
u
re si
g
n
al
s ca
n
be e
n
co
dere
d
a
s
four states. T
h
e state cha
nges can
be
detected by
co
m
p
arin
g th
e prev
i
o
u
s
ly sam
p
led
state to
th
e cu
rren
t
sam
p
led
state. Th
is can
in turn
m
u
ltip
ly th
e in
pu
t
si
gnal
f
r
eq
ue
n
c
y
by
a fact
or
of
fo
ur
. A
new
m
e
t
hod f
o
r
de
t
ect
i
ng t
h
e r
o
t
a
t
i
ondi
rect
i
on
o
f
t
h
e m
o
t
o
r i
s
sho
w
n
i
n
Fi
g
u
re
6.
It
can be
seen t
h
at
t
h
e enc
ode
d
st
at
e of 8
,
1
4
,
7, a
nd
1 i
n
cl
ock
w
i
s
e
di
rect
i
on a
r
e
di
ffe
ren
t
from
th
o
s
e states
o
f
2
,
1
1
, 13
, and
4
.
Thu
s
we can
u
s
e a
4-to
1
6
d
e
m
u
ltip
lex
e
r an
d
so
m
e
o
u
t
pu
t lo
g
i
c to
d
e
tect th
e
di
rect
i
o
n.T
h
e
cou
n
t
di
rect
i
o
n
(
u
p
or
do
w
n
) i
s
al
so det
e
rm
ined
by
o
b
se
rvi
ng t
h
e
pre
v
i
o
u
s
an
d cu
rre
nt
s
t
at
es.
The
desi
g
n
ci
r
c
ui
t
i
s
sh
o
w
n i
n
t
h
e
b
o
t
t
o
m
part
o
f
Fi
gu
re
7.
The
u
ppe
r
par
t
of
Fi
g
u
re
7
sh
ows
t
h
e
desi
gn
of
t
h
e
4
-
tim
e rate circu
it, th
e
ou
tpu
t
o
f
wh
ich is go
i
n
g to
fetch in
to an
up
/do
w
n
po
sitio
n coun
ter.
Fig
u
re
5
.
(a) the d
i
g
ital filter circu
it (b
)sim
u
l
atio
n
resu
lt
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 4
,
N
o
. 5
,
O
c
tob
e
r
20
14
:
648
–
6
57
65
3
Fig
u
re
6
.
Th
e
d
e
term
in
in
g
strateg
y
fo
r
ro
tatio
n d
i
rectio
n.
3.
3. I
nhi
bi
t
L
o
gi
c
Th
e inh
i
b
it lo
gic sectio
n
samp
les th
e o
e
/ and
sel read
ing
co
mman
d
sign
al fro
m
th
e
m
i
c
r
op
ro
cessor
o
r
d
i
g
ital system
o
n
th
e falling
ed
g
e
of th
e clo
c
k
and
in
h
i
b
i
ts th
e po
sition
d
a
ta latch
to av
o
i
d
th
e latch
e
d
d
a
ta
being update
d
during a two-byte readi
ng cy
cles for a 16-bit data access. The desis
n
of the inhi
bit logi
c also
follows the FSM
m
odels as descri
bed a
b
ove.T
h
e state
di
agram
and ne
x
t
– st
at
e/
out
pu
t
abl
e
are sho
w
n i
n
fig
u
re 8
(
a) a
n
d
(b)
,
res
p
ective
l
y
.
As
can be s
een, the
r
e are three m
i
nim
u
m states and onl
y two flip flops are
n
eed
for th
e i
m
p
l
e
m
en
tatio
n
o
f
th
e m
o
d
e
l. Si
m
ilarly, we u
s
e th
e
D flip flo
p
as th
e state reg
i
sters
d
u
e to
its
si
m
p
licit
y. Th
e ex
citatio
n
tab
l
e equ
a
tio
n log
i
c ar
e sh
own
in
f
i
gu
r
e
8
(
c)
.
The ou
tpu
t
is ju
st
th
e sam
e
as second
flip
fl
o
p
ou
tpu
t
state.
Fi
gu
re 7.
The
Qua
d
rat
u
re
dec
ode
r a
n
d f
o
ur
-tim
e rate circuit.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Di
gi
t
a
l
E
n
c
ode
r Desi
gni
ng
f
o
r Mo
bi
l
e
R
o
b
o
t
C
o
nt
rol
(Alireza Re
zaee)
65
4
Fi
gu
re
8.
Desi
gn
o
f
i
nhi
bi
t
l
o
gi
c (a
) st
at
e
di
agram
,
(b
)
next
-
s
t
a
t
e
/
out
p
u
t
t
a
b
l
e,
(c) ex
citatio
n tab
l
e and
ex
citatio
n
eq
u
a
ti
o
n
.
4.
SIMULATION AND
TEST
Th
e
ov
erall circu
it of t
h
e in
terface IC
p
l
o
tted
b
y
u
s
ing
t
h
e Altra MAXPLUS
II an
d ISE Xilinx
.
Is
sho
w
n i
n
fi
g
u
r
e
9. T
h
e
wa
ve
fo
rm
sim
u
l
a
tion
p
r
o
v
i
d
e
d
i
n
t
h
i
s
t
ool
has
veri
fi
e
d
eac
h c
i
rcui
t
sy
m
bol
in t
h
i
s
figure. An
ove
rall sim
u
lation res
u
lt to
test the function of
the
interface IC is shown in
Figure 10
by giving
tw
o
qu
ad
r
a
ture inp
u
t
sign
al
(
c
h
a
and chb
)
an
d a cl
o
c
k si
g
n
a
l
w
ith m
u
ch
h
i
gh
er fr
eq
uen
c
y th
an
t
h
e
in
pu
t
qua
d
r
at
ure si
g
n
al
s. As ca
n b
e
seen, a 4
-
t
i
m
e
rat
e
si
gnal
(4
xf
f)
wh
ose f
r
e
que
ncy
i
s
fo
ur
t
i
m
e
s of t
h
at
of i
n
p
u
t
p
u
l
ses is su
ccessfu
lly g
e
n
e
rat
e
d
In
add
itio
n
,
th
e d
i
rectio
n
sig
n
a
l (d
ir) is
activ
e lo
w if th
eph
a
se
A sign
al is
lead
in
g th
e
phase B sign
al an
d activ
e
h
i
gh if th
e
ph
ase
Asign
a
l is lagg
ing
th
e ph
as
B sig
n
a
l. The
p
o
s
ition
up/
do
w
n
c
o
u
n
t
e
r
up
co
u
n
t
s
f
r
o
m
0 t
o
9
w
h
i
l
e
t
h
e
di
r si
gn
al
i
s
act
i
v
e
hi
g
h
.
Th
e
p
o
s
ition
data latch
o
u
t
put (latch
[7..0
]
)
Re
m
a
in
s at 6
wh
en
th
e
o
e
/si
g
n
a
l is activ
e l
o
w
for a
1
6
-
bit data access. At the
sam
e
ti
me the inhi
bit logic
output
signal (i
nh) is acti
v
e
high
a
n
d re
mains high
until the
l
o
w
-
by
t
e
dat
a
has bee
n
read
out
o
n
t
h
e seco
nd rea
d
i
n
g
cycle. The sim
u
lation res
u
lts indi
cate that the function
of qua
d
rat
u
re
decode
r/counte
r
interface IC
are correct
. T
h
e design circ
uit has b
een furt
her tested by the
ex
p
e
r
i
m
e
n
t
al syste
m
, as show
n in
Figu
r
e
1
1
. Th
e m
o
tor optical enc
o
der ca
n
produc
e two qua
d
rat
u
re
A/B
p
h
a
se sig
n
als with
th
e rate of 20
00
pu
lses
p
e
r revo
lu
tio
n.
A t
e
st
pro
g
r
a
m
i
n
t
h
e perso
n
al
com
put
er h
a
s bee
n
d
e
sign
ed
to read
th
e coun
t nu
m
b
er latch
e
d on
th
e in
t
e
r
f
a
ce IC
.
Fo
r
dec
odi
ng
an
d c
o
u
n
t
i
n
g
t
h
e
p
u
l
s
e
s
, we
ro
tate th
e m
o
to
r sh
aft m
a
n
u
a
lly in
abou
t every fiv
e
secon
d
s.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 4
,
N
o
. 5
,
O
c
tob
e
r
20
14
:
648
–
6
57
65
5
Fi
gu
re
9.
The
ove
ral
l
ci
rc
ui
t
of
q
u
a
d
ratu
re
d
ecode
r/co
u
n
ter
interfac
e
IC
.
Fig
u
r
e
10
.Simu
l
atio
n
r
e
su
lt of
th
e qu
ad
r
a
ture d
e
co
d
e
r
/
counter
In
ter
f
a
ce I
C
During
th
e ti
me in
terv
al
,we can
see t
h
e latch
e
d c
oun
t nu
mb
er
d
i
sp
layed
o
n
th
e PC m
o
nito
r clearly
.
Fo
r on
e
ro
tatio
n
i
n
th
e cl
o
c
k
w
ise
ro
tation
,
th
ere
will b
e
8
000
pu
lses t
o
b
e
co
un
ted, an
d
t
h
en th
e
d
i
sp
lay
num
ber i
s
1F
4
0
i
n
h
e
x
-
deci
m
a
l
dat
a
f
o
rm
at
.
Tabl
e
I s
u
m
m
a
ri
es t
h
e
co
ut
n
u
m
b
er co
rres
p
on
di
n
g
t
o
t
h
e r
o
t
a
t
i
o
n
cycles in cloc
kwise and c
o
unt
er cloc
kw
ise directio
n
,
resp
ectiv
ely. Th
e
resu
lts also
v
e
rify th
e fu
n
c
ti
o
n
o
f
t
h
e
qua
drature
ec
oder/c
ounter i
n
t
e
rface
IC
properly.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Di
gi
t
a
l
E
n
c
ode
r Desi
gni
ng
f
o
r Mo
bi
l
e
R
o
b
o
t
C
o
nt
rol
(Alireza Re
zaee)
65
6
Figure
11. T
h
e
experim
e
ntal sy
ste
m
fortesting the
interface
IC.
Tabl
e
1. T
h
e
m
o
t
o
r r
o
t
a
t
i
o
n c
y
cl
es and
co
rre
spo
n
d
i
n
g c
o
unt
s.
Rotation
cycles pe
r 5
sec
Counts in
Clockwise
Dir
ection
Counts in
Counter
Clockwise
Dir
ection
1 1F40
E
0
BF
2 3E
80
C17F
3 5DC0
A23F
4 7D00
82FF
5 9C40
63BF
I
m
p
l
e
m
en
t in
2s1
50f
g25
6 x
ilin
x
i
n
I
S
E
Dev
i
ce Utilizatio
n
fo
r 2
s
15
0fg
4
56
Resource used
Avail
utilize
I
/
Os
57
288
19.
79%
Function gener
a
tor
57
3456
1.
65%
CL
B Slices
35
1728
2.
03%
DFFs 70
4320
1.
62%
5.
CO
NCL
USI
O
N
This pa
per pre
s
ents the design of
qua
drat
ure deco
der/c
o
unter interface IC in the gate
and re
giste
r
l
e
vel
by
usi
n
g
an Al
t
r
a FLE
X
1
0
k
A
, XC
9
5
1
4
4
X
L
Xi
l
i
nx de
vi
ce. Im
plem
ent
a
t
i
on of
t
h
e ci
rcui
t
usi
ng t
h
e
C
P
LD de
vi
ce i
s
easi
e
r t
h
an t
h
e pre
v
i
o
us w
o
r
k
d
one i
n
t
r
a
n
s
i
st
or l
e
vel
.
Si
m
u
l
a
t
i
on and e
xpe
ri
m
e
nt
al
t
e
st
s are
shown to ve
ri
fy the
ASIC
functio
ns
properly. T
h
e i
n
terface
IC ca
n be a
p
pliedas
an i
n
terface
to a
m
i
cropr
ocess
o
r – ba
sed m
o
t
o
r co
nt
rol
sy
st
e
m
. It
can be al
so i
n
t
e
g
r
at
ed a
s
a part
of ci
r
c
ui
t
of an a
p
pl
i
cat
i
on-
speci
fi
c di
gi
t
a
l
co
nt
r
o
l
IC
fo
r m
o
ti
on
c
ont
rol
.
REFERE
NC
ES
[1]
L Zhen,
L Xu. “Sensorless Field Oriention Con
t
rol of
Inductio
n
Machines Bas
e
d on a Mutual MRAS Scheme”.
IEEE Industrail
Electronics
. 201
2; 45: 824-831.
[2]
K Kubo, M Watanabl
e, T Ohm
a
e, and
K Kam
i
y
am
a. “A full
y
d
i
gital
i
zed speed r
e
gulator usigm
u
ltim
icropro
cessor
s
y
stem for
induction motor dr
ivers”.
I
EEE Trans. Ind. Applicant
.
1985; IA- 1: 100
1-1008.
[3]
Hewlett
P
ack
ard
.
Quadrature Decoder/Counter
I
n
terface ICs HC
TL- 2000
. 2016
Datasheet.
[4]
H Le_Hu
y
. “
Microprocessors an
d digita
l ICs
for
motion con
t
rol
”. Proc. ofthe EEE. 1994; 82(8): 11
40- 1163.
[5]
EB Patterson, D
Morley
, CG Oswald,
and PG Holmes. “Total d
i
gital ASIC
contr
o
l for an
induction motor drive”.
IEE Co
lloquium
onASIC Techno
logy
for Power Electronics
Equ
i
p
m
ent
. 2010
: 2
/
1-
4.
[6]
J Pasanen, P Jah
konen, SJ Ovask
a
, O V
a
inio
, H
Te
nhunen. “An in
tegrated d
i
gital
motion contro
l u
n
it”.
IEEE Trans.
on Instrumentation and Measurement
. 1991
; 40(3
)
: 654- 657
.
[7]
CC W
a
ng, P
M
Lee
,
YL
Ts
eng
,
and CF
W
u
. “
A
l
o
w-cos
t
quardrt
ure de
coder
/
cou
n
ter
interf
ac
e
int
e
grat
ed
circu
it
f
o
r
AC induction motor server
con
t
r
o
l”.
Int
.
J.
El
ectr
onis
. 2000; 87(9
)
: 1053- 1063
.
[8]
AltraInc, FLEX
10KA Handbook, 1997
.
[9]
Daniel D Gajski.
Princ
i
ples o
f
Di
gital D
e
sign
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BIOGRAP
HI
ES OF
AUTH
ORS
Alirez
a Re
za
ee
rece
ived h
i
s
B.
S
c
. degr
ee
in C
ontrol Eng
i
ne
eri
ng from
S
h
arif
Univers
i
t
y
of
Techno
log
y
, Iran 2002 and M.Sc and Ph.D degree
in Electrical Engin
eering f
r
om Amirkabir
University
of
Technolog
y
,
Iran
(
2005 and 2011
r
e
spectively
)
.
From
2013 till now he is an assistance prof
essor in departm
e
nt of s
y
stem
an
d m
echatroni
cs
engineering in n
e
w sciences and techno
log
y
f
acu
lty
at univers
i
t
y
o
f
Tehran
. His
res
earch in
ter
e
s
t
are in intelligent robotics, mobile robot, navi
gation
,
machine learning
, bay
e
sian networks
,
cognitiv
e sc
ien
c
e.
Reza Afshar was born in
Qazvin-Iran
in 198
9.
He r
e
ceived
the B
.
Sc. degr
ee
in electrical
engineering fro
m the Islamic Azad University
,
Bu
in Zahr
a,
Iran, in 2014
. Currently
,
he is
working toward his M.S degree in Electrical En
gineer
ing at Is
la
m
i
c Azad Unive
r
s
i
t
y
M
i
yan
e
h
Bra
n
c
h
, Miy
a
neh,
Ira
n
. His re
searc
h
inte
re
sts in
clude an
aly
s
is
and
designing
of Digital VLSI.
Evaluation Warning : The document was created with Spire.PDF for Python.