Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
7,
No.
2,
April
2017,
pp.
759
–
766
ISSN:
2088-8708
759
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
A
New
Instrumentation
Amplifier
Ar
chitectur
e
Based
on
Differ
ential
Differ
ence
Amplifier
f
or
Biological
Signal
Pr
ocessing
Zainul
Abidin
1
,
K
oichi
T
anno
2
,
Shota
Mago
3
,
and
Hir
oki
T
amura
4
1
Department
of
Materials
and
Informatics,
Uni
v
ersity
of
Miyazaki,
Japan
2,3
Department
of
Electrical
and
System
Engineering,
Uni
v
ersity
of
Miyazaki,
Japan
4
Department
of
En
vironmental
Robotics,
Uni
v
ersity
of
Miyazaki,
Japan
Article
Inf
o
Article
history:
Recei
v
ed
No
v
9,
2016
Re
vised
Feb
24,
2017
Accepted
Mar
9,
2017
K
eyw
ord:
biological
signal
instrumentation
amplifier
dif
ferential
dif
ference
amplifier
common-mode
g
ain
resistor
mismatches
ABSTRA
CT
In
this
paper
,
a
ne
w
Instrum
entation
Amplifier
(IA)
architecture
for
biological
signal
pro-
cessing
is
proposed.
First
stage
of
the
proposed
IA
archi
tecture
consists
of
fully
balance
dif
ferential
dif
ference
amplifier
and
three
resistors.
Its
second
stage
w
as
designed
by
using
dif
ferential
dif
ference
amplifier
and
tw
o
resistors.
The
second
stage
has
smaller
number
of
resistors
than
that
of
con
v
entional
one.
The
IA
architectures
are
simulated
and
compared
by
using
1P
2M
0
:
6
-
m
CMOS
process.
From
HSPICE
simulation
result,
lo
wer
common-
mode
v
oltage
can
be
achie
v
ed
by
the
proposed
IA
archi
tecture.
A
v
erage
common-mode
g
ain
(
A
c
)
of
the
proposed
IA
architecture
is
31
:
26
dB
lo
wer
than
that
of
con
v
entional
one
under
3
%
resistor
mismatches
condition.
Therefore,
the
A
c
of
the
proposed
IA
architecture
is
more
insensiti
v
e
to
resistor
mismatches
and
suitable
for
biological
signal
processing.
Copyright
c
2017
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
K
oichi
T
anno
Department
of
Electrical
and
Systems
Engineering
Institute
of
Education
and
Research
for
Engineering,
Uni
v
ersity
of
Miyazaki
1-1,
Gakuen
Kibanadai
Nishi,
Miyazaki,
889-2192,
Japan
tanno@cc.miyazaki-u.ac.jp
1.
INTR
ODUCTION
Biological
signals
processing
by
using
wearable
de
vice
is
useful
for
health
care
system.
Sensing
of
biological
signals
is
a
v
ery
challenging
research.
The
bi
ological
signals,
such
as
Electroencephalogram
(EEG),
Electrooculogram
(EOG),
Electrocardiogram
(ECG),
Electromyogram
(EMG),
and
Axon
Action
Potential
(AAP)
ha
v
e
amplitudes
in
the
order
of
V
to
mV
and
frequencies
span
from
DC
to
a
fe
w
kHz,
as
sho
wn
in
Fig.1
[1]-[3].
In
order
to
detect
and
process
the
v
ery
weak
and
lo
w
frequenc
y
signals,
design
of
analog
front-end
has
to
meet
strict
performance
parameters.
IA
is
often
used
in
sensor
interf
ace.
Three
operational
amplifiers
(op-amps)
based
IA
archite
cture
is
often
emplo
yed
to
achie
v
e
high
signal-to-noise
ratio
in
first
block
of
sensor
interf
ace.
In
the
case
of
biological
signals
sensing,
the
IA
architecture
needs
lo
w
A
c
and
it
can
be
achie
v
ed
by
satisfying
well-matched
condition
of
resistors
netw
ork
[4]-[10].
Ho
we
v
er
,
in
actual
f
abricat
ed
chips,
res
istors
are
often
not
well-matched
and
it
deteriorates
the
A
c
.
In
reference
[3],
an
IA
architecture
based
on
Fully
Balanced
Dif
ferential
Dif
ference
Amplifier
(FBDD
A)
which
its
A
c
is
lo
w
and
insensiti
v
e
t
o
resistor
mismatches
w
as
presented.
In
this
paper
,
it
is
called
as
con
v
entional
IA
architecture.
W
ith
same
number
of
resistors
(7
resistors
i
ncluding
g
ain-setting
resistor),
tw
o
op-amps
in
first
stage
of
the
3
op-amps
based
IA
architecture
were
replaced
by
using
FBDD
A.
Lar
ge
common-mode
input
v
oltage
and
limitation
of
circuit
design
of
the
FBDD
A
(in
the
first
stage)
produce
some
amount
of
common-mode
v
oltage.
Under
the
resistor
mismatches
condition,
common-mode
v
oltage
reduction
by
the
second
stage
is
necessary
.
This
paper
focuses
on
reduction
of
remaining
common-mode
v
oltage
of
first
stage
by
ne
w
design
of
second
stage.
Furthermore,
a
ne
w
IA
architecture
based
on
Dif
ferential
Dif
ference
Amplifier
(DD
A)
with
smaller
number
of
resistors,
lo
wer
A
c
J
ournal
Homepage:
http://iaesjournal.com/online/inde
x.php/IJECE
I
ns
t
it
u
t
e
o
f
A
d
v
a
nce
d
Eng
ine
e
r
i
ng
a
nd
S
cie
nce
w
w
w
.
i
a
e
s
j
o
u
r
n
a
l
.
c
o
m
,
DOI:
10.11591/ijece.v7i2.pp759-766
Evaluation Warning : The document was created with Spire.PDF for Python.
760
ISSN:
2088-8708
and
more
insensiti
v
e
to
resistor
mismatches
is
presented.
Figure
1.
V
oltage
and
frequenc
y
ranges
of
some
biological
signals
Figure
2.
Three
op-amps
based
IA
architecture
2.
PR
OBLEM
OF
CONVENTION
AL
INSTR
UMENT
A
TION
AMPLIFIER
ARCHITECTURE
In
man
y
te
xt
books
and
literatures,
under
the
condition
of
well-matched
resistors
netw
ork
(
R
2
=
R
3
,
R
4
=
R
5
,
and
R
6
=
R
7
),
deri
v
ation
of
output
v
oltage
of
the
3
op-amp
based
IA
architecture
sho
wn
in
Fig.2
(
V
out
),
can
be
determined
by
V
out
=
R
7
R
5
2
R
3
R
1
+
1
(
V
in
2
V
in
1
)
(1)
Defining
V
in
1
and
V
in
2
as
v
cm
v
dm
and
v
cm
+
v
dm
,
respecti
v
ely
(
v
cm
and
v
dm
are
common-mode
v
oltage
and
dif
ferential
input,
respecti
v
ely).
Representing
resistor
mismatch
of
R
i
as
R
i
+1
(1
+
i
+1
)
j
i
2
f
2
;
4
;
6
g
,
where
i
+1
is
mismatch
rate
of
R
i
+1
,
the
V
out
becomes
[3]
V
out
=
R
7
R
5
2
R
3
R
1
(1
+
+
3
)
+
1
+
v
dm
+
R
7
R
5
(
1)
v
cm
(2)
where
is
coef
ficient
defined
as
follo
ws
=
R
5
+
R
7
R
5
(1+
5
)
1+
7
+
R
7
(3)
IJECE
V
ol.
7,
No.
2,
April
2017:
759
–
766
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
761
Figure
3.
IA
architectures:
(a)
Con
v
entional
(b)
Proposed
Eq.
2
indicates
that
the
V
out
contains
v
cm
.
The
is
caused
by
resistor
mismatches
of
second
stage.
Therefore,
g
ain
of
second
stage
is
often
set
to
0
dB
to
a
v
oid
deterioration
of
the
A
c
.
In
this
w
ay
,
the
A
c
of
the
3
op-amps
based
IA
architecture
is
sensiti
v
e
to
the
resistor
mismatches
[3].
In
order
to
o
v
ercome
this
problem,
we
proposed
IA
architecture
sho
wn
in
Fig.
3a
[3].
The
number
of
resistors
in
the
con
v
entional
IA
architecture
is
as
same
as
that
in
the
Fig.
2.
First
stage
of
the
con
v
entional
IA
architecture
which
is
modified
from
[11]
w
as
designed
by
using
FBDD
A,
2
ne
g
ati
v
e
feedback
resistors,
and
g
ain-setting
resistor
.
The
FBDD
A
consists
of
2
stages
fully
dif
ferential
g
ain
stage
and
Common-Mode
Feed
Back
(CMFB)
circuit
as
sho
wn
in
Fig.
4.
Since
an
ideal
amplifier
responds
only
to
dif
ferential
v
oltage,
A
c
is
zero
in
ideal
case.
Therefore,
in
ideal
condition,
the
output
v
oltages
of
FBDD
A
(
V
out
1
c;
2
c
)
can
be
determined
by
[11]
V
out
1
c;
2
c
=
A
f
(
V
in
2
V
in
3
)
(
V
in
1
V
in
4
)
g
(4)
where
A
is
the
amplification
of
FBDD
A.
Using
(4)
and
the
defined
V
in
1
and
V
in
2
,
under
the
same
manner
of
resistor
mismatch
condition,
output
v
oltages
of
the
first
stage
(
V
out
1
c;
2
c
)
become
as
follo
w
.
V
out
1
c
=
R
3
R
1
(2
+
3
)
+
1
v
dm
(5)
V
out
2
c
=
R
3
R
1
(2
+
3
)
+
1
v
dm
(6)
While,
its
s
econd
stage
is
op-amp
based
subtractor
.
Final
output
(
V
outc
)
of
the
con
v
entional
IA
architecture
can
be
deri
v
ed
as
follo
ws.
V
outc
=
R
7
R
5
R
3
R
1
(2
+
3
)
+
1
(1
+
)
v
dm
(7)
From
the
abo
v
e
deri
v
ation,
v
cm
can
be
theoretically
rejected
since
passing
first
stage
and
lo
wer
A
c
can
be
achie
v
ed
e
v
en
though
there
are
resistor
mismatches.
Therefore,
we
can
set
the
g
ain
of
the
second
stage
lar
ger
than
0
dB
(of
fset
v
oltage
must
be
considered).
In
actual
condition,
nonideality
must
be
considered.
Limitations
in
practical
circuit
design
and
de
vice
mis-
matches
produce
some
amount
of
v
cm
,
especially
FBDD
A
[12].
T
ransistor
mismatch
often
occurs
due
to
channel
width
and
length
(
W
=L
).
Furthermore,
mismatch
of
W
=L
v
alue
will
af
fect
to
mismatch
of
transconductance
(
g
m
)
as
mentioned
in
this
deri
v
ation
result
[13,
14].
g
m
=
@
I
ds
@
V
g
s
(8)
=
s
2
C
ox
W
L
j
I
ds
j
(1
+
V
ds
)
(9)
=
s
2
C
ox
W
L
j
I
ds
j
(10)
A
Ne
w
Instrumentation
Amplifier
Ar
c
hitectur
e
Based
on
Dif
fer
ential
Dif
fer
ence
Amplifier
...
(Zainul
Abidin)
Evaluation Warning : The document was created with Spire.PDF for Python.
762
ISSN:
2088-8708
Figure
4.
Circuit
schematic
of
FBDD
A
Figure
5.
Circuit
schematic
of
op-amp
Figure
6.
Circuit
schematic
of
DD
A
Since
the
FBDD
A
main
component
is
cross-coupled
amplifier
(see
Fig.
4),
tra
nsistor
mismatch
of
cross-coupled
amplifier
is
analyzed.
In
order
to
analyze
the
ef
fect
of
transconductance
mismatch
of
transistors
M
17
,
M
18
,
M
19
,
and
M
20
(see
Fig.
4),
the
cross-coupled
amplifier
can
be
simplified
by
replacing
transistors
M
7
and
M
8
with
R
ss
and
transistors
M
33
and
M
34
with
R
d
.
Supplying
the
inputs
with
v
cm
,
the
common-mode
g
ain
of
the
cross-coupled
amplifier
(
A
ccr
)
can
be
deri
v
ed
as
follo
ws.
A
ccr
=
V
out
2
c;p
V
out
1
c;p
v
cm
=
f
(
g
m
17
+
g
m
18
g
m
19
g
m
20
)
v
cm
(
g
m
17
g
m
18
)
V
p
(
g
m
19
g
m
20
)
V
q
g
R
d
v
cm
=
(
(
g
m
17
+
g
m
18
g
m
19
g
m
20
)
g
2
m
17
+
g
2
m
18
R
ss
(
g
m
17
+
g
m
18
)
R
ss
+
1
g
2
m
19
+
g
2
m
20
R
ss
(
g
m
19
+
g
m
20
)
R
ss
+
1
)
R
d
(11)
Since
A
c
of
FBDD
A
(
A
cF
B
D
D
A
)
is
not
infinite
from
(11),
some
amount
of
v
cm
may
appear
in
V
out
1
c;
2
c
.
Because
IJECE
V
ol.
7,
No.
2,
April
2017:
759
–
766
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
763
of
g
ain
or
resistor
mismatches
of
second
stage,
the
v
cm
may
appear
and
be
amplified
in
V
outc
.
Finally
,
this
condition
deteriorates
the
A
c
of
the
IA
architecture.
Ne
xt,
we
discuss
about
ne
w
design
of
second
stage
in
the
proposed
IA
architecture.
3.
PR
OPOSED
INSTR
UMENT
A
TION
AMPLIFIER
ARCHITECTURE
Proposed
IA
architecture
is
sho
wn
in
Fig.
3b
.
The
proposed
IA
architecture
consists
of
2
stages.
First
stage
is
as
same
as
that
of
the
con
v
entional
one.
It
has
the
same
output
v
oltages
(
V
out
1
p;
2
p
)
as
(5)
and
(6),
respecti
v
ely
.
Second
stage
consists
of
Dif
ferential
Dif
ference
Amplifier
(DD
A)
and
tw
o
resistors
which
are
independent
each
other
.
The
DD
A
is
4
inputs
single
output
amplifier
.
In
ideal
condition,
the
relationship
can
be
defined
as
follo
ws.
V
outp
=
A
f
(
V
out
1
p
V
out
2
p
)
(
V
f
V
g
)
g
(12)
Implementing
DD
A
for
second
stage
may
reduce
the
remaining
v
cm
of
first
stage
(in
V
out
1
p;
2
p
of
Fig.
3b)
because
V
outp
sho
wn
in
(12)
has
component
of
subtraction
(
V
out
1
p
V
out
2
p
)
which
is
independent
of
resistor
mismatch.
Furthermore,
re
g
arding
resistors
used
in
the
second
stage,
number
of
resistors
of
the
proposed
IA
architecture
is
smaller
than
that
of
the
con
v
entional
one.
Using
(12)
and
referring
Eqs.(5)
and
(6),
the
output
of
the
second
stage
(
V
outp
)
under
the
resistor
mismatch
condition
can
be
deri
v
ed
as
follo
ws.
V
outp
=
2
1
+
R
f
R
g
R
3
R
1
(2
+
3
)
+
1
v
dm
(13)
From
Eq.
(13),
e
v
en
though
A
cF
B
D
D
A
is
finite,
g
ain
of
second
stage
is
more
than
0
dB,
and
resistor
mismatch
of
second
stage
occurs,
the
v
cm
can
be
drastically
reduced
compared
with
con
v
entional
one.
As
mentioned
in
Chapter
2,
in
IA
sho
wn
in
Fig.
2,
resistor
mismatches
of
second
stage
cause
high
A
c
(see
Eq.
(2)).
Therefore,
implementing
2
independent
resistors
(
R
f
and
R
g
),
the
second
stage
of
the
proposed
IA
architecture
can
be
set
to
higher
g
ain
to
get
hi
gher
dif
ferential
g
ain
with
smaller
ef
fect
to
the
A
c
.
Furthermore,
ne
w
design
of
second
stage
mak
es
the
proposed
IA
architecture
has
lo
wer
A
c
and
more
insensiti
v
e
to
resistor
mismatches
than
the
con
v
entional
one.
4.
SIMULA
TION
RESUL
T
In
this
chapter
,
the
IA
architectures
were
e
v
aluated
using
1P
2M
0
:
6
-
m
CMOS
process.
In
order
to
compare
the
performance
of
the
IA
architectures,
the
transistor
le
v
el
circuit
of
3
kinds
amplifier
were
realized.
The
op-amp
in
second
stage
of
con
v
entional
IA
architecture
w
as
realized
by
widely
used
op-amp
circuit
sho
wn
in
Fig.
5
[13,
15].
The
DD
A
w
as
realized
by
circuit
schematic
sho
wn
in
Fig.
6.
It
consists
of
2
stages
fully
dif
ferential
g
ain
stage
and
phase
compensation
circuits
(
R
c
4
,
C
c
4
)
with
single
output.
Fig.
4
sho
ws
the
emplo
yed
FBDD
A,
which
is
modified
from
the
reference
[11].
The
FBDD
A
is
de
v
eloped
from
DD
A
by
adding
CMFB
circuit
and
phase
compensation
circuits
(
R
c
2
and
C
c
2
)
because
of
its
dif
ferential
output.
In
the
CMFB
circuit,
V
c
is
set
to
0
V
.
T
able
1.
Simulation
Condition
Items
V
alue
CMOS
process
1P
2M
0
:
6
-
m
CMOS
V
dd
[V]
2
:
5
V
ss
[V]
2
:
5
V
c
[V]
0
R
bias
[k
]
295
M
1
;
3
[
m/
m]
1
:
3
/
2
,
M
=
2
M
4
14
[
m/
m]
1
:
3
/
2
,
M
=
4
M
15
28
[
m/
m]
16
:
1
/
3
,
M
=
2
M
29
40
[
m/
m]
3
:
3
/
2
,
M
=
2
R
c
1
4
[k
]
9
C
c
1
4
[pF]
0
:
5
Note:
M
means
the
number
of
parallel
connection
A
Ne
w
Instrumentation
Amplifier
Ar
c
hitectur
e
Based
on
Dif
fer
ential
Dif
fer
ence
Amplifier
...
(Zainul
Abidin)
Evaluation Warning : The document was created with Spire.PDF for Python.
764
ISSN:
2088-8708
Figure
7.
FFT
results
of
V
outc
and
V
outp
Figure
8.
Histogram
of
A
c
(dB)
based
on
Monte
Carlo
analysis
T
able
2.
Summary
of
the
Simulation
Results
P
arameters
Con
v
entional
IA
Proposed
IA
A
C
analysis
Dif
ferential
g
ain
[dB]
54
:
15
54
:
15
3
dB
g
ain
bandwidth
[kHz]
301
:
34
398
:
46
Po
wer
cons.
[
W]
843
:
79
992
:
52
Monte
Carlo
analysis
A
v
e.
Ac
[dB]
85
:
53
116
:
79
Noise
perf
ormance
(PV)
Input
ref.
noise
[
V/
p
H
z
]
89
:
68
89
:
68
Output
ref.
noise
[mV/
p
H
z
]
41
:
41
45
:
78
Note:
PV
=
Peak
V
alue
In
order
to
e
v
aluate
the
A
c
,
the
V
in
1
and
V
in
2
were
supplied
by
v
cm
which
is
repre
sented
by
sine
w
a
v
e
signal
with
amplitude
of
50
mV
and
frequenc
y
of
60
Hz.
The
resistors
netw
ork
of
both
IA
architectures
(see
Fig.
3)
w
as
designed
as
R
1
=
10
k
,
R
2
=
R
3
=
R
6
=
R
7
=
250
k
,
R
4
=
R
5
=
25
k
,
R
f
=
9
k
,
and
R
g
=
1
k
.
W
e
set
same
g
ain
for
both
stages
and
the
ideal
total
dif
ferential
g
ain
of
both
IA
architectures
is
54
:
15
dB.
The
IA
architectures
were
s
imulated
using
HSPICE.
The
detailed
simulation
condition
is
sho
wn
in
T
able
1.
Representing
w
orst
case
of
resistor
mismatches
conditi
on
(
3
%),
HSPICE
simulation
w
as
done
under
the
mismatch
rates
3
=
7
=
3%
and
5
=
3%
.
The
resistors
R
2
and
R
6
become
257
:
5
k
and
R
4
becomes
24
:
25
k
.
Fig.
7
sho
ws
the
FFT
simulation
result
of
V
outc
and
V
outp
.
At
frequenc
y
60
Hz,
the
v
cm
of
the
con
v
entional
and
proposed
IA
architectures
reach
98
:
66
dBV
and
137
:
34
dBV
,
respecti
v
ely
.
The
proposed
IA
architecture
has
38
:
68
dBV
lo
wer
v
cm
than
the
con
v
entional
one.
Monte
Carlo
simulation
w
as
done
by
500
tim
es
to
get
data
of
A
c
with
de
viation
of
resistor
mi
smatch
3
%
w
as
randomly
gi
v
en
to
all
resistors
of
both
IA
architectures.
Fig.
8
sho
ws
histogram
of
A
c
.
A
v
erage
A
c
of
the
proposed
and
con
v
entional
IA
architectures
are
116
:
79
dB
and
85
:
53
dB,
respecti
v
ely
.
The
a
v
erage
A
c
of
the
proposed
IA
architecture
is
lo
wer
than
that
of
t
he
con
v
entional
one.
Lastly
,
the
simulated
performance
of
the
IA
architectures
are
listed
in
T
able
2.
5.
CONCLUSION
In
this
paper
,
a
ne
w
IA
architecture
based
on
DD
A
has
been
presented.
Resistor
mismatches
ef
fect
to
common-mode
g
ain
of
IA
architectures
has
been
identified
and
compared
in
theoretic
al
analysis
and
HSPICE
sim-
ulation.
W
ith
same
dif
ferential
g
ain
and
smaller
number
of
resistors,
ne
w
design
of
second
stage
mak
es
the
proposed
IA
architecture
has
lo
wer
common-mode
g
ain.
Its
ability
to
achie
v
e
lo
wer
common-mode
g
ain
under
resistor
mis-
matches
condition
mak
es
it
more
suitable
as
a
part
of
inte
grated
circuit
for
biological
signal
processing.
This
design
w
as
submitted
for
f
a
b
r
ication.
Actual
chip
e
v
aluation
and
de
v
elopment
of
lo
w
common-mode
DD
A
and
its
transistor
mismatch
ef
fect
are
considered
as
future
w
ork.
IJECE
V
ol.
7,
No.
2,
April
2017:
759
–
766
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
765
A
CKNO
WLEDGEMENT
This
w
ork
is
supported
by
VLSI
Design
and
Education
Center
(VDEC),
the
Uni
v
ersity
of
T
ok
yo
in
collabo-
ration
with
Synopsys,
Inc.
and
Cadence
Design
Systems,
Inc.
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ong
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K.
T
anno,
S.
Mago,
H.
T
amura,
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w
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Amplifier
Architecture
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v
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to
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all
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J.
W
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wer
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R.
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all
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G.
W
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echniques
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u
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ork,
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R.
Dehghani,
”Design
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”
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[15]
N.
Mukahar
and
S.
H.
Ruslan,
”A
93.36
dB,
161
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CMOS
Operational
T
ransconductance
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T
A)
for
a
16
Bit
Pipeline
Analog-to-Digital
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v
erter
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”
IAES
International
Journal
of
Electrical
and
Computer
Engineering
,
v
ol.
2,
no.
1,
pp.
106-111,
Feb
.
2012.
BIOGRAPHIES
OF
A
UTHORS
Zainul
Abidin
w
as
born
in
1986.
He
recei
v
ed
the
B.
Eng.
from
Uni
v
ersity
of
Bra
wijaya
and
M.
Eng.
from
Uni
v
ersity
of
Miyazaki
in
2008
and
2011,
respecti
v
ely
,
and
is
currently
w
orking
for
Uni
v
ersity
of
Bra
wijaya
and
to
w
ard
the
PhD
de
gree
in
Department
of
Materials
and
Informatics
at
Uni
v
ersity
of
Miyazaki.
He
has
been
in
v
olv
ed
with
design
of
analog
inte
grated
circuit
since
Master
De
gree.
His
current
research
interest
includes
analog
circuit
for
biological
signal
processing.
He
is
af
filiated
with
IEEE
and
IEICE
as
student
member
.
A
Ne
w
Instrumentation
Amplifier
Ar
c
hitectur
e
Based
on
Dif
fer
ential
Dif
fer
ence
Amplifier
...
(Zainul
Abidin)
Evaluation Warning : The document was created with Spire.PDF for Python.
766
ISSN:
2088-8708
K
oichi
T
anno
w
as
born
in
Miyazaki,
Japan,
on
April
22,
1967.
He
recei
v
ed
B.
E.
and
M.
E.
de-
grees
from
the
F
aculty
of
Engineering,
Uni
v
ersity
of
Miyazaki,
Miyazaki,
Japan,
in
1990
and
1992,
respecti
v
ely
,
and
Dr
.
Eng.
de
gree
from
Graduate
School
of
Science
a
nd
T
echnology
,
K
umamoto
Uni
v
ersity
,
K
umamoto,
Japan,
in
1999.
From
1992
to
1993,
he
joined
the
Microelectronics
Prod-
ucts
De
v
elopment
Laboratory
,
Hitachi,
Ltd.,
Y
ok
ohama,
Japan.
He
w
as
eng
aged
in
research
on
lo
w-v
oltage
a
nd
lo
w-po
wer
equa
lizer
for
re
ad
channel
LS
I
of
ha
rd
disk
dri
v
es.
In
1994,
he
joined
Uni
v
ersity
of
Miyazaki,
where
he
is
currently
a
Professor
in
the
Department
of
Electrical
and
Sys-
tems
Engineering.
His
main
research
interests
are
in
analog
inte
grated
circuit
design
and
multiple-
v
alued
logic
circuit
design.
Dr
.
T
anno
is
a
member
of
IEEE
and
the
Ex
ecuti
v
e
Subcommittee
of
the
IEEE
Computer
Society
T
echnical
Committee
on
Multiple-V
alued
Logic.
Shota
Mago
w
as
born
in
1992.
He
recei
v
ed
the
B.Eng
from
Uni
v
ersity
of
Miyazaki
in
2015,
and
is
currently
studying
to
get
mast
er
de
gree
of
Electrical
and
Electronic
Engineering
at
Uni
v
ersity
of
Miyazaki.
His
current
research
is
Analog
CMOS
Inte
grated
Circuits.
Hir
oki
T
amura
recei
v
ed
the
B.E
and
M.E
de
gree
from
Miyazaki
Uni
v
ersity
in
1998
and
2000,
respecti
v
ely
.
From
2000
to
2001,
He
w
as
an
Engineer
in
Asahi
Kasei
Corporation,
Japan.
In
2001,
He
joined
T
o
yama
Uni
v
ersity
,
T
o
yama,
Japan,
where
He
w
as
a
T
echnical
Of
ficial
in
Department
of
Intellectual
Information
Systems.
In
2006,
He
joined
Miyazaki
Uni
v
ersity
,
Miyazaki,
Japan,
where
He
w
as
an
Assistant
Professor
in
Departm
ent
of
Electrical
and
El
ectronic
Engineering.
In
2012,
He
is
currently
a
Professor
in
the
Department
of
En
vironment
al
Robotics.
His
main
research
interests
are
Neural
Netw
orks
and
Optimization
Problems.
In
recent
years,
He
has
the
interest
in
Biomedical
Signal
Processing
using
Soft
Computing.
IJECE
V
ol.
7,
No.
2,
April
2017:
759
–
766
Evaluation Warning : The document was created with Spire.PDF for Python.