Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
8,
No.
6,
December
2018,
pp.
4148
4156
ISSN:
2088-8708,
DOI:
10.11591/ijece.v8i6.pp4148-4156
4148
High
Speed
and
Lo
w
P
edestal
Err
or
Bootstrapped
CMOS
Sample
and
Hold
Cir
cuit
Agung
Setiab
udi
1
,
Hir
oki
T
amura
2
,
and
K
oichi
T
anno
3
1
Department
of
Materials
and
Informatics,
Uni
v
ersity
of
Miyazaki,
Japan
2
Department
of
En
vironmental
Robotics,
Uni
v
ersity
of
Miyazaki,
Japan
3
Department
of
Electrical
and
System
Engineering,
Uni
v
ersity
of
Miyazaki,
Japan
Article
Inf
o
Article
history:
Recei
v
ed
Jan
23,
2018
Re
vised
May
31,
2018
Accepted
Jun
20,
2018
K
eyw
ords:
Sample
and
Hold
Circuit
Error
Reduction
CMOS
Switch
Clock
Feedthrough
Channel
Char
ge
Injection
Bootstrap
Circuit
Abstract
A
ne
w
high
speed,
lo
w
pedestal
error
bootstrapped
CMOS
sample
and
hold
(S/H)
circuit
is
proposed
for
high
speed
analog-to-
digital
con
v
erter
(ADC).
The
proposed
circuit
is
made
up
of
CMOS
transmission
g
ate
(TG)
switch
and
tw
o
ne
w
bootstrap
circuits
for
each
transistor
in
TG
switch.
Both
TG
switch
and
bootstrap
circuits
are
used
to
decrease
channel
char
ge
injection
and
on-resistance
input
signal
dependenc
y
.
In
result,
distortion
can
be
reduced.
The
decrease
of
channel
char
ge
injecti
on
input
signal
dependenc
y
also
mak
es
the
minimizing
of
pedestal
error
by
adjusting
the
width
of
NMOS
and
PMOS
of
TG
swi
tch
possible.
The
performance
of
the
proposed
circuit
w
as
e
v
aluated
using
HSPICE
0.18-
m
CMOS
process.
F
or
50
MHz
sinusoidal
1
V
peak-to-peak
dif
feren-
tial
input
signal
with
a
1
GHz
sampling
clock,
the
proposed
circuit
achie
v
es
2.75
mV
maximum
pedestal
error
,
0.542
mW
po
wer
consumption,
90.87
dB
SNR,
73.50
SIN
AD
which
is
equal
to
11.92
bits
ENOB,
-73.58
dB
THD,
and
73.95
dB
SFDR.
Copyright
©
2018
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
K
oichi
T
anno,
Department
of
Electrical
and
System
Engineering,
Uni
v
ersity
of
Miyazaki,
1-1
Gakuenkibanadai-nishi,
Miyazaki,
889-2192,
Japan.
tanno@cc.miyazaki-u.ac.jp
1.
INTR
ODUCTION
Analog
techniques
ha
v
e
dominated
signal
processing
for
years,
b
ut
digital
techniques
are
slo
wly
en-
croaching
into
this
domain.
Digital
signal
processing
(DSP)
is
becoming
popular
because
its
fle
xibility
to
per
-
form
v
arious
processing
operations.
This
technology
is
widely
used
in
man
y
dif
ferent
domains,
such
as
wireless
communications,
medical
electronics,
measurement
instrumentation,
digital
multimedia,
etc.
One
of
the
essen-
tial
component
of
DSP
is
analog
to
digital
con
v
erter
(ADC),
because
most
natural
signals
in
the
w
orld
(such
as
v
oltage,
current,
temperature
and
pressure)
are
analog.
ADC
perform
the
digitalization
of
analog
signals
at
fix
ed
time
period,
which
is
generally
specified
by
the
application.
Since
the
digital
signal
that
will
be
processed
by
DSP
is
originally
from
ADC,
performance
of
the
DSP
is
highly
dependent
to
the
performance
of
ADC
itself.
T
o
a
v
oid
premature
signal
de
gradation,
the
ADC
must
achie
v
e
specified
sampling
speed,
resolution
and
precision.
T
o
meet
the
specifications,
se
v
eral
techniques
and
ADC
architectures
ha
v
e
been
proposed.
P
arallel
(flash)
ADC
is
by
f
ar
the
f
astest
and
conceptually
simplest
has
been
reported
[1].
The
dra
wbacks
of
this
architecture
are
the
resolution
is
limited
by
circuit
comple
xity
,
high
po
wer
dissipation,
and
comparator
and
reference
mismatch.
T
o
reduce
hardw
are
com
ple
xity
,
po
wer
dissipation
and
die
area,
and
to
i
ncrease
the
resolution
b
ut
to
maintain
high
con
v
ersion
rates,
flash
con
v
erters
can
be
e
xtended
to
pipeline
[2],
delta-sigma
ADC
[3,
4],
or
successi
v
e
approximation
ADC
[5].
The
k
e
y
b
uilding
block
in
front-end
of
ADC
is
Sample
and
Hold
circuit
(S/H).
This
front-end
circuit
is
almost
ine
vita
b
l
e
in
some
types
of
ADC.
The
main
function
of
S/H
is
to
t
ak
e
analog
input
signal
samples
and
hold
its
v
alue
until
ADC
can
process
the
information.
In
other
w
ord,
the
accurac
y
and
the
speed
of
the
J
ournal
Homepage:
http://iaescor
e
.com/journals/inde
x.php/IJECE
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
4149
con
v
erter
is
strongl
y
dependent
on
performance
of
S/H,
because
this
circuit
pro
vide
the
information
which
will
be
processed
by
the
con
v
erter
.
The
architectures
of
S/H
can
roughly
be
di
vided
into
tw
o,
open-loop
and
closed-
loop
architectures.
The
main
dif
ference
between
them
is
that
in
closed-loop
architectures,
the
hold
capacitor
is
placed
in
a
feedback
loop,
at
least
in
hold
mode,
whereas
the
open-loop
one
has
no
feedback.
Moreo
v
er
,
the
characteristics
between
these
tw
o
architectures
are
mostly
dif
ferent.
The
open-loop
architectur
e
of
fer
the
simplicity
and
speed
solution,
ho
we
v
er
its
accurac
y
is
limited
by
distortion
arising
from
nonlinearity
of
the
switch
which
is
caused
by
its
signal
dependent
on-resistance
and
pedestal
error
which
is
caused
by
the
signal
dependent
channel
char
ge
injection
and
clock
feedthrough.
On
the
other
hand,
enclosing
the
capacitor
in
the
feedback
loop
on
the
close-l
oop
architecture
can
reduces
the
ef
fect
of
nonlinearity
and
signal-dependent
char
ge
injection
and
clock
feedthrough
from
the
MOS
switches,
of
fering
better
accurac
y
as
a
result.
Unfortunately
,
an
ine
vitable
consequence
of
the
use
of
feedback
is
conditionally
stability
problem.
Furthermore,
since
close-loop
architecture
uses
Op-Amp,
its
bandwidth
and
sle
w
rate
directly
limit
the
speed
of
the
S/H.
The
comple
xity
and
po
wer
consumption
of
the
Op-Amp
also
rise
another
problem.
In
order
to
maintain
the
simplicity
and
the
speed,
and
to
increase
the
accurac
y
of
S/H,
in
this
paper
a
ne
w
open-loop
CMOS
S/H
is
proposed.
The
proposed
circuit
consists
of
ne
w
bootstrap
circuit
to
o
v
ercome
channel
char
ge
injection
and
clock
feedthrough
signal
dependent
problem,
and
transmission
g
ate
(TG)
swi
tch
to
deal
with
on-resistance
problem.
In
this
paper
,
a
simple
theoretical
and
numerical
method
to
minimize
the
pedestal
error
is
also
presented.
The
rest
of
this
paper
is
or
g
anized
as
follo
ws.
Section
2
e
xplain
the
operat
ion
of
S/H,
especially
open-loop
S/H.
In
this
section,
channel
char
ge
injection
and
clock
feedthrough
mechanism
will
be
reanalyzed
in
detail.
Se
v
eral
pre
vious
e
xisting
techniques
related
to
open-loop
S/H
will
also
be
presented
in
this
section.
Section
3
presents
the
proposed
circuit
and
its
theoretical
analysis.
Section
4
presents
the
simulation
result
of
proposed
circuit
and
the
comparison
with
other
w
orks.
At
last,
the
conclusion
is
presented
in
section
5.
2.
OPEN-LOOP
SAMPLE
AND
HOLD
CIRCUIT
Simple
open-loop
S/H
circuit
consists
of
tw
o
main
part,
first
part
is
analog
switch
and
second
one
is
hold
capacitor
.
The
analog
switch
is
used
to
control
the
connection
between
signal-source
(input)
nod
e
and
data-
holding
(output)
node,
whereas
the
hold
capacitor
is
used
to
hold
the
data
in
output
node.
The
operation
of
S/H
circuit
tak
es
place
in
tw
o
phases:
sampling
and
hold.
When
the
clock
v
oltage
(
)
which
is
applied
to
the
g
ate
of
transistor
is
high,
transistor
is
on.
Channel
is
appearing
underneath
the
g
ate
and
connecting
drain
and
source
of
the
transistor
.
In
this
phase,
input
node
and
output
node
is
connected
and
sampling
function
is
performed.
After
the
switch
is
turned
of
f,
the
data
appearing
in
the
holding
(output)
node
will
be
held
until
the
ne
xt
operation
step
occurs,
this
phase
is
called
hold
phase.
In
the
transition
phase
between
sampling
and
hold,
the
channel
char
ge
disappears
through
either
the
source/drain
electrodes
or
substrate
electrodes.
Char
ge
which
disappears
through
source/drain
is
deposited
on
hold
capacitor
creating
an
error
component
to
the
sample
v
oltage.
This
phenomenon
is
called
channel
char
ge
injection.
In
an
MOS
transistor
it
is
also
kno
wn
that
it
has
parasitic
capacitance
that
is
formed
by
o
v
erlapping
between
g
ate
and
dif
fusion
(source
and
drain).
When
transistor
turns
of
f,
this
o
v
erlap
capacitance
also
flo
ws
the
char
ge
to
hold
capacitor
creating
another
error
component
to
sample
v
oltage.
This
phenomenon
is
called
clock
feed
through.
These
tw
o
mechanisms
are
the
main
sources
that
create
an
error
in
sample
v
oltage.
Some
researches
ha
v
e
been
done
and
published
re
g
arding
these
tw
o
mechanisms[6,
7].
2.1.
Channel
Char
ge
Injection,
Clock
F
eedthr
ough
and
On-Resistance
Pr
oblem
In
the
sampling
phase,
transistor
is
on
and
a
channel
e
xists
at
the
oxide-silicon
interf
ace.
This
phase
can
be
depicted
in
Figure.
1.
(a).
Assuming
V
in
=
V
out
,
the
total
char
ge
in
the
in
v
ersion
layer
(channel)
can
be
obtained
as
Q
ch
=
W
LC
ox
(
h
V
in
V
t
)
(1)
Q
ch
=
W
LC
ox
(
V
dd
V
in
V
t
)
(2)
where
W
is
channel
width,
L
is
channel
length,
C
ox
is
oxide
capacitance
per
unit
area,
h
is
the
high
le
v
el
of
clock
v
oltage,
and
V
t
is
threshold
v
oltage
of
the
transistor
.
In
man
y
application
the
high
le
v
el
of
clock
v
oltage
is
equal
to
supply
v
oltage
(
h
=
V
dd
).
Thus,
the
equation
(1)
can
be
re
written
as
(2).
High
Speed
and
Low
P
edestal
Err
or
Bootstr
apped
CMOS...
(Agung
Setiab
udi)
Evaluation Warning : The document was created with Spire.PDF for Python.
4150
ISSN:
2088-8708
(a)
(b)
Figure
1.
S/H
phases:
(a)
Sampling
phase
of
S/H
circuit,
(b)
On-of
f
transition
phase
of
S/H
circuit
When
the
switch
turns
of
f
(S/H
circ
uit
enter
hold
phase),
Q
ch
e
xits
through
the
source
and
drain
terminals
lik
e
sho
wn
in
Figure.
1.
(b).
The
char
ge
injected
to
left
side
of
Figure.
1.
(b)
is
absorbed
by
the
input
source,
creating
no
error
.
Whereas,
the
char
ge
injected
to
the
right
side
is
deposited
on
C
H
,
creating
an
error
in
the
output
node.
Assuming
that
the
amount
of
char
ge
which
flo
w
to
the
left
side
equal
to
the
one
which
flo
w
to
the
right
side,
it
is
obtained
that
the
amount
of
char
ge
causes
error
in
the
output
node
is
Q
c
h
/2.
Therefore,
the
error
v
oltage
caused
by
channel
char
ge
injection
then
can
be
written
as
follo
w
V
cci
=
W
LC
ox
(
V
dd
V
in
V
t
)
2
C
H
(3)
On
the
turning
of
f
process,
the
MOS
switch
also
couples
the
clock
transition
to
the
hold
capacitor
(
C
H
)
through
this
o
v
erlap
capacitance
(g
ate-drain
or
g
ate-source
o
v
erlap
capacitance).
The
coupling
current
that
flo
w
from
g
ate
to
drain/source
through
o
v
erlap
capacitance
causes
an
error
in
the
output
node.
The
error
v
oltage
caused
by
clock
feedthrough
can
be
written
as
follo
w
V
cf
t
=
L
ov
W
C
ox
L
ov
W
C
ox
+
C
H
h
(4)
Where
L
o
v
is
g
ate-drain
or
g
ate-source
o
v
erlap
length.
These
errors
are
the
main
source
of
accurac
y
problem
in
open-loop
S/H.
Error
caused
by
channel
char
ge
injection
is
more
dominant
compared
with
error
caused
by
clock
feedthrough,
because
the
length
of
o
v
erlap
capacitance
in
eq.
(4)
is
v
ery
small.
In
some
cases,
this
error
is
often
ne
glected.
The
other
problem
that
limit
the
accurac
y
of
open-loop
S/H
is
nonlinearity
.
This
nonlinearity
is
caused
by
signal
dependent
on-resistance
sho
wn
in
eq.
(5).
Where
is
mobility
of
the
electron.
From
the
equation,
it
also
can
be
inferred
that
the
switch
has
nar
ro
w
input
swing.
because
as
the
input
signal
equal
to
V
dd
V
t
,
the
on-resistance
become
infinity
.
R
on
=
1
C
ox
W
L
(
V
dd
V
in
V
t
)
(5)
IJECE
V
ol.
8,
No.
6,
December
2018
:
4148
–
4156
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
4151
2.2.
Open-Loop
S/H
Cir
cuit
Using
TG
Switch
The
simple
w
ay
to
decrease
the
error
and
nonlinearity
caused
by
channel
char
ge
injection,
clock
feedthrough
and
non-uniform
on-resistance
of
the
switch
is
by
using
TG
switch.
Figure
2
sho
ws
schematic
of
basic
S/H
cir
-
cuit
using
CMOS
switch.
The
switch
part
of
this
circuit
consist
of
tw
o
M
OS
transistors,
N
type
MOS
transistor
and
P
type
MOS
transistor
(TG
switch).
By
using
TG
switch,
the
problem
of
narro
w
input
v
oltage
swing
and
non-uniform
on-resistance
can
be
solv
ed.
Input
range
of
this
switch
is
nearly
0
V
-
V
dd
,
on-resistance
of
this
switch
is
also
relati
v
ely
uniform
compared
with
single
transis
tor
switch.
On-resistance
of
TG
switch
is
written
in
eq.
(6).
R
on
=
1
n
C
ox
W
n
L
n
(
V
dd
V
in
V
tn
)
+
p
C
ox
W
p
L
p
(
V
in
j
V
tp
j
)
(6)
Figure
2.
S/H
circuit
using
TG
switch
Since
the
TG
swit
ch
is
b
uilt
using
tw
o
type
MOS
transistors,
the
error
in
this
switch
is
also
caused
by
those
tw
o
transistor
.
And
as
well-kno
wn
that
the
characteristic
of
N
type
and
P
type
MOS
transistor
are
mutually
opposite.
Thus,
the
error
of
NMOS
and
PMOS
are
mutual
ly
compensate.
The
total
error
in
this
S/H
circuit
is
written
in
eq.
(7).
V
=
1
2
C
H
C
ox
[
W
p
L
p
(
V
in
j
V
tp
j
)
W
n
L
n
(
V
dd
V
in
V
tn
)]
+
L
ov
p
W
p
L
ov
n
W
n
L
ov
n
W
n
C
ox
+
L
ov
p
W
p
C
ox
+
C
H
C
ox
h
(7)
Where
subs
cript
n
and
p
refer
to
N
type
and
P
type
MOS
transistor
,
respecti
v
ely
.
The
equations
used
for
modeling
hold
error
in
this
paper
is
basic
model,
ne
glecting
body
ef
fect
and
g
ate/clock
v
oltage
f
alling
rate.
The
first
term
in
this
equation
is
the
error
caused
by
channel
char
ge
injection.
This
term
is
dominant
term.
The
second
term
is
error
caused
by
clock
fe
edthrough.
This
term
is
less
dominant
and
can
be
ne
glected
in
some
application
with
less
accurac
y
consideration.
Theoretically
,
the
performance
of
open-loop
S/H
circuit
using
TG
switch
is
better
than
the
other
one
with
single
MOS
transistor
.
Ho
we
v
er
,
in
the
high
speed
and
high
accurac
y
application,
the
use
of
open-loop
S/H
circuit
with
TG
swi
tch
is
not
recommended.
Because
the
ef
fect
of
channel
char
ge
injection,
clock
feedthrough
and
on-resistance
signal
dependent
is
still
v
ery
significant
to
accurac
y
de
gradation.
T
o
o
v
ercome
this
problem,
man
y
researchers
de
v
elop
and
propose
ne
w
techniques.
The
use
of
dummy
transistor
to
eliminate
the
ef
fect
of
channel
char
ge
injection
and
clock
feedthrough
has
been
reported.
Ho
we
v
er
,
the
performance
of
dummy
transistor
is
limited
by
the
transistor
mismatch
and
unbalance
impedance
at
drain
and
source
terminal
of
the
switch.
The
other
technique
is
bottom
plate
sampling.
Recently
,
the
impro
v
ement
of
bottom
plate
sampling
is
reported
in
[8,
9].
This
technique
sho
ws
decent
performance
to
decrease
char
ge
injection
and
cl
ock
feedthrough
ef
fect,
b
ut
the
comple
x
clocking
phase
in
this
technique
rises
another
problem
in
system
comple
xity
.
Se
v
eral
other
techniques
al
so
ha
v
e
been
reported,
such
as
the
use
of
current
con
v
e
yor
as
analog
switch,
current
controlled
High
Speed
and
Low
P
edestal
Err
or
Bootstr
apped
CMOS...
(Agung
Setiab
udi)
Evaluation Warning : The document was created with Spire.PDF for Python.
4152
ISSN:
2088-8708
current
mirror
switching,
distrib
uted
S/H,
substrate-biasing-ef
fect
attenuated
T
switch
[10],
cross
couple
switch
capacitor
netw
ork,
of
fset
cancellation
replica
cir
cuit
[11],
bootstrapping
techniques
[12],
and
other
techniques
[13,
14,
15,
16].
F
or
open-loop
S/H
ci
rcuit
the
bootstrapping
technique
is
a
suitable
one,
this
technique
k
eeps
the
g
ate-source
v
oltage
of
sampling
transistor
fix
at
particular
v
alue.
This
approach
k
eeps
the
on-resistance
constant
and
thus
impro
v
e
the
switch
linearity
.
By
k
eeping
the
g
ate-source
v
oltage
fix,
it
also
decreases
t
he
channel
char
ge
injection
and
clock
feedthrough
signal
dependent.
3.
PR
OPOSED
S/H
CIRCUIT
T
o
solv
e
the
problems
presented
in
section
2.,
a
ne
w
bootstrapped
S/H
circuit
with
TG
switch
is
pro-
posed.
As
depicted
in
Figure.
3,
unlik
e
the
common
bootstrap
circuit
[12],
the
proposed
circuit
is
made
up
of
CMOS
TG
switch
and
no
v
el
bootstrap
circuit
structure
for
each
transistor
in
TG
s
witch
(NMOS
bootstrap
circuit
and
PMOS
bootstrap
circuit).
The
proposed
circuit
is
operated
in
dif
ferential
mode,
b
ut
for
simplicity
,
Figure.
3
sho
ws
only
single
input
mode
circuit.
CMOS
TG
switch
is
formed
by
M
s
1
and
M
s
2
,
while
C
1
,
M
1
5
and
C
2
,
M
6
10
form
NMOS
and
PMOS
bootstrap
circuits,
respecti
v
ely
.
Figure
3.
Proposed
S/H
circuit
These
circuits
are
controlled
by
and
which
are
non-o
v
erlapping
clocks
with
opposite
phases.
The
operation
principles
of
the
proposed
circuit
is
e
xplained
as
follo
ws.
When
is
high,
(
=
1
,
=
0
),
in
NMOS
bootstrap
circuit,
M
1
3
are
on
and
M
4
5
are
of
f,
cause
V
dd
is
applied
at
top
plate
of
capacitor
C
1
,
and
since
M
2
is
on,
the
output
of
this
circuit
which
is
connected
to
the
g
ate
o
f
NMOS
in
TG
switch
is
connected
to
ground
(
V
g
n
=
0
).
While
in
PMOS
bootstrap
circuit,
M
6
8
are
on
and
M
9
10
are
of
f.
Thus,
V
dd
is
applied
at
top
plate
of
capacitor
C
2
,
and
since
M
7
is
on,
the
output
of
this
circuit
which
is
connected
to
the
g
ate
of
PMOS
in
TG
switch
is
connected
to
V
dd
(
V
g
p
=
V
dd
).
In
this
phase,
the
circuit
is
in
hold
phase
as
depicted
in
Figure.
4.
(a)
(b)
Figure
4.
Hold
phase
in
bootstrap
circuit:
(a)
NMOS
bootstrap,
(b)
PMOS
bootstrap
IJECE
V
ol.
8,
No.
6,
December
2018
:
4148
–
4156
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
4153
When
is
lo
w
,
(
=
0
,
=
1
),
in
NMOS
bootstrap
circuit,
M
1
3
are
of
f
and
M
4
5
are
on,
cause
the
bottom
plate
of
capacitor
C
1
connects
to
V
in
and
its
top
plate
connects
to
V
g
n
.
Thus,
the
output
of
this
circuit,
V
g
n
equal
to
V
in
+
V
dd
.
While
in
PMOS
bootstrap
circuit
,
M
6
8
are
of
f
and
M
9
10
are
on,
cause
the
top
plate
of
capacitor
C
2
connects
to
V
in
and
its
bottom
plate
connects
to
V
g
p
.
Therefore,
the
output
of
the
circuit,
V
g
p
equal
to
V
in
V
dd
.
In
this
phase,
the
circuit
is
in
sampling
phase
as
depicted
in
Figure.
5.
Based
on
the
operation
principles
e
xplanation,
the
output
of
NMOS
and
PMOS
bootstrap
circuits
can
be
written
in
Eqs.
(8)
and
(9),
respecti
v
ely
.
V
g
n
=
(
V
in
+
V
dd
;
in
sampling
phase
0
;
in
hold
phase
(8)
(a)
(b)
Figure
5.
Sampling
phase
in
bootstrap
circuit:
(a)
NMOS
bootstrap,
(b)
PMOS
bootstrap
V
g
p
=
(
V
in
V
dd
;
in
sampling
phase
V
dd
;
in
hold
phase
(9)
By
using
Eqs.
(8)
and
(9),
the
on-resistanc
e
and
the
total
error
of
the
proposed
circuit
can
be
written
in
Eqs.
(10)
and
(11),
respecti
v
ely
.
R
on
=
1
n
C
ox
W
n
L
n
(
V
dd
V
tn
)
+
p
C
ox
W
p
L
p
(
V
dd
j
V
tp
j
)
(10)
V
=
1
2
C
H
C
ox
[
W
p
L
p
(
V
dd
j
V
tp
j
)
W
n
L
n
(
V
dd
V
tn
)]
+
L
ov
p
W
p
(2
V
dd
V
in
)
L
ov
n
W
n
(
V
dd
+
V
in
)
L
ov
n
W
n
C
ox
+
L
ov
p
W
p
C
ox
+
C
H
C
ox
(11)
Equation
(10)
sho
ws
that
the
on-resistance
of
proposed
S/H
circuit
is
independent
t
o
input
signal.
Al-
though
it
is
well
kno
wn
that
the
threshold
v
olt
age
of
transistor
is
input
signal
dependent,
it
can
be
ne
glected
because
its
v
alue
v
ariation
is
small
enough.
By
this
condition,
the
linearity
of
S/H
can
be
increased
and
the
distortion
can
be
reduced.
This
equation
also
sho
ws
that
the
o
v
erdri
v
e
v
oltage
of
each
transistor
in
TG
switch
increase
by
V
in
.
It
means
the
v
alue
of
on-resistance
becomes
smaller
and
it
can
increase
the
switching
speed.
Equation
(11)
sho
ws
that
the
total
error
dominant
term
(error
caused
by
channel
char
ge
injection)
is
independent
to
input
signal
V
in
.
Although
the
second
t
erm
(error
caused
by
clock
feedthrough)
becomes
in-
put
signal
dependent,
this
technique
still
gi
v
es
the
adv
antages.
Because
the
input
signal
dependent
shifts
from
dominant
term
to
less
dominant
term,
so
that
the
total
input
signal
dependent
can
decrease.
4.
SIMULA
TION
RESUL
TS
The
performance
of
the
proposed
circuit
w
as
e
v
aluated
using
HSPICE
with
1P
,
5M,
3-well,
0.18-m
CMOS
process
(BSIM3v3.2
LEVEL53).
Figure
6
sho
ws
the
input
and
output
w
a
v
eform
of
bootstrap
circuit
for
a
sinusoidal
input
of
1
V
peak-to-peak
at
50
MHz
with
a
1
GHz
sampling
clock.
From
this
simul
ation
result
it
can
High
Speed
and
Low
P
edestal
Err
or
Bootstr
apped
CMOS...
(Agung
Setiab
udi)
Evaluation Warning : The document was created with Spire.PDF for Python.
4154
ISSN:
2088-8708
be
kno
wn
that
in
the
sampling
phase
the
circuit
can
track
the
input
(dashed
line)
v
oltage
and
gi
v
e
the
output
(solid
line)
of
V
in
+
V
dd
for
NMOS
bootstrap
circuit
and
V
in
V
dd
for
PMOS
bootstrap
circuit.
Figure
7
(a)
sho
ws
the
transient
response
of
the
proposed
S/H
circuit
for
50
MHz
sinusoidal
1
V
peak-to-peak
dif
ferential
input
signal
with
a
1
GHz
sampling
clock.
The
common
mode
(CM)
le
v
el
of
dif
ferential
signal
is
0.25
V
.
The
pedestal
error
as
the
function
of
dif
ferential
input
v
oltage
is
sho
wn
in
Figure.
7
(b).
F
or
50
MHz
sinusoidal
1
V
peak-to-
peak
dif
ferential
input
signal
with
a
1
GHz
sampling
clock,
the
maximum
absolute
v
alue
and
root-means-square
(RMS)
v
alue
of
pedestal
error
are
2.75
mV
and
1.72
mV
,
respecti
v
ely
with
0.542
mW
po
wer
consumption.
(a)
(b)
Figure
6.
The
input
and
output
w
a
v
eform
of
bootstrap
circuit
for
a
sinusoidal
input
of
1
V
peak-to-peak
at
50
MHz
with
a
1
GHz
sampling
clock:
(a)
NMOS
bootstrap
circuit,
(b)
PMOS
bootstrap
circuit
(a)
(b)
Figure
7.
Simulation
results
of
proposed
S/H
circuit
for
50
MHz
sinusoidal
1
V
peak-to-peak
dif
ferential
input
signal
with
a
1
GHz
sampling
clock:
(a)
Input
and
output
w
a
v
eform,
(b)
Pedestal
error
Figure
8
sho
ws
the
sampled
signal
spectrum
of
50
MHz
sinusoidal
1
V
peak-to-peak
dif
ferential
input
signal
with
a
1
GHz
sampling
clock.
From
the
analysis,
in
the
Nyquist
bandwidth
the
proposed
circuit
has
performances
of
90.87
dB
SNR,
73.50
SIN
AD/SNDR
which
is
equal
to
11.92
bits
ENOB,
-73.58
dB
THD,
and
73.95
dB
SFDR.
Furthermore,
the
simulation
of
the
circuit
in
v
arious
sampling
frequencies
and
input
frequencies
are
done.
The
input
frequenc
y
v
aries
from
10
MHz
to
50
MHz
in
the
step
of
10
MHz
while
the
sample
frequenc
y
v
aries
from
300
MHz
to
1
GHz
in
the
step
of
100
MHz.
From
this
condition
the
proposed
circuit
has
a
v
erage
performances
of
69.64
dB
SNR,
64.50
SIN
AD/SNDR
which
is
equal
to
10.42
bits
ENOB,
-77.59
THD,
and
69.64
dB
SFDR.
At
last,
a
comparison
of
main
performance
of
the
proposed
circuit
with
other
w
orks
is
summarized
in
T
able.
1.
In
general,
the
proposed
circuit
s
ho
ws
better
performance
than
other
w
ork.
Compared
with
the
same
bootstrapping
technique
[12],
the
proposed
circuit
also
sho
ws
better
SNDR
and
higher
sampling
rate.
IJECE
V
ol.
8,
No.
6,
December
2018
:
4148
–
4156
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
4155
Figure
8.
Sampled
signal
spectrum
of
50
MHz
sinus
oidal
1
V
peak-to-peak
dif
ferential
input
signal
with
a
1
GHz
sampling
clock
T
able
1.
Comparison
of
main
performance
of
the
proposed
circuit
with
other
w
orks
P
arameter
Proposed
[11]
[13]
[14]
[15]
[16]
[10]
[9]
[8]
[12]
Sampling
rate
(MS/s)
1000
500
40
200
330
200
100
500
250
280
Input
frequenc
y
(MHz)
50
10
-
40
80
-
10
220
20
7
Input
Amplitude
(V)
1
0.8
1.4
0.8
1.2
2
2
1.6
1.6
0.5
SNR
(dB)
90.87
-
67
-
-
-
-
-
-
-
SIN
AD/SNDR
(dB)
73.50
60.50
-
45
-
-
85.5
76
-
57.01
ENOB
(bits)
11.92
9.8
9
7.2
11
12
13.9
12.33
14
9.18
THD
(dB)
-73.58
-60.5
-56
-
-68.3
-
-
-
-
-
SFDR
(dB)
73.95
69
57
60
-
87
92.87
-
80
-
Pedestal
Error
(mV)
<
2.75
<
4.9
-
-
<
0.8
-
-
-
-
-
Po
wer
consumption
(mW)
0.542
6
0.5
22
26.4
-
-
-
-
0.88
10
3
CMOS
T
echnology
(nm)
180
90
130
180
350
350
130
350
350
90
Refer
ences
[1]
M.
Marufuzzaman,
S.
Z.
Abidin,
M.
B.
I.
Reaz,
and
L.
F
.
Rahman,
“Design
of
3-bit
ADC
in
0.18
m
CMOS
process,
”
TELK
OMNIKA
Indonesian
J
ournal
of
Electrical
Engineering
,
v
ol.
12,
no.
7,
pp.
5197–5203,
2014.
[2]
Y
.-S.
Shu
and
B.-S.
Song,
“
A
15-bit
linear
20-MS/s
pipelined
ADC
digitally
calibrated
with
signal-
dependent
dithering,
”
IEEE
J
.
Solid-State
Cir
cuits
,
v
ol.
43,
no.
2,
pp.
342–350,
2008.
[3]
Y
.
F
an,
Y
.
Huijing,
and
L.
Gang,
“
A
high
performance
si
gma-delta
ADC
for
audio
decoder
chip,
”
TELK
OM-
NIKA
,
v
ol.
11,
no.
11,
pp.
6570–6576,
2013.
[4]
S.
Shu-jing
and
Z.
Hai-li,
“The
study
and
achie
ving
of
high-precision
data
acquisition
based
on
ADC,
”
TELK
OMNIKA
,
v
ol.
11,
no.
8,
pp.
4453–4460,
2013.
[5]
J.
Y
.
Lin
and
C.
C.
Hsieh,
“
A
0.3
V
10-bit
SAR
ADC
with
first
2-bit
guess
in
90-nm
CMOS,
”
IEEE
T
r
ans-
actions
on
Cir
cuits
and
Systems
I:
Re
gular
P
aper
s
,
v
ol.
64,
no.
3,
pp.
562–572,
2017.
[6]
B.
Sheu,
J.
Shieh,
and
M.
P
atil,
“Modeling
char
ge
injection
in
MOS
analog
switches,
”
IEEE
T
r
ansactions
on
Cir
cuits
and
Systems
,
v
ol.
CAS-34,
no.
2,
pp.
214–216,
1987.
[7]
B.
Sheu
and
C.
Hu,
“Switch-induced
error
v
oltage
on
a
switched
capacitor
,
”
IEEE
J
ournal
of
Solid-State
cir
cuits
,
v
ol.
SC-19,
no.
4,
pp.
519–525,
1984.
[8]
T
.
Moradi
Khanshan,
M.
Nematzade,
K.
Hadidi,
A.
Khoei,
Z.
D.
K
oozehkanani,
and
J.
Sobhi,
“V
ery
linear
open-loop
CMOS
sample-and-hold
structure
for
high
precision
and
high
speed
ADCs,
”
Analo
g
Inte
gr
ated
High
Speed
and
Low
P
edestal
Err
or
Bootstr
apped
CMOS...
(Agung
Setiab
udi)
Evaluation Warning : The document was created with Spire.PDF for Python.
4156
ISSN:
2088-8708
Cir
cuits
and
Signal
Pr
ocessing
,
v
ol.
88,
no.
1,
pp.
23–30,
2016.
[9]
M.
Mousazadeh,
“
A
highly
linear
open-loop
high-speed
CMOS
sample-and-hold,
”
Analo
g
Inte
gr
ated
Cir
-
cuits
and
Signal
Pr
ocessing
,
v
ol.
90,
no.
3,
pp.
703–710,
2017.
[10]
K.
Ding,
K.
Cai,
and
Y
.
Han,
“Design
of
a
high-speed
sample-and-hold
circuit
using
a
substrate-biasing-
ef
fect
attenuated
T
switch,
”
Micr
oelectr
onics
J
ournal
,
v
ol.
41,
no.
12,
pp.
809
–
814,
2010.
[11]
M.
Azarmehr
,
R.
Rashidzadeh,
and
M.
Ahmadi,
“High-speed
CMOS
track-and-hold
with
an
of
fset
can-
cellation
replica
circuit,
”
in
Pr
oceedings
of
2010
IEEE
International
Symposium
on
Cir
cuits
and
Systems
,
pp.
4297–4300,
2010.
[12]
T
.
B.
Nazzal
and
S.
A.
Mahmoud,
“Lo
w-po
wer
bootstrapped
sample
and
hold
circuit
for
analog-to-digital
con
v
erters,
”
in
2016
IEEE
59th
International
Midwest
Symposium
on
Cir
cuits
and
Systems
(MWSCAS)
,
pp.
1–4,
2016.
[13]
F
.
Centurelli,
P
.
Monsurro,
S.
Pennisi,
G.
Scotti,
and
A.
T
rifiletti,
“Design
solutions
for
sample-and-hold
circuits
in
CMOS
nanometer
technologies,
”
IEEE
T
r
ansactions
on
Cir
cuits
and
Systems
II:
Expr
ess
Briefs
,
v
ol.
56,
no.
6,
pp.
459–463,
2009.
[14]
S.
Jiang,
M.
A.
Do,
K.
S.
Y
e
o,
and
W
.
M.
Lim,
“
An
8-bit
200-MSample/s
pipelined
ADC
with
mix
ed-
mode
front-end
S/H
circuit,
”
IEEE
T
r
ansactions
on
Cir
cuits
and
Systems
I:
Re
gular
P
aper
s
,
v
ol
.
55,
no.
6,
pp.
1430–1440,
2008.
[15]
T
.-S.
Lee,
C.-C.
Lu,
and
C.-C.
Ho,
“
A
330MHz
11
bit
26.4mW
CMOS
lo
w-hold-pedestal
fully
dif
feren-
tial
track-and-hold
circuit,
”
in
2008
IEEE
International
Symposium
on
VLSI
Design,
A
utomation
and
T
est
(VLSI-D
A
T)
,
pp.
144–147,
2008.
[16]
M.
Y
ousefi,
Z.
D.
K
oozeKanani,
A.
Rostami,
J.
Sobhi,
and
M.
H.
Zarifi,
“
A
fle
xible
sample
and
hold
circuit
for
data
con
v
erter
applications,
”
in
2008
IEEE
Re
gion
8
International
Confer
ence
on
Computational
T
ec
hnolo
gies
in
Electrical
and
Electr
onics
Engineering
,
pp.
318–321,
2008.
IJECE
V
ol.
8,
No.
6,
December
2018
:
4148
–
4156
Evaluation Warning : The document was created with Spire.PDF for Python.