Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
6, N
o
. 4
,
A
ugu
st
2016
, pp
. 14
34
~
1
440
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
4.1
010
3
1
434
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
FPGA B
a
s
e
d Control Method for Three P
h
ase BL
DC Mot
o
r
Suneeta
1
,
R
S
r
i
n
i
vas
an
1
, Ram Saga
r
2
1
Departem
ent
of
El
ectron
i
cs and Com
m
unication E
ngineering, Vem
a
na In
stitu
te of
Technolog
y
2
Founder Director, ARIES Nainital
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Ja
n
4, 2016
Rev
i
sed
Mar
12
, 20
16
Accepted
Mar 26, 2016
This paper
intro
duces a good method which
is helpful
to assist in the desig
n
and control of
cos
t
effe
ctiv
e, e
ffici
ent Brus
hle
s
s
Direct Current (BLDC)
m
o
tors. Speed Control of BLD
C
m
o
to
r using PIC microcontrollers requires
more hardware, and with the availa
bility
of
FPGA versatile features
m
o
tivated
to d
e
v
e
lop
a
cos
t
ef
fec
tive
and
rel
i
abl
e
control
with v
a
ri
able
s
p
ee
d
range. In this p
a
per,
an algo
rith
m wh
ich uses the Resolver
signa
ls captur
e
d
from the motor is developed with the help
of Resolver to Digital converters.
The program has been written usi
ng VHDL.
This program generates the
firing pulses req
u
ired to driv
e th
e MOSF
ETs of
three ph
ase fully controlled
bridge
converter
driven
b
y
dr
iver
s. Then
th
e prog
ram has been lo
aded on
th
e
Spartan- 3 FPGA device and tested on the 30V, 2000 rpm B
L
DC motor
which can make the motor run at constan
t
speed ranging from 10 to 2000
rpm. The proposed hardware
and
the program are found to be ver
y
good and
efficient.
The res
u
lts ar
e good
co
mpar
e to
PIC Microcontro
ller
bas
e
d design
.
Keyword:
BLDC
FPGA
MOSFET
RDC
VH
DL
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Suneeta,
Depa
rt
em
ent
of El
ect
r
oni
cs
a
n
d
C
o
m
m
uni
cat
i
on E
n
gi
nee
r
i
n
g
,
Vem
a
n
a
In
stitute o
f
Techno
log
y
,
N
o
1 Mah
a
y
o
gi V
e
m
a
n
a
Ro
ad
,K
or
am
an
g
a
la, Bang
alor
e-560
013
,K
arn
a
taka, Ind
i
a.
Em
a
il: su
n
itahav
e
ri@g
m
a
il.c
o
m
1.
INTRODUCTION
Perm
anent
m
a
gnet
b
r
ushl
ess
dc (B
LDC
)
m
o
t
o
rs are use
d
i
n
wi
de a
ppl
i
cat
i
on du
e t
o
t
h
ei
r p
o
w
e
r
density and ease of control.
More
ove
r, the
m
achines
hav
e
hi
gh e
ffi
ci
en
cy
over
a wi
de speed
range. The
h
i
gh
ly efficien
t conv
en
tio
nal DC m
o
to
rs are su
ita
bl
e for va
rious applications
beca
use
of their
characte
r
istics [1]. T
h
ey require comm
utato
r
s and brushe
s, f
o
r
conv
er
si
on
of
d
c
to ac
whic
h are s
u
bject to
wear an
d re
q
u
i
re
m
a
i
n
t
e
nanc
e. Thi
s
dra
w
ba
ck of c
o
n
v
en
tio
n
a
l DC m
o
to
rs m
a
k
e
s to
sh
ift to
BLDC m
o
to
rs
whic
h are
electronically commutated.
Recent efficienc
y
standa
rds
in
a
ppliance
s
, has forced
applianc
e
m
a
nufact
ure
r
s
t
o
m
i
grat
e t
o
B
L
DC
m
o
t
o
rs
i
n
t
h
ei
r a
p
pl
i
cat
i
ons.
I
n
vi
e
w
o
f
t
h
ese e
n
orm
ous a
p
pl
i
cat
i
ons,
researc
h
er
s st
a
r
t
e
d
de
vel
o
pi
n
g
m
e
t
hods
f
o
r
effi
ci
ent
use
o
f
t
h
ese
m
o
t
o
rs
i
n
di
ve
rsi
f
i
e
d
fi
el
ds.
To
m
e
nt
i
on a
few:
Ji
an
we
n Sha
o
N
o
l
a
n et
.al
[2]
has
dev
e
l
ope
d a n
ovel
m
i
crocont
rol
l
er-
b
ase
d
Sens
or l
e
ss b
r
ushl
e
ss DC
(B
LDC
)
m
o
t
o
r d
r
i
v
e
fo
r a
u
t
o
m
o
t
i
v
e fue
l
pum
ps i
n
2
0
0
3
.
Al
s
o
, t
h
ey
have
de
ve
l
ope
d a
n
Im
pro
v
e
d
Micr
o
c
on
tro
ller
-
B
ased
Sen
s
o
r
less Bru
s
h
l
ess D
C
(
B
LD
C
)
Mo
to
r Dr
iv
e for
A
u
t
o
m
o
tiv
e A
p
p
licatio
n
s
, i
n
2
006
[3]
.
Ni
kol
ay
S
a
m
o
y
l
enko
[4]
st
udi
ed t
h
e
D
y
nam
i
c perf
or
m
a
nce of B
r
us
hl
ess DC
m
o
tors
wi
t
h
u
n
b
al
ance
d
Hal
l
sens
o
r
s.
P.
Deve
n
d
ra
e
t
.al
[5]
has
de
vel
o
ped
a m
i
croc
o
n
t
r
ol
l
e
r
-
b
a
sed
c
o
nt
rol
o
f
t
h
ree p
h
ase br
ushl
es
s
DC (BL
D
C)
, i
n
2011.
To the e
x
tent t
h
e aut
h
ors
have su
rveyed
not m
u
ch work
has
been
re
po
rt
ed on FP
GA dri
v
e
n
R
e
sol
v
e
r
base
d B
L
DC
m
o
t
o
rs. He
nce
i
n
t
h
i
s
pa
per
,
an al
g
o
r
i
t
h
m
for
res
o
l
v
e
r
bas
e
d F
P
G
A
dri
v
en B
L
DC
m
o
tors
are
p
r
esen
ted. Effectiv
en
ess
of the wo
rk
is
s
p
eci
fied t
h
rough
ha
rdware
realization.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
FPGA
Based
Contr
o
l Method for Three
Phase B
L
DC
Mot
o
r (Suneeta)
1
435
2.
REVIEW
OF
BLDC MOT
O
R CO
NTR
O
L
SCHE
MES
The c
o
nt
rol
sc
hem
e
s of B
L
D
C
m
o
t
o
r are m
a
in
ly classified in
fo
llowing
t
w
o ways
•
Sens
or
bas
e
d
c
ont
rol
•
Sens
or
l
e
ss c
o
nt
r
o
l
In sensor
b
a
sed
con
t
ro
l, a
Hall sen
s
o
r
is
used
wh
ich d
e
t
ects th
e
po
sitio
n
o
f
t
h
e
ro
to
r m
a
g
n
e
t and
g
i
v
e
s a sign
al wh
ich
is u
s
ed
to
g
i
v
e
ap
propriate ex
citatio
n to
th
e stato
r
wind
ing
.
Hall
sen
s
o
r
work
s
o
n
Hall
Effect whic
h s
t
ates that when a curre
nt carrying conduct
o
r is placed in ma
gnetic field, it exerts a trans
v
ers
e
fo
rce
on
t
h
e c
o
nd
uct
o
r.
The se
ns
or l
e
ss dri
v
e p
r
i
n
c
i
pl
e i
s
based
on t
h
e det
ect
i
on
of t
h
e r
o
t
o
r
po
si
t
i
on
us
i
ng
vari
ous
t
echni
q
u
es o
n
e
of w
h
i
c
h i
s
t
h
e EM
F det
ect
i
on. T
h
ere
are vari
ous m
e
t
h
o
d
s f
o
r p
o
s
i
t
i
on and
vel
o
ci
t
y
est
i
m
a
ti
on
bas
e
d
on
t
h
e i
n
d
u
c
e
d B
a
c
k
EM
F
det
ect
i
o
n
.
Th
ere are two
m
a
in
ways t
o
m
o
n
ito
r ab
so
lu
te
sha
f
t position those are encoders and res
o
lve
r
s.
Resolve
r
s are t
h
e ol
der technology, bu
t th
eir rugg
ed
n
e
ss allo
ws th
em
to
survive where othe
r
de
vices
coul
d
not
. E
n
c
ode
rs,
bei
n
g i
nhe
re
n
t
l
y
di
gi
t
a
l
,
hav
e
becom
e
t
h
e m
e
t
hod
of c
h
o
i
ce for m
o
st
appl
i
cat
i
o
ns, b
u
t
t
h
ey
can'
t
survive
wher
e
a re
sol
v
er
can.
A res
o
lver is a
n
electrom
echanical device wi
th a
m
echanical design sim
i
la
r to a
m
o
tor. It
contains a
r
o
t
o
r
w
ith
on
e
o
r
t
w
o
o
r
t
h
ogon
al pr
im
ar
y w
i
n
d
i
n
g
s and
a st
ato
r
w
ith
two
or
tho
gon
al secon
d
a
r
y
w
i
n
d
i
n
g
s. The
vol
t
a
ge
i
n
one
st
at
or wi
n
d
i
n
g va
ri
es as t
h
e
si
ne o
f
t
h
e s
h
aft
an
gl
e an
d t
h
e ot
her
va
ri
es as t
h
e co
si
ne.
Thi
s
reso
l
v
er
u
s
es a ro
tary tran
sformer to
ex
cite th
e prim
ar
y
,
so no
b
r
us
hes a
r
e
neede
d
.
A
n
ac
vol
t
a
ge
i
s
ap
pl
i
e
d t
o
the rot
o
r a
n
d the voltage induced i
n
each stator wi
ndi
ng
depe
nds on the
position of t
h
e sha
f
t. Resolver-to-
d
i
g
ital conv
ert
e
rs can
b
e
u
s
ed to
in
terpo
l
ate resu
lts.
These R/D c
o
nverters give a
n
absol
u
te or i
n
crem
en
tal o
u
t
pu
t with
a reso
l
u
tio
n
o
f
up
to
4
096
coun
ts
per
re
v
o
l
u
t
i
o
n.
The
res
o
l
v
er
si
gnal
s
are
l
o
w
ban
d
w
i
d
t
h
am
pl
i
t
ude m
odul
at
ed
si
ne
w
a
ves.
T
h
e
reso
l
v
er t
o
di
gi
t
a
l
con
v
ert
e
r per
f
o
rm
s t
w
o basi
c f
u
nct
i
o
ns:
dem
odul
at
i
on
of t
h
e
resol
v
er f
o
rm
at si
gnal
s
t
o
rem
ove
t
h
e
carri
er
, a
n
d
an
gl
e det
e
rm
i
n
ati
on t
o
pr
ovi
de
a di
gi
t
a
l
rep
r
esent
a
t
i
o
n
o
f
t
h
e r
o
t
o
r a
n
gl
e. Th
e m
o
st
po
pul
a
r
m
e
t
hod
o
f
per
f
o
rm
i
ng t
h
ese
f
unct
i
o
ns
i
s
cal
l
e
d
rat
i
o
m
e
t
r
i
c
tracki
n
g
co
n
v
er
si
on
.
Since the
res
o
lver s
econdary
signals
represe
n
t the si
ne and cosine
of
th
e
ro
tor ang
l
e, t
h
e
ratio
of the
si
gnal
am
pl
i
t
udes i
s
t
h
e t
a
ng
ent
o
f
t
h
e
rot
o
r
an
gl
e. T
h
us t
h
e r
o
t
o
r
a
ngl
e
θ
, is th
e arc tan
g
en
t of t
h
e si
n
e
sig
n
a
l
di
vi
de
d by
t
h
e
cosi
ne si
g
n
al
. The rat
i
o
m
e
t
r
ic t
r
acki
n
g
conv
erter
p
e
rforms an
i
m
p
licit
a
r
c tan
g
e
n
t
calcu
lation
o
n
th
e
ratio
of
th
e reso
lv
er si
gn
als
b
y
fo
rci
n
g a coun
ter t
o
track
th
e po
sition
o
f
th
e
reso
lver.
3.
FPGA
BA
SED
CO
NTROL
SC
HEME
The pr
o
p
o
s
ed
cont
rol
sc
hem
e
f
o
r
B
L
DC
m
o
t
o
r
co
nt
r
o
l
usi
n
g V
HDL
codi
ng
o
n
S
p
a
r
t
a
n 3 FP
GA
devi
ce i
s
sh
o
w
n i
n
t
h
e
Fi
g
u
re
1.
Fi
gu
re 1.
FP
G
A
base
d
C
o
nt
r
o
l
Th
e driv
e to
th
e MOSFETS in
th
e in
v
e
rter circu
it is g
i
v
e
n
b
y
th
e Sp
artan
3
FPGA.
Th
e reso
lv
er
sig
n
a
ls
fro
m
t
h
e m
o
to
r are
fed
as inpu
ts to th
e RDC. R
D
C p
r
o
v
i
d
e
s
p
o
sitio
n
of th
e m
o
tor in
d
i
g
ital form
.
B
a
sed o
n
R
D
C
posi
t
i
on a
n
d t
h
e di
rect
i
o
n
of r
o
t
a
t
i
on
of
t
h
e
m
o
t
o
r, t
h
e corre
sp
o
ndi
n
g
gat
e
d
r
i
v
e i
s
m
a
de
active by the
FPGA a
nd
fe
d to the stator
of t
h
e BL
DC
m
o
to
r. Th
e commu
tatio
n
sequ
en
ce
fo
r
ro
tat
i
n
g
th
e
m
o
t
o
r i
n
cl
oc
k
wi
se
di
rect
i
o
n
whe
n
vi
ewe
d
f
r
om
t
h
e n
o
n
dr
i
v
i
n
g
en
d i
s
gi
ven
i
n
t
h
e Ta
bl
e 1.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE
Vo
l. 6
,
N
o
. 4
,
Au
gu
st 2
016
:
14
34
–
1
440
1
436
Tabl
e
1. T
h
e
S
i
x St
at
es a
n
d
C
o
i
l
C
u
r
r
e
n
t
Di
r
ect
i
ons
State
A
B
C
State 1
Positive
Nil
Negative
State 2
Positive
Negative
Nil
State 3
Nil
Negative
Positive
State 4
Negative
Nil
Positive
State 5
Negative
Positive
Nil
State 6
Nil
Positive
Negative
Based
on
th
e RDC in
pu
t to
th
e FPGA, th
e co
rre
sp
o
ndi
ng
M
O
SFETs ar
e
m
a
de act
i
v
e
and c
u
r
r
e
n
t
fl
o
w
s t
h
r
o
ug
h
t
w
o
wi
n
d
i
n
gs
and t
h
e ot
her
wi
n
d
i
n
g i
s
i
n
a
c
t
i
v
e and
he
nc
e com
m
ut
at
i
o
n
i
s
do
ne el
ect
r
oni
cal
l
y
with
th
e use
o
f
a FPGA.
Exci
t
i
ng t
h
e c
o
rres
p
on
di
n
g
wi
ndi
ng
base
d
on
t
h
e R
D
C
si
gn
al
, t
h
e m
o
t
o
r i
s
com
m
ut
at
ed and i
s
m
a
d
e
to
run
at th
e
desired
sp
eed. In
itially
irresp
ectiv
e o
f
th
e
ro
to
r
p
o
sitio
n
,
t
h
e wind
ing
s
are ex
cited
in
th
e g
i
v
e
n
sequ
en
ce and
o
n
ce t
h
e m
o
to
r starts ro
tating
,
ro
t
o
r
p
o
sitio
n
is sensed
b
y
th
e reso
lv
er an
d
t
h
en
t
h
e mo
tor is
exci
t
e
d
base
d
on
t
h
e R
D
C
si
gnal
a
n
d acc
or
di
n
g
t
o
t
h
e
di
re
ct
i
on
of
r
o
t
a
t
i
o
n
of
t
h
e m
o
t
o
r.
The speed ca
n be controlle
d in a closed loop
by
m
easuring the actual spee
d of t
h
e m
o
tor. If the
spee
d i
s
g
r
eat
e
r
t
h
a
n
t
h
e
desi
red
rat
e
d s
p
ee
d, t
h
e
n
all th
e
MOSFETs are tu
rn
ed
off
for a sho
r
t
d
u
ratio
n
and
then a
g
ain exc
ited based
on the RDC position a
n
d accord
i
ngly spee
d ca
n be adjusted to get constant s
p
eed.
Th
e
ADC
08
00 is u
s
ed
to
conv
ert th
e an
al
o
g
sig
n
a
l co
rrespo
nd
ing
t
o
th
e sp
eed of th
e m
o
to
r to a d
i
g
ital v
a
lu
e
an
d co
m
p
arison
is
do
n
e
with
th
e calcu
lated
d
i
g
ita
l v
a
l
u
e
wh
ich
is propo
rti
o
n
a
l t
o
th
e rated
sp
eed
.
3.
1.
Spar
t
an 3
F
P
GA
The S
p
a
r
t
a
n-
3
fam
i
l
y
of Fi
el
d
-
Pr
o
g
ram
m
able Gat
e
A
rrays
is specifically designe
d
to m
eet the nee
d
s
o
f
h
i
gh
v
o
l
u
m
e, co
st-sen
sitive co
nsu
m
er electron
i
c app
licatio
n
s
.
It offers d
e
n
s
ities rang
ing
fro
m
5
0
,
0
0
0
t
o
5,
00
0,
0
0
0
sy
st
em
gat
e
s.
The Spartan-3 FPGA enhance
m
ents,
co
mb
in
ed
with
adv
a
n
c
ed
pro
ces
s technology, deliver m
o
re
functionality
a
nd ba
ndwidt
h. Because
of
the
i
r exce
ptionall
y low cost,
Spa
r
tan-3 FPGAs
are ideally suited to
a
wi
de
ra
nge
o
f
con
s
um
er el
ect
ro
ni
cs a
ppl
i
cat
i
ons
.
Th
e Spartan-3
fam
i
ly
is a su
p
e
rio
r
altern
ative to
m
a
sk
p
r
og
ramm
ed
ASICs. FPGAs avo
i
d
th
e h
i
gh
in
itial co
st, the leng
th
y
d
e
velo
p
m
en
t cycles, an
d th
e inh
e
ren
t
inflex
i
b
ilit
y o
f
conv
en
tio
n
a
l
ASICs. Also
,
FPG
A
pr
og
ra
m
m
a
bi
l
i
t
y
perm
i
t
s
desi
gn u
p
g
ra
des i
n
t
h
e f
i
el
d wi
t
h
no
h
a
rd
ware
re
pl
acem
e
nt
necessa
ry
, a
n
i
m
p
o
ssib
ility with
ASICs.
Th
e Sp
artan-3 fam
i
l
y
arch
itectu
r
e con
s
ists o
f
fi
v
e
fun
d
a
men
t
al p
r
o
g
rammab
l
e
functional elements those
are
C
o
n
f
i
g
ura
b
l
e
Lo
gi
c B
l
ocks (
C
LB
s) co
nt
ai
n
R
A
M
-
base
d L
o
o
k
-
U
p
Tabl
es
(LUTs
)
t
o
i
m
pl
em
ent
l
ogi
c
a
n
d
stora
g
e elem
en
ts that can be use
d
as flip-flops
or
l
a
t
c
hes
.
C
L
B
s
can be pr
o
g
ram
m
ed to pe
rf
orm
a wi
d
e
v
a
riety of log
i
cal fun
c
tion
s
as
well as to store d
a
ta.
In
p
u
t
/
out
put
B
l
ocks
(I
OB
s)
c
ont
rol
t
h
e
fl
o
w
o
f
dat
a
bet
w
een
t
h
e
I/
O
pi
ns a
n
d t
h
e i
n
t
e
r
n
al
l
ogi
c
o
f
t
h
e
devi
ce.
Each
I
O
B
su
p
p
o
r
t
s
bi
di
rect
i
o
nal
d
a
t
a
fl
ow
pl
u
s
3-st
at
e o
p
e
r
at
i
o
n
.
T
w
ent
y
-si
x
di
ffe
rent
si
g
n
al
st
anda
rd
s, i
n
cl
udi
ng ei
ght
hi
g
h
-
p
er
f
o
rm
ance di
ffe
re
nt
i
a
l
st
anda
r
d
s.
Do
u
b
l
e
Dat
a
-R
at
e (
D
DR
) re
gi
st
ers a
r
e
in
clu
d
e
d
.
Th
e
Dig
itally Co
n
t
ro
lled
Im
p
e
d
a
n
ce (DCI) feat
u
r
e
p
r
ov
id
es au
to
m
a
tic o
n
-
ch
ip
term
in
atio
n
s
,
sim
p
l
i
f
y
i
ng b
o
a
rd
desi
gn
s.
B
l
ock R
A
M
pr
ovi
des
dat
a
st
o
r
age
i
n
t
h
e f
o
r
m
of 1
8
-
K
bi
t
d
u
al
-
p
o
r
t
bl
oc
ks
.
Multiplier bl
oc
ks acce
pt two
18-bit bina
ry num
b
ers as i
n
puts and calculat
e
the
product.
Dig
ital Clo
c
k
Man
a
g
e
r (DC
M
) b
l
o
c
k
s
prov
id
e sel
f-calibratin
g, fu
lly d
i
g
ital so
lu
tion
s
for
d
i
stribu
ting,
del
a
y
i
ng,
m
u
l
t
i
pl
y
i
ng,
di
vi
di
n
g
, a
n
d
pha
se s
h
i
f
t
i
ng cl
ock
si
g
n
al
s.
Th
is alg
o
rith
m is u
s
ed
to
writ
e a p
r
og
ram
in
VHDL and
is lo
ad
ed
on
to
the FPGA Sp
artan
3
d
e
v
i
ce
an
d
tested
on
t
h
e 30
V
an
d
20
00
r
p
m
BLD
C
m
o
to
r
sh
own
in
t
h
e Figu
re 2
.
M
o
to
r is
capable t
o
operat
e wit
h
1
60v
an
d 700
0r
p
m
sp
eed.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
FPGA
Based
Contr
o
l Method for Three
Phase B
L
DC
Mot
o
r (Suneeta)
1
437
Fig
u
r
e
2
.
30
V
,
20
00
rp
m
BL
D
C
m
o
to
r
4.
PROP
OSE
D
HA
RD
WA
RE
FO
R BLD
C
MOTO
R
Propo
sed
h
a
rdware sch
e
m
a
ti
c stru
ct
u
r
e is sh
own
in Figure 3
.
Th
e
VHDL
p
r
og
ram
h
a
s
been
written
an
d tested
on
si
m
u
lato
r and
hardware.
4.
1.
RTL Sche
matic
Fi
gu
re
3.
R
TL
Schem
a
t
i
c
of F
P
G
A
c
ont
r
o
l
ci
rcui
t
4.
2.
MOSFET Dri
v
er
Circuit
The
basi
c
har
d
ware
st
r
u
ct
ure
t
o
r
u
n a
n
B
L
D
C
m
o
t
o
r i
s
i
n
v
e
rt
er
bri
dge
. T
h
e si
gnal
ge
ne
rat
e
d
fr
o
m
FPGA is
fed
into
inv
e
rter throu
g
h
op
to- iso
l
ato
r
s. Th
e inv
e
rt
er circu
it is sh
own in
Figu
re 4.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE
Vo
l. 6
,
N
o
. 4
,
Au
gu
st 2
016
:
14
34
–
1
440
1
438
Fi
gu
re 4.
M
O
S
F
ET dri
v
er
ci
r
c
ui
t
Th
e co
m
p
lete h
a
rdware
set up
for th
e m
o
to
r con
t
ro
l is sh
own in
Figu
re 5.
Figu
re
5.
The
c
o
m
p
lete Hard
ware
set u
p
5.
RESULTS
A
N
D
DI
SC
US
S
I
ONS
The
pul
ses
ge
nerat
e
d f
r
om
the FP
G
A
t
o
c
ont
rol
B
L
DC
m
o
t
o
r ci
rcui
t
are as sh
o
w
n i
n
Fi
gu
re 6 a
n
d
FPGA
base
d si
gnals
are m
a
intaining acc
urac
y com
p
are ot
her technique
ba
sed c
o
ntrol
signals.
Fi
gu
re
6.
P
u
l
s
es t
o
dri
v
e t
h
e
M
O
SFET
s
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
FPGA
Based
Contr
o
l Method for Three
Phase B
L
DC
Mot
o
r (Suneeta)
1
439
Th
e pu
lses shown
in
th
e Figure 6
are fed
to
th
e 3
0
V
, 20
00
rp
m
BLDC
m
o
to
r an
d
th
e m
o
to
r ro
tates
with
th
e sp
ecified
sp
eed
.
Th
e
m
o
to
r ro
tates with
2
000
r
p
m
i
s
m
easured
t
h
ro
u
gh t
a
c
hom
et
er an
d i
t
s
fee
d
bac
k
t
h
r
o
u
g
h
resol
v
er. The re
sol
v
e
r
pr
o
v
i
d
es i
n
fo
rm
ati
on i
n
t
h
e fo
rm
of si
ne and c
o
si
ne
. Usi
ng re
sol
v
er t
o
di
gi
t
a
l
con
v
e
r
t
e
r t
h
e
s
e si
gnal
s
are c
o
n
v
e
r
t
e
d i
n
t
o
di
gi
t
a
l
an
d fe
d
t
o
FP
G
A
. T
h
e
m
o
t
o
r fee
dba
ck
out
put
i
s
s
h
ow
n i
n
Fi
gu
re 7.
Fi
gu
re
7.
R
e
sol
v
er
fee
dbac
k
6.
CO
NCL
USI
O
N
The p
r
op
ose
d
al
go
ri
t
h
m
has been
pr
o
g
ram
m
ed i
n
VH
DL
and i
t
ge
nerat
e
s t
h
e fi
ri
n
g
p
u
l
s
es re
qui
red
t
o
dri
v
e t
h
e M
O
SFE
Ts o
f
t
h
r
ee phas
e
f
u
l
l
y
cont
rol
l
e
d
bri
d
ge co
n
v
ert
e
r
.
The p
r
og
ram
has been l
o
ade
d
on t
o
t
h
e FP
GA S
p
a
r
t
a
n 3
de
vi
ce and
fed t
o
t
h
e
M
O
SFET
s
o
f
t
h
ree
ph
ase f
u
l
l
y
cont
r
o
l
l
e
d
br
i
dge c
o
n
v
e
r
t
e
r
dri
v
e
n
by
opt
o i
s
ol
at
o
r
dri
v
er ci
rc
ui
t
.
The o
u
t
p
ut
fr
o
m
t
h
e conve
rt
er i
s
fed t
o
t
h
e t
h
ree
phase st
at
or wi
n
d
i
n
g of
30
V,
20
0
0
r
p
m
B
L
DC
m
o
t
o
r an
d t
h
e m
o
t
o
r i
s
fo
u
nd t
o
r
u
n at
co
nst
a
nt
spee
d w
h
i
c
h i
s
set
by
t
h
e e
x
t
e
r
n
al
pote
n
tiom
e
ter connected to t
h
e FPGA ci
rcu
it. Th
e
program is fo
und
to
b
e
efficien
t and
th
e
resu
lts with
th
e
desi
g
n
e
d
har
d
ware
are ve
ry
go
o
d
.
REFERE
NC
ES
[1]
T Sutikno
, NRN Idris, NS Wido
do,
A Jidin.
FP
GA Based a
P
W
M
Techniqu
e
for P
e
rm
anent
M
a
gnet AC M
o
tor
Drives.
International Journal of
Reco
n
figurable
and Embedded
S
y
stems
. 2012; 1(
2): 43-48.
[2]
K.
Iizuka,
et al.
, “Microcomputer control fo
r sen
s
orless brushless motor,”
IEEE T
r
ans Ind Applica
t
, vol IA-21
,
pp
.
595-601, 1985
.
[3]
R. C. Beccerra,
et a
l
.
, “Four quadrant sensorless
brushless motor,” in
Proc
. I
EEE
APEC’91
, pp
. 2
02-209, 1991
.
[4]
S. Ogasawara
a
nd H. Akag
i,
“
A
n approa
ch to
positio
n
sensorless drive
for br
ushless dc m
o
to
rs,” in
Conf. Rec.
IEEE-I
A
S Annu. Meet
ing
, pp. 443
–447, 1990
.
[5]
P. Devendr
a,
et al.
, “Microcontr
o
ller
based
contr
o
l
of
thre
e ph
as
e
BLDC m
o
tor,
”
JERS
, vo
l/issue:
(2)4, 2011
.
BIOGRAP
HI
ES
OF AUTH
ORS
M
r
s
.
S
uneeta
re
ceiv
e
d th
e B
E,
M
.
Te
ch deg
r
ee
from
VTU; Bel
g
aum
.working
as
an As
s
i
s
t
ant
Professor,
VEM
ANA.
IT,
Bangalore.
India.
Guid
ed many
Undergraduate and
post graduate
students in VLSI and Embedded
field. At pr
esent pursing f
o
r Ph.D Degree with JNTUK/
Kakinada, Ind
i
a
and life member
for ISTE.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE
Vo
l. 6
,
N
o
. 4
,
Au
gu
st 2
016
:
14
34
–
1
440
1
440
Dr. R. Srinivasan obtained h
i
s Bachlors, maste
r’s and doctorate degree
from IISc, Bangalore,
India. H
e
has
s
e
rved as
S
c
ient
i
s
t with Natio
n
a
l
Aeros
p
ace
Lab
o
ratori
es
Banga
l
o
re and wi
th
Indian Institu
te
of Astroph
y
s
ics,
Bangalore
in va
rious capa
c
it
ies and speci
ali
zed i
n
analog/d
i
git
a
l
Controls and servo sy
stems relate
d to astronomical instrumentatio
n.
He has numb
e
r of papers to
his cred
it
with n
a
tion
a
l
& in
tern
a
tional
Journals/
c
onferenc
e
s.
Prof. Ram Sagar completed his
M.Sc. (1973)
an
d
Ph.D. (1981)
in Ph
y
s
ics from University
of
Gorakhpur. He joined the U
.
P State Observator
y,
Nainital
in 1979, where he w
a
s the director
during 1996 -
2
000. Prof. Ram
Saga
r spent some time at th
e K
u
maon University
, Nain
ital, as
faculty
member in Ph
y
s
ics De
p
a
rtment during
1979-1986. He
then join
ed and
worked at th
e
Indian Insti
t
ute of Astroph
y
s
i
c
s, Bangalore un
til 2000
, when
he m
oved to N
a
init
al
, as
the
Director
of th
e
State Observ
ator
y
ther
e (2000-20
04). He subsequ
e
ntly
moved
to the Ar
y
a
bhatta
Research
Institu
te of Observati
onal Sci
e
nces
(ARIES) in 2004 as its dir
ecto
r
. His areas of
research interest are Star - formation and stel
lar evolution,
Star
cl
usters,
GRBs,
AGNs,
Aster
seism
o
log
y
,
Gra
v
itat
i
onal
l
e
nsin
g and Atmospheric Ph
y
s
ics.
He is a Chief Editor of Journal of Astrophy
si
cs and Astronomy
since 2013.Prof.
Ram Sagar is a
fellow of
the
In
dian Ac
adem
y
of S
c
ien
ces
,
Ba
ngalore, Ind
i
a,
National
Acad
e
m
y of S
c
ienc
es
,
Allahab
a
d, India and Laser an
d
S
p
ectros
c
opi
c
S
o
ciet
y of In
dia. He
is
a re
cipi
ent of th
e
Astronomical Society
of Ind
i
a Young Astron
omer’s award (1983–84), the
Ro
y
a
l Society
,
London, Commonwealth Bur
s
ar
y
f
e
llowship
(1983–85), th
e Alexand
e
r v
on Humboldt
Foundation German Research fellowship (1990)
, and Rajiv G
a
ndhi Sadbhavana Award as
Eminent Scientist of the
y
e
ar 2
009. He has pu
blished over 22
5 resear
ch pap
e
rs in refer
eed
journals and
an
other over 120
contribut
ions in
pr
oceed
ings et
c
.
His scient
ific
work has been
cited over
4000
times in th
e r
e
put
ed peer r
e
viewed journals.
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