Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
6, N
o
. 1
,
Febr
u
a
r
y
201
6,
pp
. 29
8
~
30
6
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
1.8
388
2
98
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
High Throughput FPGA Implementa
tion of Data Encryption
Standard with Time Variable Sub-Keys
Sou
f
ian
e
O
uki
li, Seddik Bri
Department o
f
Electrical
Engin
e
ering, High
Scho
ol of
Technolog
y
,
Moula
y
Ism
a
il Universi
t
y
,
Morocco
Article Info
A
B
STRAC
T
Article histo
r
y:
Received
J
u
n 18, 2015
Rev
i
sed
No
v
28
, 20
15
Accepted Dec 14, 2015
The Da
ta
Encr
yption S
t
and
a
rd
(DES
)
was the
first modern an
d the most
popular s
y
mmetric k
e
y
algorith
m
used
for en
cr
y
p
tion
and d
e
cr
y
p
tion of
digital data. Ev
en though it is
nowaday
s no
t considered secu
r
e
against a
determ
ined
att
a
c
k
er, it
is still use
d
in le
ga
c
y
appli
cat
ions. This pa
per presents
a secure and h
i
gh-throughput
Field
Programming Gate Array
s
(FPGA)
implementation
of the Data En
cr
y
p
tion
S
t
and
a
rd algorithm
.
This
i
s
achi
e
ved
b
y
combining
16 pipelining concept wi
th time variable su
b-key
s
and
com
p
ared with p
r
evious
il
lus
t
rat
e
d encr
ypt
i
on al
g
o
rithm
s
. The s
u
b
-
ke
y
s
v
a
r
y
over time b
y
ch
anging th
e key
schedule
p
e
rmutation choice
1
.
Therefor
e,
ever
y
time th
e plaintexts are
encr
y
p
te
d b
y
d
i
ffer
e
nt sub-key
s
. Th
e proposed
algorithm is implemented on Xilinx Sp
artan-3e (
X
C3s500e) FPGA. Our DES
design achieved
a data en
cr
y
p
tion ra
te of 1030
5.95 Mbps and 2625 number
of occupied
CLB slices. These re
sults s
howed that th
e proposed
implementation
is one of th
e f
a
stest
hardwar
e
implementations
with much
great
er s
e
curit
y
.
Keyword:
Data en
cryp
tion
stan
d
a
rd
FPGA im
p
l
e
m
en
tatio
n
Pip
e
lin
ing
Security
Su
b-
key
s
Tim
e
variable
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Sou
f
ian
e
Ouk
ili,
Depa
rt
m
e
nt
of
El
ect
ri
cal
Engi
neeri
n
g
,
H
i
gh
Scho
o
l
of Techno
log
y
,
Mo
u
l
ay Ism
a
i
l
U
n
i
v
er
sity, M
o
r
o
cco
B.P 3103
,
H
i
gh
Scho
o
l
of
Tech
no
log
y
, Mekn
ès, Mo
ro
cco
Em
a
il: so
u
f
iane.ou
k
ili@g
m
ai
l.co
m
1.
INTRODUCTION
Cryp
tog
r
aph
y
is th
e science o
f
u
s
ing
math
e
m
atics
t
o
tran
sfo
r
m
i
n
tellig
ib
le in
fo
rm
atio
n
t
o
u
n
i
n
t
ellig
ib
le d
a
ta. Cryp
t
o
grap
h
y
en
ab
les
to
sto
r
e se
n
s
it
iv
e in
fo
rm
atio
n
or tran
sm
it
it acro
ss in
secu
re
net
w
or
ks,
so
t
h
at
i
t
can
not
be r
ead
by
a
n
y
one e
x
ce
pt
t
h
e i
n
t
e
nde
d
re
ci
pi
ent
.
T
h
i
s
c
a
n
be
do
ne
b
y
t
w
o
t
echni
q
u
es
, sy
m
m
e
t
r
i
c
key
and asy
m
m
e
t
r
i
c
key
.
Sy
m
m
e
t
r
i
c
key
cry
p
t
o
gr
aphy
involves
the usa
g
e of the sam
e
key
fo
r enc
r
y
p
t
i
on an
d dec
r
y
p
t
i
o
n
.
O
n
t
h
e
ot
he
r ha
nd t
h
e
asym
m
e
t
r
i
c
key
i
nvol
ves t
h
e usage
of
one
key
fo
r
encry
p
t
i
on a
n
d
anot
he
r, di
ffe
rent
key
f
o
r d
ecry
p
t
i
o
n. Sec
r
et
key
cry
p
t
o
gra
p
hy
i
n
cl
ude
s DES, A
E
S,
3D
ES
,
I
D
EA
, Blowf
i
sh
algo
r
ith
m
s
et
c. and
pub
lic key cr
yp
to
gr
ap
hy in
clu
d
e
s RSA
,
D
i
g
ital Sign
atur
e and
Messag
e
Digest al
go
rith
m
s
[1-2]
.
The
Data Encryption Standard (DE
S
) i
s
an e
n
cryp
ti
o
n
stand
a
rd
fo
r
p
r
o
t
ectin
g co
nfid
en
tial
i
n
f
o
rm
at
i
on. It
has
bee
n
de
v
e
l
ope
d i
n
t
h
e
19
7
0
s at
IB
M
and
ad
o
p
t
e
d a
s
a Fed
e
ral
I
n
f
o
rm
at
i
on Pr
oc
essi
ng
St
anda
r
d
si
nce
19
7
7
by
t
h
e
Nat
i
onal
Inst
i
t
u
t
e
of St
a
n
d
a
rds a
n
d Tec
h
nol
ogy
[3
-4]
.
DES
has
been
us
e
d
p
e
rv
asiv
ely
b
y
m
a
n
y
ap
p
licatio
n
s
t
h
at requ
ire data
con
f
i
d
en
tiality. Ho
wev
e
r, fro
m
year 2
001
,
DES h
a
s b
e
en
sup
e
rse
d
e
d
by
t
h
e A
dva
nce
d
Encry
p
t
i
on
St
anda
r
d
AE
S [
5
]
.
B
u
t
i
n
pra
c
t
i
ce, a l
o
t
of
har
d
ware
or s
o
ft
war
e
ap
p
lication
s
sti
ll resort to
DES.
The DE
S i
s
a
bl
oc
k ci
phe
r t
h
at
ope
rat
e
s o
n
6
4
-
b
i
t
bl
ock
s
of dat
a
an
d uses 5
6
-
b
i
t
pri
v
at
e effect
i
v
e
key. Because
of its s
m
all key size, several attacks ag
ainst
DES algorithm were published [6-8]. To i
n
crease
t
h
e secu
ri
t
y
of
t
h
e al
go
ri
t
h
m
,
we p
r
o
p
o
sed
t
h
e Dat
a
Enc
r
y
p
t
i
on St
a
nda
r
d
base
d
on
va
ri
abl
e
su
b-
key
s
wi
t
h
ti
m
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
H
i
gh
Th
ro
ughp
u
t
FPGA Implem
en
ta
tion o
f
D
a
t
a
En
cryp
tio
n S
t
a
nda
rd
with
Tim
e
…
(S
ou
fia
n
e
Ou
kili)
29
9
The p
r
o
p
o
se
d schem
e
uses perm
ut
at
i
on choi
ce 1(
PC
-1
) b
ox i
n
t
h
e
key
sched
u
l
e
, w
h
i
c
h cont
ai
ns s
e
veral
perm
ut
at
i
ons t
o
be sel
ect
ed
b
y
t
h
e sende
r.
Whe
n
e
v
er t
h
e
perm
ut
at
i
on ch
ange
s, t
h
e s
u
b
-
key
s
cha
nge al
so, s
o
there a
r
e
different cipheret
e
x
ts for t
h
e sam
e
key and
plainte
x
t. T
h
ere
f
ore, t
h
e sec
u
rity is i
n
crease
d
.
Im
pl
em
ent
a
ti
on o
f
DES i
s
usu
a
l
l
y
di
vi
de
d i
n
t
o
s
o
ft
war
e
and
har
d
wa
re ap
pr
oac
h
es.
Whi
l
e
t
h
e
soft
ware m
e
t
h
o
d
has se
cu
ri
t
y
pr
obl
em
s, t
h
e
ha
rdwa
re encry
p
tion can
be a
better c
hoice. FPGA
i
m
p
l
e
m
en
tatio
n
o
f
DES en
cryp
tio
n algo
rithm
p
e
rform
s at m
u
ch
faster d
a
ta-rates an
d
p
r
o
v
i
d
e
s
b
e
tter
secu
rity
t
h
an e
q
ui
val
e
nt
so
ft
wa
re i
m
plant
a
t
i
ons
[
9
]
.
In t
h
is pa
pe
r,
we
prese
n
t a
n
efficient a
n
d a
secu
re
h
a
r
d
w
a
re
i
m
pl
em
entat
i
on of 1
6
-st
a
ge pi
pel
i
n
e
d
DES,
base
d o
n
t
h
e vari
at
i
o
n
of t
h
e
key
sch
e
dul
e
perm
ut
at
i
on C
h
oi
ce 1
(
P
C
-1
) with
time. Data b
l
o
c
k
s
can
b
e
loade
d
at each clock cycle a
nd afte
r an ini
tial dela
y of 17 clock cycles, the
ciphe
retexts will appea
r
on
consecutive cl
ock cycles. T
h
e design is im
p
l
e
m
ented
o
n
X
i
l
i
nx Spa
r
t
a
n
F
P
G
A
t
ech
nol
o
g
y
.
T
h
e FP
GA
s of
fe
r
th
e adv
a
n
t
ag
e
o
f
h
a
rdware speed
an
d so
ftware flex
ib
ility an
d pro
g
ramma
b
ility.
The rest
of t
h
i
s
pape
r i
s
or
g
a
ni
zed as f
o
l
l
o
ws:
Sect
i
on
2
descri
bes t
h
e
DES al
g
o
r
i
t
h
m
.
Pi
pel
i
n
i
ng
DES
an
d
pi
p
e
l
i
n
i
n
g
DES
bas
e
d
on
t
i
m
e vari
abl
e
s
u
b
-
key
s
are
prese
n
t
e
d
i
n
Sect
i
o
n
3
a
n
d Se
ct
i
o
n
4
.
S
e
ct
i
on
5
gives im
ple
m
entation sum
m
ary. Section 6 com
p
ares
th
e ach
iev
e
d
resu
lts with
th
e p
r
ev
iou
s
DES
im
pl
em
ent
a
t
i
o
ns. C
o
ncl
u
si
on
an
d
refe
rences
are
gi
ve
n i
n
S
ect
i
on
7 a
n
d
8
respect
i
v
el
y
.
2.
DAT
A E
N
C
R
Y
PTIO
N ST
A
N
D
A
R
D
ALG
O
RITH
M
DES
al
g
o
ri
t
h
m
encry
p
t
s
6
4
-
bi
t
pl
ai
nt
ext
bl
oc
ks
with
64
-b
it k
e
y and g
e
n
e
rates 64
-b
it ciph
ertext
bl
oc
ks as sh
o
w
n i
n
Fi
g
u
r
e 1. Thi
s
al
g
o
ri
t
h
m
uses co
m
p
l
i
cat
ed l
ogi
cal
funct
i
o
ns s
u
c
h
as vari
ous t
y
pes of
perm
utations,
XOR a
nd shift functions. One
bit in each 8 b
its of the
key
may be utilize
d
for error dete
ction in
key generation. Bits 8,
16,
24, 32, 40,
48,
56 an
d 64 are used i
n
ensu
ring that
each byt
e
of the key
is
of odd
pari
t
y
an
d ot
he
rwi
s
e
i
g
n
o
r
ed
. C
onse
q
uent
l
y
, t
h
e
ef
fect
i
v
e k
e
y
l
e
ngt
h
i
s
56
bi
t
s
.
Fi
gu
re 1.
DE
S bl
oc
k vi
ew
DES i
s
a
n
i
t
e
rat
i
v
e al
g
o
ri
t
h
m
as show
n i
n
Fi
gu
re
2. F
o
r eac
h
bl
oc
k
of
pl
ai
nt
e
x
t
,
encry
p
t
i
o
n
i
s
h
a
nd
led
i
n
16
ro
und
s wh
ich
all p
e
r
f
or
m
th
e i
d
en
tical op
er
at
io
n
.
In
ev
er
y ro
und
a d
i
f
f
e
r
e
nt su
b-
k
e
y is
u
s
ed
and
al
l
sub
-
key
s
ar
e de
ri
ve
d f
r
o
m
t
h
e m
a
i
n
key
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 1, Feb
r
uar
y
20
1
6
:
29
8 – 30
6
30
0
Fi
gu
re 2.
DE
S al
go
ri
t
h
m
bl
ock di
ag
ram
Th
e in
co
m
i
n
g
b
l
o
c
k
of p
l
ain
t
ex
t (64
b
its) fi
rstly p
a
sses th
ro
ugh
an
in
itial p
e
rm
u
t
atio
n
(IP) and
then
will b
e
d
i
v
i
d
e
d in
to
t
w
o 32-b
i
t h
a
lv
es,
3
2
righ
t b
its and
3
2
left b
its.
I
n
ev
er
y ro
und, th
e r
i
gh
t 32
b
its ar
e exp
a
nd
ed
t
o
48
b
its u
s
ing
th
e
exp
a
n
s
ion
p
e
r
m
u
t
at
io
n
(E)
,
by
d
u
p
licatin
g
h
a
l
f
of th
e b
its. Th
en, th
e
resu
lt is co
m
b
in
ed
with
a
sub-k
e
y
usin
g
an
XOR
o
p
e
ration
.
Th
e XOR
out
put is divi
ded into eight 6-bit
and
fe
d into eight substitution boxes (S).
Each of these
boxes re
places
its six
input bits with four
output bi
ts,
according t
o
a non-linea
r
trans
f
orm
a
tion. The
out
puts a
r
e concatenate
d
and
pass t
h
ro
u
gh a
st
rai
ght
pe
rm
ut
at
i
on (
P
). T
h
e resul
t
i
s
pr
oc
essed t
h
ro
u
gh
XOR
f
u
nct
i
on
wi
t
h
t
h
e l
e
ft
3
2
bi
t
s
and t
h
e o
u
t
p
ut
i
s
t
h
e ri
ght
bi
t
s
of t
h
e ne
xt
ro
u
n
d
.
The
left b
its o
f
th
e nex
t
roun
d
are th
e righ
t b
its o
f
the
p
r
ev
iou
s
ro
und as sh
own
in Fi
g
u
r
e
3
.
After th
e 16
th iteratio
n, th
e
righ
t and left
b
its
are con
cat
en
ated and
finally p
a
ss throu
gh a
fin
a
l
p
e
rm
u
t
atio
n
(IP-1), wh
ich
is
th
e inv
e
rse of t
h
e in
itial p
e
rm
u
t
atio
n
(IP). Th
e
o
u
t
p
u
t
is t
h
e cip
h
e
rtex
t
b
l
o
c
k (6
4
b
its).
Fi
gu
re 3.
O
n
e r
o
u
n
d
of
DE
S
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
H
i
gh
Th
ro
ughp
u
t
FPGA Implem
en
ta
tion o
f
D
a
t
a
En
cryp
tio
n S
t
a
nda
rd
with
Tim
e
…
(S
ou
fia
n
e
Ou
kili)
30
1
DES is a
p
r
i
v
ate k
e
y alg
o
rithm
,
in
wh
ich
the sam
e
k
e
y is
u
s
ed
fo
r
bo
th
en
cry
p
tio
n
and d
ecry
p
tio
n.
Fig
u
r
e
4 show
s t
h
e
k
e
y sch
e
du
le
g
e
n
e
r
a
t
i
o
n
.
I
t
is also an iter
a
tiv
e
p
r
o
cess co
m
p
risin
g
16
r
ound
s and
gene
rat
e
s 1
6
s
u
b
-
key
s
fr
om
the m
a
i
n
key
.
The
56-b
it effectiv
e k
e
y
g
e
ts firstly p
e
rm
u
t
ate
d
(PC
-1
) and
splits up
in
to
two
28
-b
i
t
h
a
lv
es;
each
h
a
lf is
therea
fter treated separately. Then
, f
o
r
ev
er
y roun
d, bo
th
h
a
lv
es ar
e
shi
f
t
e
d l
e
ft
by
ei
t
h
er o
n
e
or t
w
o
bi
t
s
, de
pe
n
d
i
n
g o
n
t
h
e
r
o
un
d
num
ber.
A
f
t
e
r t
h
at
, t
h
e t
w
o
o
u
t
p
ut
s g
o
t
h
r
o
u
g
h
anot
her pe
rm
utat
i
on
(
P
C
-2
). Th
e resu
lt is th
e
su
b-k
e
y and
it is co
d
e
d
o
n
48
b
its, 24
b
its from th
e left h
a
lf, and
24
f
r
om
t
h
e ri
g
h
t
.
Th
e d
e
cryp
tion
alg
o
rith
m
is
ex
actly th
e sa
me as
th
e encryption one,
but the
only difference is that
the round
keys
are
use
d
i
n
the re
verse
order. T
h
e
out
put
of
each
round during decryp
ti
on is t
h
e input t
o
the
cor
r
es
po
n
d
i
n
g
ro
u
nd
d
u
ri
ng
e
n
cry
p
t
i
o
n
.
T
h
i
s
great
l
y
si
m
p
li
fies im
p
l
e
m
en
tatio
n
,
p
a
rticu
l
arly in
h
a
rd
ware, as
th
ere is
no
n
e
ed
for sep
a
rate en
cry
p
tio
n and
d
ecry
p
tio
n algo
rith
m
s
.
Fi
gu
re 4.
Key
sche
dul
e ge
ner
a
t
i
o
n
3.
PIPELINED
DES
Pipeline is a
n
im
portant technique t
o
i
n
creas
e the
perform
a
n
ce
of a syste
m
[10]. T
h
e ite
rative
nature
of t
h
e
DES al
go
ri
t
h
m
m
a
kes i
t
i
d
eal
l
y
sui
t
e
d t
o
pi
pel
i
n
i
ng a
nd i
t
can
be 4,
6,
8 o
r
16 st
a
g
es [
11]
. The
p
i
p
e
lin
ing
strateg
y
co
n
s
ists in
p
a
rallelizin
g th
e d
a
ta in
p
u
ts an
d
ou
tpu
t
s with
th
e p
r
o
c
essin
g
. Basically, it
mean
s to
p
r
o
cess th
e d
a
ta th
at is g
i
v
e
n
as in
pu
t in
a cont
i
n
u
ous m
a
nner wi
t
h
o
u
t
havi
ng t
o
wai
t
for t
h
e cu
rre
nt
pr
ocess t
o
get
ove
r.
Thi
s
pi
p
e
l
i
n
i
ng c
o
ncept
i
s
seen i
n
m
a
ny
pr
ocess
o
rs
. R
e
gi
st
ers a
r
e
use
d
t
o
st
o
r
e t
h
e
c
u
r
r
ent
out
put
of
t
h
e
r
o
u
n
d
t
h
at
i
s
be
i
ng e
x
ec
ut
ed.
I
n
t
h
i
s
case
i
n
st
ead
of
passi
ng
t
h
e o
u
t
p
ut
of e
ach r
o
un
d t
o
t
h
e ne
xt
ro
u
n
d
di
re
ct
l
y
we
use a
re
gi
st
er
whi
c
h
wo
ul
d act
as
a
bypa
ss or a
n
i
n
ternal register. Si
nce the c
u
rre
n
t rounds
val
u
e i
s
st
ore
d
i
n
t
h
e
re
gi
st
er
t
h
e
next
i
n
p
u
t
t
o
t
h
e c
u
rre
nt
ro
u
n
d
i
s
gi
ve
n as s
o
on
as t
h
e c
u
r
r
ent
o
u
t
put
i
s
obt
ai
ne
d.
I
n
t
h
i
s
way
t
h
e i
n
p
u
t
t
o
t
h
e
next
r
o
u
n
d
i
s
gi
ve
n
f
r
om
t
h
e regi
st
e
r
av
oi
di
ng a
di
rect
co
nt
act
be
t
w
een
t
h
e t
w
o
ro
u
nds
.
DES
i
m
pl
em
ent
a
t
i
on p
r
esent
e
d
i
n
t
h
i
s
pa
pe
r
i
s
base
d
o
n
1
6
st
a
g
es pi
pel
i
n
i
n
g. I
n
or
der
t
o
pi
pel
i
n
e
t
h
e
algorithm
,
registers R and L
(32-bit)
a
r
e placed at the le
ft and ri
ght
of
the outputs
of
each round of
t
h
e
alg
o
rith
m
to
allo
w t
h
e sequ
entialit
y o
f
th
e d
a
ta, as sh
own
in Figu
re 5.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 1, Feb
r
uar
y
20
1
6
:
29
8 – 30
6
30
2
Fi
gu
re 5.
Pi
pel
i
ned DE
S
4.
PIPELINING DES B
A
SE
D
ON
TIME VARIABLE SUB
-
KEYS
There
ha
ve
been se
veral a
p
proaches
to
attack
DES algorithm
.
The
m
o
st
p
o
p
u
l
ar
is th
e lin
ear
cry
p
t
a
nal
y
si
s [
6
]
,
di
f
f
ere
n
t
i
a
l
cry
p
t
a
nal
y
si
s
[7]
an
d e
xha
us
t
i
v
e key
searc
h
[
8
]
.
I
n
or
der
t
o
m
a
ke DES
m
o
re
secure
, we
de
v
e
l
ope
d a ne
w
al
go
ri
t
h
m
shown i
n
Fi
g
u
re
6
.
It
has a
key
s
c
hed
u
l
e
pe
rm
ut
at
i
on ch
oi
ce 1
(
PC
-1
)
bo
x t
h
at
co
nt
ai
ns
fo
ur
di
f
f
er
e
n
t
pe
rm
ut
at
i
ons i
n
or
der
t
o
be
use
d
peri
odi
ca
l
l
y
. As a re
sul
t
of t
h
i
s
, t
h
e s
u
b
-
key
s
change. There
f
ore
,
eve
r
y tim
e
the plai
ntexts
are enc
r
ypte
d
by differe
n
t s
u
b
-
k
e
ys.
Detectin
g th
e al
g
o
rithm
wil
l
be diffic
u
lt
for the
attackers because
of the ti
me variant
be
havior.
We ca
n u
s
e se
veral
perm
ut
at
ions
i
n
t
h
e b
o
x
.
In
o
u
r
desi
gn
,
we h
a
ve
f
o
u
r
.
Sen
d
er
speci
fi
e
s
h
o
w m
a
ny
clock cycles (N1, N2,
N3 and N4) that he
will use each
of
these four
pe
rm
utati
ons. Constantly, the
program
ch
ecks th
e Time v
a
lu
e. If it is less th
an
sen
d
er cl
oc
k cy
cl
e val
u
e, t
h
e pe
r
m
ut
at
i
on i
s
kept
, ot
he
r
w
i
s
e, t
h
e ne
xt
perm
ut
at
i
on i
s
sel
ect
ed fr
om
the pe
rm
ut
at
i
on bo
x a
nd t
i
m
e
val
u
e i
s
set
t
o
zero
.
Fl
o
w
cha
r
t
sh
ow
n i
n
Fi
gu
re
7
i
n
t
r
o
d
u
ces t
h
e
st
eps
of
cha
n
gi
ng
t
h
e
key
sc
h
e
dul
e
pe
rm
ut
ati
on c
h
oi
ce 1
(
P
C
-1
).
The se
nder a
n
d recei
ver ha
ve the sam
e
perm
utati
on box. They a
r
e connected t
o
have the sam
e
perm
ut
at
i
on at
any
speci
fi
c t
i
m
e
. In o
r
de
r t
o
av
oi
d t
h
e
di
sad
v
ant
a
ge o
f
t
h
e sy
nc
hr
oni
z
a
t
i
on bet
w
ee
n
t
h
em
,
send
er tran
sm
i
t
s ad
d
ition
a
l data with
th
e cip
h
e
rtex
ts to
receiv
e
r, t
o
in
d
i
cate th
e co
rrect ch
o
i
ce
o
f
p
e
rm
u
t
atio
n
fr
om
t
h
e perm
ut
at
i
on
b
o
x
.
The key sche
dule is pipeline
d
, re
gisters are
placed to
store the curre
nt output
of the round that is
b
e
ing
ex
ecu
t
ed, so
th
is p
a
rt will b
e
p
e
rfo
r
m
e
d
v
e
ry fa
st and th
e alg
o
r
it
h
m
su
ppo
rts th
e
u
s
e o
f
d
i
fferen
t
k
e
ys
every cloc
k cycle, thus im
proving over
all se
curity since us
ers are
not rest
ri
ct
ed t
o
usi
ng
t
h
e sam
e
key
d
u
ri
n
g
any one se
ssion
of
data tra
n
s
f
er.
It is
noticeable that the
des
i
gn
of these
re
gi
sters is t
h
e sa
me as registers
us
e
d
i
n
r
o
un
d bl
oc
k
s
.
O
u
r pr
op
ose
d
desi
g
n
i
n
pre
s
ent
e
d
i
n
Fi
g
u
r
e
8.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
H
i
gh
Th
ro
ughp
u
t
FPGA Implem
en
ta
tion o
f
D
a
t
a
En
cryp
tio
n S
t
a
nda
rd
with
Tim
e
…
(S
ou
fia
n
e
Ou
kili)
30
3
Fi
gu
re
6.
Key
sche
dul
e
base
d
o
n
t
i
m
e vari
ab
l
e
perm
ut
at
i
on
(PC
-1
)
Fi
gu
re
7.
Fl
o
w
cha
r
t
o
f
perm
ut
at
i
o
n
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 1, Feb
r
uar
y
20
1
6
:
29
8 – 30
6
30
4
Fi
gu
re 8.
O
u
r
pr
o
pose
d
desi
g
n
5.
IMPLEME
N
TATION SUMMARY
Seve
ral crypt
o
gra
p
hic m
echanism
s
have
been esta
b
lished
in ord
e
r t
o
co
m
b
at secu
rity th
reats.
Security ap
p
licatio
n
s
v
a
ry in
th
eir
requ
ire
m
en
ts,
which add a
n
e
x
tra
challenge
since a highly secure
mech
an
ism
may n
o
t
b
e
th
e on
ly req
u
i
remen
t
bu
t rat
h
er a m
o
re efficien
t i
m
p
l
e
m
en
tatio
n in
term
s o
f
perform
a
nce and area
.
FPGA im
ple
m
entation of our
m
odified DE
S algor
ithm
was accom
p
lished on a Sparta
n-3e de
vice
XC
3s
5
00e
-
4
f
g
32
0 usi
ng
Xi
l
i
nx I
S
E Desi
gn
Sui
t
e
14.
7 as sy
nt
hesi
s an
d
M
odel
s
i
m
6.1f
as sim
u
l
a
ti
on
t
ool
.
The
desi
g
n
w
a
s co
ded
usi
n
g
VH
DL l
a
ng
ua
ge.
It
occ
upi
e
d
2
6
25
(
56%
)
C
L
B
sl
i
ces, 1
9
8
9
(2
1%
) sl
i
ce Fl
i
p
Fl
ops
a
n
d
2
0
3
(8
7%
) I/
Os.
T
h
e
desi
g
n
ac
hi
eves a
f
r
eq
ue
n
c
y
of
1
6
1
.
0
3
M
H
z.
It
t
a
kes
17
cl
oc
k cy
cl
e
s
l
a
t
e
ncy
fi
rst
t
i
m
e
onl
y
t
h
en e
n
cry
p
t
s
one
dat
a
bl
oc
k
(6
4
bi
t
s
) pe
r c
l
ock cy
cl
e. T
h
eref
ore
,
t
h
e ac
hi
eve
d
t
h
ro
u
g
h
put
i
s
(
161
.0
3
×
64
)
= 10
305
.9
5
M
b
p
s
an
d th
e t
h
ro
ugh
pu
t
p
e
r
C
L
B slice is (
1
0
305
.9
5
/
2
625
) = 3
.
92
Mbp
s
/slice.
Si
m
u
latio
n
w
i
nd
ow
is
show
n in
Fi
g
u
r
e
9
.
Fi
gu
re 9.
Si
m
u
l
a
t
i
on W
i
n
d
o
w
o
f
ou
r DES
de
si
gn
6.
PERFO
R
MA
NCE CO
MP
A
R
ISO
N
S
Th
ere are sev
e
ral h
a
rdware i
m
p
l
e
m
en
tatio
n
s
for th
e
DES alg
o
rith
m
th
a
t
ai
m
to
ach
iev
e
th
e m
o
st
effi
ci
ent
a
r
chi
t
ect
ure,
by
i
m
pr
o
v
i
n
g hi
gh
-t
hr
o
u
g
h
put
a
n
d
area-e
ffi
ci
ent
.
Tabl
e
1 s
h
o
w
s t
h
e
pe
rf
or
m
a
nce
figu
res fo
r so
m
e
rep
r
esen
tative h
a
rdware imp
l
em
en
tatio
n
s
o
f
th
e
DES.
DES
i
m
pl
em
ent
a
t
i
o
n
at
[
1
1]
uses
a
pi
pel
i
n
e
d
desi
g
n
wi
t
h
s
k
ew
c
o
re
key
-
s
c
hed
u
l
i
n
g t
o
l
o
ad
di
f
f
ere
n
t
k
e
ys ev
ery clock
cycle, allo
win
g
th
e po
ssi
b
ility
o
f
u
s
ing
mu
ltip
le k
e
ys in
an
y o
n
e
sessi
on
o
f
d
a
ta tran
sfer.
A
Jav
a
-b
ase
DES i
m
p
l
e
m
en
tatio
n
ach
i
ev
es t
h
e
fastest en
cryp
tio
n rate
o
f
10
75
2 Mbp
s
[12
]
.
It u
tilizes Jb
its on
a
Virtex XC
V150-6
de
vice. J
b
i
t
s provides
a J
a
va-bas
e
d
Ap
p
lication Pr
o
g
ra
m
m
i
ng Inte
rfa
ce (
A
PI
)
fo
r t
h
e r
u
n
-
t
i
m
e
creat
i
on and m
odi
fi
cat
i
o
n o
f
t
h
e co
nfi
g
urat
i
o
n bi
t
s
t
r
ea
m
.
In t
h
i
s
desi
gn t
h
e
key
sch
e
dul
e i
s
com
p
u
t
ed i
n
soft
ware
. Als
o
, it can only accomm
odate one
key per
data
transfe
r
sessi
on. In
[13],
the implem
entation uses a
n
on-stand
a
rd
rep
r
esen
tation
an
d
v
i
ew
t
h
e p
r
o
cesso
r
same as a
SIM
D
(Sing
l
e In
st
ru
ctio
n
M
u
ltip
le
Data)
com
put
er, as
6
4
pa
ral
l
e
l
one
-
b
i
t
pr
ocess
o
r
s
com
put
i
n
g
the sam
e
in
stru
ctio
n. A
VLSI
DES im
p
l
e
m
en
tatio
n
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
H
i
gh
Th
ro
ughp
u
t
FPGA Implem
en
ta
tion o
f
D
a
t
a
En
cryp
tio
n S
t
a
nda
rd
with
Tim
e
…
(S
ou
fia
n
e
Ou
kili)
30
5
uses
0.
6
m
i
cron C
M
O
S
t
e
c
h
n
o
l
o
gy
[
1
4]
.
DE
S i
m
pl
em
ent
a
tion
at
[
1
5]
u
s
es
a
no
vel
m
e
t
h
o
d
fo
r i
m
pl
em
ent
i
n
g
the key schedule. This
m
e
thod supports
the use of differe
n
t keys every cl
ock cycle and
utilizes perm
utations
to
cr
eate th
e su
b-k
e
ys fro
m
th
e inpu
t k
e
y. Th
e su
b-k
e
ys ar
e d
e
layed
b
y
th
e r
e
qu
ir
ed
am
o
u
n
t
using
t
h
e
necessa
ry
arra
y
of l
a
t
c
hes
.
T
h
e Im
pl
em
ent
a
t
i
on
of
DES
at
[1
6]
i
s
ba
sed
on
t
i
m
e
vari
ab
l
e
dat
a
pe
rm
utat
i
o
n
.
Th
e d
e
sign
u
s
es an
in
itial p
e
rm
u
t
atio
n
b
o
x
th
at co
n
t
ains sev
e
ral
p
e
rm
u
t
atio
n
s
to
b
e
sel
ected
p
e
riod
ically. A
sin
g
l
e-ch
ip imp
l
em
en
tatio
n
of an
iterativ
e
DES algo
rith
m
is presen
ted
i
n
[1
7
]
.
Th
e
d
e
sign
imp
l
em
en
ted
all
DES
p
r
im
itiv
e
s
in
on
e-ro
und
sch
e
m
e
. I
m
p
l
em
en
tatio
n
in
[18
]
u
s
ed
p
i
p
e
lin
ing
techn
i
qu
es t
o
en
h
a
n
ce th
e thr
ough
pu
t
o
f
th
eir
it
er
ativ
e
d
e
sign
.
The desi
g
n
s
i
n
[1
2-
1
4
, 1
7
-
18]
use
t
h
e
i
m
pl
ement
a
t
i
on o
f
t
h
e ori
g
i
n
al
versi
o
n of DES
.
I
n
[
1
6]
,
D
E
S
i
s
i
m
p
l
e
m
en
ted
with
ti
m
e
-v
aryin
g
b
e
h
a
v
i
or.
DES with
the
p
o
s
sib
ility to
s
u
ppo
rt th
e u
s
e o
f
d
i
fferen
t keys p
e
r
dat
a
t
r
an
sfe
r
se
ssi
on i
s
pre
s
ent
e
d i
n
[1
1,
1
5
]
.
C
o
m
p
ari
ng
ou
r
pr
o
pose
d
desi
gn
wi
t
h
t
h
ese i
m
pl
em
ent
a
t
i
ons, we
co
n
c
l
u
d
e
th
at
it is
m
o
re secu
re du
e to
th
e ti
me-v
aryi
ng
b
e
h
a
v
i
or and
th
e po
ssib
ility
to
u
s
e d
i
fferent k
e
ys
every cl
ock cycle.
Tabl
e 1.
Perform
a
nce
com
p
arison
Author
s
Device
used
CLB
slices
Sy
ste
m
clock
(MHz
)
T
h
r
oughp
ut
(
M
bps)
T
h
r
oughp
ut per
slices (Mbps/slice)
Patel,
Joshi,
Saxen
a
[11]
XC3S500E
2814
111.
88
2
7160
2.
54
16-stage
pipelined
designs
Patter
s
on [12]
XCV150
1584
168
1075
2
6.
78
Biham
[13]
Alpha 8400
-
-
-
300
127
-
-
-
W
ilcox,
Pier
son,
R
ober
t
son,
W
itzke, Gass
[14]
ASI
C
-
-
-
-
-
-
9280
-
-
-
M
c
L
oone,
M
c
Can
n
y
[15]
XCV1000
6446
59.
5
3808
0.
59
Abd E
l
-
L
atif,
Ha
m
e
d,
Hasaneen
[16]
XC3S500E
2062
124.
73
4
7983
3.
87
Kaps,
Paar
[18]
XC4028E
X
741
25.
18
402.
7
0.
543
W
ong,
War
k
,
Dawson [1
7]
XC4020E
438
10
26.
7
0.
061
One
r
ound
design
From
t
h
e resul
t
s
i
n
t
h
e t
a
bl
e, we fi
nd t
h
at
ou
r 1
6
-st
a
ge p
i
pel
i
n
ed de
si
g
n
gi
ves
1.
43
9,
81.
1
4
9
,
1.
1
1
an
d 2.706
times m
o
r
e
th
ro
ug
hpu
t th
an
th
e d
e
sign
s i
n
[
1
1
,
13
-1
5
]
,
r
e
spectiv
ely. Loo
k
in
g
at t
h
e CLB slices
area co
un
t,
ou
r d
e
si
g
n
n
e
ed
s
on
ly 0
.
93
2 ti
m
e
s th
e CLB slic
e
s
use
d
i
n
[
1
1]
a
n
d 0.407 tim
es in [
1
5]
. CLB s
lices
in [13] and
[14] are not
report
ed.
Al
so f
r
o
m
t
h
e t
a
bl
e, we n
o
t
e
t
h
at
ou
r p
r
o
pos
ed
desi
g
n
gi
ves
1.
29
, 2
5
.
5
9
2
a
nd
38
5.
9
9
t
i
m
e
s
m
o
re
th
ro
ugh
pu
t th
an
th
e p
i
p
e
lin
ed d
e
sig
n
s [16
,
18
] an
d
th
e iterativ
e o
n
e
[1
7
]
. Bu
t, it n
eed
s 1
.
2
7
3
ti
m
e
s th
e CLB
sl
i
ces use
d
i
n
[
16]
,
5.
9
9
3
t
i
m
es i
n
[
17]
a
n
d
3
.
5
4
2
t
i
m
es i
n
[1
8]
.
H
o
weve
r,
o
u
r
de
si
gn
achi
e
ves
hi
g
h
e
r
th
ro
ugh
pu
t
p
e
r CLB slice th
an
th
e three
d
e
si
g
n
s
[16
-
1
8
]
.
Th
e
p
r
op
osed
d
e
sign
ach
i
ev
es on
ly 0.958
times th
r
oug
hput o
f
th
e
d
e
si
g
n
in
[
1
2
]
and need
s
1
.
657
ti
m
e
s
th
e CLB slices u
s
ed
. Howev
e
r, t
h
is d
e
sign
is no
t a sin
g
l
e-chip
i
m
p
l
e
m
en
ta
tio
n
of th
e full DES
al
go
ri
t
h
m
si
nce t
h
e key
sche
dul
e i
s
com
put
ed i
n
s
o
ft
w
a
re
and i
t
can
onl
y
sup
p
o
r
t
o
n
e
key
per
dat
a
t
r
ansfe
r
session [12].
Fro
m
th
e co
m
p
ariso
n
,
we n
o
tice th
at o
u
r im
p
l
e
m
en
tatio
n
is co
mp
etitiv
e with
th
e repo
rted
im
ple
m
entatio
ns.
It is m
o
re s
ecure
and
one
of the
fa
stest si
ngle
-
chi
p
F
P
GA
desi
gns
with area e
fficient.
7.
CO
NCL
USI
O
N
Thi
s
pape
r
pr
esent
s
a
n
ef
fi
ci
ent
im
pl
em
ent
a
t
i
on
fo
r t
h
e desi
g
n
of
a
1
6
-st
a
ge pi
p
e
l
i
n
ed
DES
al
go
ri
t
h
m
wi
t
h
t
i
m
e
vari
abl
e
sub
-
key
s
. The
al
go
ri
t
h
m
uses
di
ffe
re
nt
key
sched
u
l
e
pe
rm
ut
at
i
on ch
oi
ce 1
(PC
-1
)
peri
odi
cal
l
y
wi
t
h
t
i
m
e
. There
f
ore t
h
e ci
p
h
e
r
t
e
xt
cha
n
ges
by
tim
e
for t
h
e sa
me key and
plaintext.
As a
res
u
lt of
th
is, th
e security o
f
th
e alg
o
rith
m
is
increased. T
h
e plaintext blocks ca
n be
loaded e
v
ery c
l
ock cycle and
after
an
in
itial d
e
lay o
f
17
clo
c
k cycles, th
e ci
p
h
e
rtex
t b
l
o
c
ks will ap
p
ear
o
n
co
nsecu
tive clo
c
k
cycles. The
im
pl
em
ent
a
t
i
o
ns
of
t
h
e
D
E
S
al
g
o
ri
t
h
m
bas
e
d
on
har
d
wa
re
a
r
e
lo
w co
s
t
,
f
l
ex
ib
le
and
e
f
f
i
c
i
e
n
t en
cr
yp
tion
sol
u
t
i
o
n. T
h
e i
m
pl
em
ent
a
t
i
on of
ou
r
desi
g
n
i
s
prese
n
t
e
d
b
y
usi
ng
Spa
r
t
a
n-
3E
(XC
3
S
5
0
0
E)
fam
i
ly
FPGAs
an
d
is on
e o
f
th
e fastest h
a
rd
ware im
p
l
e
m
en
tatio
n
s
w
ith
m
u
ch greater security.
At a clock fre
quency of
1
6
1
.
03
MH
z, it
can
en
cr
y
p
t or
d
ecr
y
p
t d
a
ta
b
l
o
c
ks at a
r
a
te
of
1
030
5.95
M
b
p
s
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
6, No
. 1, Feb
r
uar
y
20
1
6
:
29
8 – 30
6
30
6
ACKNOWLE
DGE
M
ENTS
The authors gratefully ack
nowledg
e th
e sup
port o
f
Mou
l
ay Is
m
a
il
Un
iv
ersity in
th
e realizatio
n
of
th
is wo
rk
.
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