Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
V
o
l.
6, N
o
. 3
,
Ju
n
e
201
6, p
p
. 1
205
~ 12
12
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
3.9
457
1
205
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Delay Comparison for 16x16
Vedic Multiplier Using
RCA an
d CLA
M
.
B
h
ava
ni, M
.
Siva
Kuma
r, K. Srinivas
Ra
o
Department o
f
Electronics
and C
o
mmuunica
tion
Engineering, KLUniversity
, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Ja
n
6, 2016
R
e
vi
sed M
a
r
2,
2
0
1
6
Accepted
Mar 20, 2016
In an
y
integr
at
e
d
chip
com
puls
o
r
y
adders
are
re
quired b
ecaus
e
f
i
rs
t the
y
ar
e
fast and second
are th
e less power cons
umption
and delay
.
And
at th
e same
tim
e m
u
ltipl
i
ca
ti
on process is a
l
so used
in var
i
ous applic
ations
. So as th
e
speed of m
u
ltipl
i
er incr
eases th
e
n
the
speed of p
r
ocessor also inc
r
eases. And
hence we ar
e p
r
oposing the Vedic m
u
ltip
lier
using these add
e
rs. Vedic
m
u
ltiplier
is an
anci
ent m
a
the
m
atics which u
s
es m
a
inl
y
16 s
u
tras for its
operation. In th
is project we
are
usi
ng “urdhva triy
agbh
y
a
m” sutr
a to do our
process. This p
a
per proposes the Vedi
c multip
lier using th
e adders ripple
carr
y
add
e
r (RC
A
) and carr
y
loo
k
a head add
e
r (
C
LA) and puts
forward that
CLA is bet
t
er
th
an RCA.
The m
a
jor p
a
ram
e
t
e
rs
we are
sim
u
lati
ng here
are
num
ber of slices and dela
y. Th
e code is writte
n b
y
using Verilog and is
im
plem
ented usi
ng Xilinx
ISE D
e
sign Suit
e.
Keyword:
Ca
r
r
y
look
ah
ea
d
ad
d
e
r
R
i
ppl
e car
ry
a
dde
r
Ved
i
c m
u
ltip
lier
Verilog
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
K. Srini
v
as
Ra
o,
Depa
rt
em
ent
of El
ect
r
oni
cs
a
n
d
C
o
m
m
uni
cat
i
on E
n
gi
nee
r
i
n
g
,
KL Uni
v
er
sity
,
In
dia
Em
a
il: d
r
k
s
rao@k
l
u
n
i
v
e
rsity.in
1.
INTRODUCTION
Ved
i
c m
a
th
e
m
atics [1
] is an
an
cien
t m
a
th
ematics wh
ich
i
s
m
a
in
ly
u
s
ed
b
y
th
e Aryan
s
to
p
e
rfo
r
m
math
e
m
atica
l
calcu
latio
n
s
. It
con
s
ists
o
f
some su
tras
t
h
at can
p
e
rfo
r
m
larg
e arith
m
e
tic
op
eration
t
o
si
m
p
le
calculations.
After
researc
h
on 8 years
the Vedic
m
a
t
h
em
at
i
c
s
was re
no
vat
e
d
by
t
h
e great
In
di
an
math
e
m
atic
ian
Jag
a
d
guru Swam
i Sri Bh
arati Tirth
a
Ma
h
a
raj
a
. Acco
rdin
g
t
o
h
i
s research, th
is m
u
ltip
lier
tech
n
i
qu
e
con
s
ists o
f
m
a
in
ly
1
6
Ved
i
c su
tras th
at
are
ne
eded to re
duce th
e calcu
latio
n easily [2
].
Th
e Su
tras alon
g
with
th
eir
brief m
ean
in
g
s
are listed
in
[2
]
,
[3
]. Of all th
e su
tras, in
th
is pap
e
r
we are
m
a
i
n
l
y
usi
n
g
Ur
dh
va
Ti
ry
ak
bhy
am
Sut
r
a.
Th
is field
is very in
terestin
g an
d
pu
ts fo
rwar
d som
e
effective algorithm
s
which are
very m
u
ch
u
tilized
in
v
a
ri
o
u
s
bran
ch
es
of en
g
i
n
eeri
n
g su
ch as
d
i
g
ital sig
n
a
l
p
r
o
cessi
ng
an
d co
m
p
u
t
i
n
g app
licatio
n
s
. By
using t
h
e a
n
cient Ve
dic m
a
them
atic sutras, m
a
inly we
ar
e u
s
i
n
g Ur
dhv
a
Tr
iyak
bh
yam
su
tr
a i
n
th
is p
a
p
e
r t
o
p
r
esen
t a simp
le d
i
g
ital m
u
l
tip
lier arch
itectu
r
e in
wh
i
c
h
we are
usi
n
g t
w
o
di
f
f
ere
n
t
a
dde
rs l
i
k
e
ri
p
p
l
e carry
adde
r a
nd ca
rry look a
h
ea
d
adde
r.
In t
h
is pape
r we c
o
nc
lude that
Vedi
c
m
u
ltiplier with carry look
a head
ad
d
e
r is
faster th
an th
e m
u
lti
p
lier wit
h
ri
p
p
le carry
a
dde
r
and
p
r
o
p
o
se
d
adde
r s
h
ows
i
t
i
s
bet
t
e
r t
h
an
carry
lo
ok
a
h
e
ad
add
e
r.
2.
UR
DH
V
A
TI
RY
AKB
H
Y
A
M
S
U
TR
A
Urdhva
Tiryakbhyam
(Vertic
al & Cr
osswis
e) algorithm
can
be de
rive
d
f
o
r “
n
”
n
u
m
b
er of
bi
t
s
. T
h
e
main
ad
v
a
n
t
age o
f
th
is m
u
lti
p
lier is, wh
en co
m
p
ared
with
th
e o
t
h
e
r mu
ltip
liers, th
e
g
a
te d
e
lay an
d area
increases sl
owl
y
as the num
ber of bits inc
r
ea
ses [4],
[5]. T
h
e
r
efore it is well k
nown
for time, space a
nd
powe
r
efficien
t m
u
lti
p
lier. It is m
e
n
tio
n
e
d
clearly
th
at th
is
m
u
lti
p
lier arch
itectu
r
e is fu
lly efficien
t in
term
s o
f
area
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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-87
08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
12
0
5
– 12
12
1
206
an
d sp
eed
.
Since in
th
is m
u
ltip
lier th
e
p
a
rtial p
r
o
d
u
c
ts and
th
eir su
m
s
are calcu
lated
in
parallel, th
e m
u
ltip
lier
i
s
i
nde
pe
nde
nt
o
f
t
h
e
pr
oces
sor
’
s cl
oc
k
fre
que
ncy
.
The
r
e
f
o
r
e t
h
i
s
m
u
l
t
i
pl
i
e
r i
s
i
nde
pe
nde
nt
of
t
h
e
c
l
ock
fre
que
ncy
bec
a
use it will re
qui
re the sam
e
am
ount
of tim
e
to calculate the product.
By choosing t
h
is ve
dic
m
u
lt
i
p
l
i
e
r’s st
r
u
ct
u
r
e i
t
can
b
e
easi
l
y
l
a
y
out
i
n
m
i
cropr
oce
ssor
s
an
d
desi
gne
rs ca
n easi
l
y
avoi
d t
h
i
s
po
wer
of
m
u
l
tip
lier. It h
a
s qu
ite regular p
r
o
b
l
em
s t
o
avo
i
d
trag
ic d
e
v
i
ce failures so
it can
b
e
easily
in
creased
b
y
in
creasing
th
e
in
pu
t and
ou
tpu
t
d
a
ta bu
s
wid
t
h
s
. Th
e adv
a
ntage is that it reduces the
ne
ed of m
i
croprocessors
t
o
o
p
e
r
at
e at
i
n
creasi
ngl
y
hi
gh
cl
oc
k
fre
qu
enci
es.
Whi
l
e
at
t
h
i
s
hi
ghe
r
cl
ock
fre
q
u
enc
y
gene
ral
l
y
res
u
l
t
s
i
n
in
creasing
p
o
wer an
d
its d
i
sadv
an
tag
e
is th
at it also
i
n
creases p
o
w
er
di
ssi
pat
i
on
w
h
i
c
h res
u
l
t
s
i
n
hi
ghe
r
device
operating tem
p
eratures
[2].
2.
1.
Multiplicatio
n of tw
o
decima
l numbers-
12
3*4
56
To
illu
strate this
m
u
ltip
licat
io
n
,
let u
s
con
s
id
er t
h
e m
u
ltip
l
i
catio
n
of two
d
ecim
a
l
n
u
m
b
e
rs (1
23
*
4
56) sh
own
in Figu
re 1 and
l
i
n
e
d
i
ag
ram
for th
e m
u
ltip
lic
atio
n
is sho
w
n in
Fi
g
u
re
2
.
Th
e
d
i
g
its
o
n
the bo
t
h
sid
e
s o
f
t
h
e lin
e are
m
u
ltip
lie
d
and
add
e
d
with
th
e carry fr
om th
e p
r
ev
iou
s
step
. Th
is g
e
nerates o
n
e
o
f
t
h
e b
its
of
t
h
e
res
u
l
t
an
d a
car
ry
. T
h
i
s
carry
i
s
a
d
ded
i
n
t
h
e
ne
xt
st
e
p
a
n
d
hence
t
h
e p
r
oce
ss
goe
s
on
.
If
m
o
re t
h
a
n
on
e
line are t
h
ere i
n
one
step, all the res
u
lts are
adde
d t
o
the
previous ca
rry.
In eac
h ste
p
, le
ast signi
ficant
bit acts
as th
e resu
lt b
it an
d
all o
t
h
e
r bits act
as carry
for th
e n
e
x
t
step
. In
itially
th
e
carry is tak
e
n
to
b
e
zero
.
To
mak
e
this
m
e
thod m
o
re clear, an al
ternate illu
stration is gi
ven
wi
th the hel
p
of
line diagram
s
in Figure
2
whe
r
e the
dot
s
re
prese
n
t
bi
t
0 o
r
1
[
2
]
.
Fig
u
re 1
.
Mu
ltip
licatio
n
o
f
two
d
ecim
a
l
n
u
m
b
e
rs
Fi
gu
re
2.
Li
ne
di
ag
ram
of t
w
o
4
bi
t
n
u
m
b
ers
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Dela
y C
o
mpa
r
iso
n
fo
r
16
x16
Ved
i
c Mu
ltip
lier Usi
n
g RCA
a
n
d
CLA (M.
Bh
a
v
an
i)
1
207
3.
AD
DER
ST
R
UCT
URE
To
im
p
l
e
m
en
t th
is Ved
i
c m
u
ltip
lier we
u
s
e two d
i
ffe
ren
t
ad
d
e
rs i.e. Ripple Carry
Add
e
r and
Carry
l
o
o
k
Ahea
d A
d
der
.
3.
1.
Ripple Carr
y Adder
A ri
ppl
e c
a
r
r
y
adde
r i
s
a
l
o
gi
c ci
rcui
t
i
n
w
h
i
c
h t
h
e ca
rry
-o
ut
o
f
eac
h
ful
l
adde
r i
s
gi
ve
n
as t
h
e ca
rr
y
i
n
of t
h
e ne
xt
si
gni
fi
ca
nt
ful
l
adde
r w
h
i
c
h s
h
ow
n i
n
Fi
gu
re
3 [
2
]
.
It
i
s
cal
l
e
d as a ri
p
p
l
e
carry
ad
der
beca
use i
n
the next stage
each carry bit will gets ripple
d
. In a rippl
e c
a
rry adder the
sum
and carry out bits of a
n
y half
ad
d
e
r stag
e is
n
o
t
v
a
lid
un
til th
e carry
o
f
t
h
at stag
e
o
ccurs.
Th
e
reaso
n
b
e
hin
d
t
h
is is Propag
a
tio
n d
e
lay
occu
rs
in
sid
e
t
h
e log
i
c circu
it.
Fi
gu
re
3.
R
i
ppl
e carry
a
d
der
The a
b
ove
Fi
g
u
re
3
re
pre
s
ent
s
a
4×4
ri
ppl
e
carry
ad
der
stru
ctur
e. By conn
ectin
g th
ese
4
b
it ad
der
s
with
ano
t
h
e
r
4 ripp
le carry ad
d
e
rs
th
en
we will g
e
t
ou
r
1
6
×
16
ripp
le carry add
e
r structu
r
e. Th
e B
o
o
l
ean
fu
nct
i
o
n [
6
]
f
o
r s
u
m
and ca
rr
y
fo
r
4×4
ri
ppl
e carry
a
d
der
i
s
gi
ve
n a
s
f
o
l
l
o
ws
Sum
=
Ai
Β
i
Ci
Carry=Ci+1
=
Ai · Bi + (Ai
Bi) · Ci
3.
2.
Carr
y L
o
ok
Ahead Adder:
The carry look a hea
d
adde
r (CL
A
) [2] s
o
lves
the carry delay proble
m by calculating t
h
e carry
sig
n
a
ls in
ad
v
a
n
ce,
b
a
sed
on
th
e inp
u
t
sign
al
s. It is b
a
sed
on
th
e fact th
at
a carry sign
al will b
e
g
e
n
e
rat
e
d
in
two
cases: (1
)
wh
en
bo
th
b
its
Ai and
Bi are
1, or
(2
)
when on
e
o
f
th
e t
w
o bits is 1
an
d th
e
carry-i
n
is
1
Fi
gu
re 4.
C
a
rry
Lo
o
k
Ahea
d Ad
de
r
Fi
gu
re
4
[2]
re
prese
n
t
s
a
4×
4
bi
t
C
a
rry
L
o
ok
A
h
ead
A
d
der
.
B
y
con
n
ect
i
n
g
t
h
ese
4
bi
t
ad
d
e
r f
o
r
4
ti
m
e
s th
en
our
1
6
×
16
carry loo
k
ah
ead
add
e
r will b
e
ob
tained
.
Giv
e
n
t
h
e t
w
o Boo
l
ean fun
c
tio
ns [6
] for
th
e
sum
and ca
rry
fo
r
4×4
CLA
a
s
f
o
llows:
SUM =
Ai
Β
i Ci
Co
u
t
= Ci+1
=
Ai · Bi + (Ai
Bi) · Ci
If we
let:
Gi
= Ai
·
Bi
--
The Ge
nerate Fu
nction
Pi = (A
i Bi) -- Th
e pr
op
ag
ate Fun
c
tion
The
n
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
12
0
5
– 12
12
1
208
Ci+1 =
Gi + Pi
· Ci
--
The
Carry
F
u
nction
Th
us, f
o
r 4
-
bi
t
adde
r,
we
can
ext
e
nd the
carry, as s
h
own
be
low:
C1 =
G0 + P0
· C0
C2 =
G1 + P1
· C1 =
G1 +
P1
·
G0
+ P1
·
P0
·
C0
C3
=
G2
+ P2
·
G1
+ P2
·
P1
·
G0
+ P2
·
P1
·
P0
·
C0
C4
=
G3
+ P3
·
G2
+ P3
·
P2
·
G1
+ P3
·
P2
·
P1
·
G
0
+ P3
·
P2
·
P1
·
P0
· C0
4.
PROP
OSE
D
LOGIC
4.
1.
Kogge
-S
toneadder
Ko
g
g
e–
St
o
n
e
adde
r
i
s
a
para
l
l
e
l
prefi
x
fo
r
m
carry
l
ook
-a
head a
d
der
.
O
t
her
paral
l
e
l
p
r
efi
x
a
d
der
s
in
clu
d
e
th
e
Bren
t-K
ung
ad
der
,
t
h
e
H
a
ns
Car
l
son
ad
d
e
r, and th
e
f
a
stest k
now
n var
i
atio
n
,
th
e
Lyn
c
h-
Swart
z
l
a
nde
r S
p
an
ni
n
g
Tree a
dde
r. T
h
e K
o
g
g
e-
St
o
n
e ad
der
has
m
a
i
n
l
y
l
o
w l
ogi
c de
pt
h
,
hi
g
h
n
ode c
o
u
n
t
,
a
n
d
m
i
nim
a
l fan o
u
t
.
Whi
l
e
a hi
gh
no
de co
u
n
t
im
pl
i
e
s a l
a
rger area, t
h
e l
o
w l
ogi
c de
pt
h and m
i
nim
a
l fan-
o
u
t
allow faster
pe
rform
a
nce [6]. There
are m
a
inly three computational stages
i
n
Ko
gge
-St
one a
dde
r. T
h
ey
are
gi
ve
n bel
o
w
1.P
r
e
p
rocessing
2.C
a
r
r
y
gene
ra
t
i
on net
w
or
k
3.P
o
stprocessi
ng
4.
2.
Preproces
sing Stage
Pre
p
rocessing
is
the
fi
rst
stage
whe
r
e
t
h
e
gene
rate and
prop
ag
ate sig
n
a
l
s
o
f
all th
e inpu
t p
a
irs
of
si
g
n
al
s A
an
d
B
are
ge
ne
ra
t
e
d sepa
rat
e
l
y
fo
r eac
h bi
t
.
T
h
e l
o
gi
cal
eq
ua
t
i
ons
of t
h
e p
r
opa
gat
e
a
nd
ge
nerat
e
si
gnal
s
a
r
e gi
v
e
n by
t
h
e f
o
l
l
o
wi
n
g
e
quat
i
o
ns
Pi=AixorBi
Gi=Aian
d
Bi
4.
3.
Carr
y Gener
a
ti
on
St
a
g
e
Carry ge
nerati
on is the second stage of the KSA. At
this stage the carries of
all th
e b
its are g
e
n
e
rated
separately for
each
bit. T
h
ey
are
divide
d i
n
to sm
aller pi
eces and this
ove
r
all process is c
a
rried out in parallel
for all th
e b
its. Carry
g
e
n
e
rate an
d
Carry prop
ag
ate b
its
a
r
e use
d
as i
n
term
ediate signals and t
h
eir logical
equat
i
o
ns
are
g
i
ven a
s
f
o
l
l
o
ws
CPi:j
=Pi:k
+1
an
dPk
:
j
CGi:j
=Gi:k
+1
o
r
(Pi:k
+1
an
d
Gk
:
j
)
4.
4.
Pos
t
pr
ocessin
g
Th
is is t
h
e
fin
a
l step
o
r
stag
e
o
f
th
e
KSA
which
is
co
mm
o
n
fo
r
all
typ
e
s
o
f
ad
d
e
rs,
i.e. calcu
latio
n
of
sum
m
ati
on
of
t
h
e
bi
t
s
gi
ve
n
by
t
h
e l
ogi
ca
l
Eq
uat
i
ons
gi
v
e
n as
bel
o
w
C
i
–1 =
(Pi
a
n
d
C
i
n)
or
Gi
Si= Pix
or
Ci–1
Fi
gu
re 5.
1
6
×
1
6 Ko
g
g
e
st
one
Ad
de
r
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Dela
y C
o
mpa
r
iso
n
fo
r
16
x16
Ved
i
c Mu
ltip
lier Usi
n
g RCA
a
n
d
CLA (M.
Bh
a
v
an
i)
1
209
Fi
gu
re
5 re
pre
s
ent
s
a
16×
1
6
Ko
g
g
e st
o
n
e
adde
r
w
ith 4 s
t
ages. T
h
e sta
g
e-1 s
h
ows
preprocessi
ng,
st
age-
2 sh
ow
s
carry
gene
rat
i
on an
d st
age
-
3 sh
ows
po
st
p
r
oces
si
n
g
and
fi
nal
l
y
fourt
h
st
age i
s
t
h
e
out
put
represe
n
tation stage.
5.
RESULTS
Th
e 16
x16
Mu
ltip
lier is
m
a
d
e
b
y
u
s
ing
4, 8
x
8
m
u
lt
ip
lie
r sub
b
l
o
c
k
s
.
Here, th
e
m
u
ltip
lican
d
s
are
h
a
v
i
n
g
th
e
b
it size o
f
(n
=16)
wh
ereas, th
e
resu
lt is of
1
6
b
i
t in
size. Th
e i
n
pu
t is
b
r
o
k
en
in
to
sm
aller g
r
oup
s
of si
ze
of
n/
2
= 8, f
o
r b
o
t
h
i
n
p
u
t
s
, t
h
at
i
s
a and
b. T
h
ese
newl
y
f
o
rm
ed gr
o
ups
of
2
bi
t
s
are gi
ven as i
n
p
u
t
t
o
8
×
8 m
u
ltip
lier b
l
ock and
t
h
e resu
lt produ
ced
1
6
b
its,
which
are th
e ou
t
p
u
t
produ
ced fro
m
8
×
8 m
u
lti
p
lier
bl
oc
k are se
nt
fo
r ad
di
t
i
on t
o
an ad
di
t
i
on t
r
ee whi
c
h i
s
sho
w
n
as h
a
rd
ware realizatio
n
of 16
b
it m
u
lt
ip
lier in
Fi
gu
re 6.
As t
h
e
ge
neri
c
adde
r i
s
desi
gne
d t
h
e desi
g
n
i
n
g o
f
hi
g
h
bi
t
m
u
l
t
i
p
l
i
e
rs i
s
not
a
n
i
s
s
u
e u
s
i
n
g t
h
e
stru
ctural m
o
delin
g
it beco
m
e
s easy fo
r ju
st
call th
e
p
r
ed
efin
ed
co
m
p
o
n
ents and
d
e
sign
t
h
e m
u
ltip
lier.
Th
e RTL sch
e
matics fo
r
1
6
×1
6 v
e
d
i
c m
u
ltip
lier, RCA an
d CLA is sho
w
n
i
n
Fi
g
u
re 7
,
8, 9 and
cor
r
es
po
n
d
i
n
gl
y
t
h
e R
TL
fo
r t
h
e
pr
o
pose
d
1
6
×1
6
k
o
gge
st
one
ad
de
r i
s
al
so s
h
ow
n i
n
Fi
gu
re
1
0
re
spect
i
v
el
y
.
Fig
u
re
6
.
Hardware realization
o
f
16
×1
6 m
u
ltip
lier
Fig
u
re 7
.
RTL sch
e
m
a
tic
fo
r 1
6
×
16
v
e
d
i
c
m
u
ltip
lier
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
12
0
5
– 12
12
1
210
Fi
gu
re 8.
R
TL schem
a
t
i
c
for 16×
1
6
R
C
A
Fi
gu
re 9.
R
TL schem
a
t
i
c
for 16×
1
6
C
L
A
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Dela
y C
o
mpa
r
iso
n
fo
r
16
x16
Ved
i
c Mu
ltip
lier Usi
n
g RCA
a
n
d
CLA (M.
Bh
a
v
an
i)
1
211
Fi
gu
re 1
0
.
R
T
L
Sc
hem
a
ti
c
fo
r 16×
1
6
ko
g
g
e
-
st
o
n
e Ad
de
r
Tabl
e
1. C
o
m
p
ari
s
i
o
n
s
Of
1
6
×
16
Ve
di
c, R
C
A, C
L
A a
n
d
pr
op
ose
d
Ko
g
g
e-
St
one
A
d
der
Para
m
e
ters
Vedic
Multiplier
RCA
CLA
Kogge-Stone
Delay 41.
751
ns
80.
688
ns
30.
216
ns
69.
648
ns
Slices 377
64
411
60
L
U
T’
s 387
75
716
75
Bonded I
O
B’
s
64
60
64
60
Thi
s
pape
r
p
r
e
s
ent
s
t
h
e
d
e
l
a
y
f
o
r t
h
e
ve
di
c
m
u
lt
i
p
l
i
e
r, R
C
A
, C
L
A a
n
d
Ko
g
g
e st
one
a
dde
r
has t
h
e
less d
e
lay wh
en
co
m
p
ared
wi
th
th
e o
t
h
e
r
p
a
p
e
rs [7
]. Presen
ts th
at th
e Ved
i
c
m
u
ltip
lier
with
16
×1
6
b
it h
a
s a
del
a
y
of 4
1
.
7
5
1ns a
n
d ot
he
r
param
e
t
e
rs are gi
ve
n. I
n
t
h
e sa
m
e
way
[6]
sh
ows t
h
at
t
h
e R
C
A
, C
L
A a
nd
Ko
g
g
e-
sto
n
e
add
e
r
h
a
s
th
e d
e
lay
of
80
.6
88
n
s
, 78
.6
65n
s
and
69
.6
48n
s r
e
sp
ectiv
ely.
Bu
t, wh
er
eas
th
e p
a
per
[8
]
prese
n
t
s
t
h
e
C
L
A
has a
del
a
y
of
3
0
.
2
1
6
n
s
and
ot
her c
o
r
r
e
sp
on
di
n
g
par
a
m
e
t
e
rs whi
c
h
are cl
earl
y
s
h
ow
n i
n
Tabl
e 1.
Fin
a
lly th
is p
a
p
e
r presen
ts a
less d
e
lay, slices,
Lo
ok
Up
Tab
l
es an
d IO
B
’
s co
rr
esp
ond
in
g
l
y
w
h
en
com
p
ared with the ab
ov
e table. Th
e Tab
l
e 2
is listed
b
e
lo
w with
ou
r
v
a
lu
es wh
ich
are
o
b
t
ain
e
d
as fo
llo
ws
wi
t
h
devi
ce ut
i
l
i
zat
i
on
sum
m
ary
al
so.
Tabl
e
2. C
o
m
p
ari
s
i
o
n
s
Of
1
6
×
16
Ve
di
c, R
C
A, C
L
A a
n
d
pr
op
ose
d
Ko
g
g
e-
St
one
A
d
der
Para
m
e
ters
Vedic
Multiplier
RCA
CLA
Kogge-Stone
Delay 25.
825
ns
24.
686
ns
21.
028
ns
8.
955ns
Slices 350
48
25
30
L
U
T’
s 600
60
60
55
Bonded I
O
B’
s
64
50
50
65
Device Utilisation
27%
23%
23%
21%
Th
e su
mm
ary
o
f
bo
th th
e add
e
rs are g
i
v
e
n
sep
a
rate
ly,
where it is ob
served
th
at
u
tilizati
o
n of
IOB
’
s
i
s
m
o
re i
n
t
h
e
p
r
o
p
o
sed
ad
d
e
r rat
h
er
t
h
a
n
i
n
C
L
A
.
B
u
t
t
h
e am
ount
o
f
m
e
m
o
ry
st
ore
d
i
n
f
o
rm
LU
T’s a
n
d
d
e
lay are less in
th
e pro
p
o
s
ed
adde
r
when com
p
ared with CLA.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E
V
o
l
.
6,
No
. 3,
J
u
ne 2
0
1
6
:
12
0
5
– 12
12
1
212
6.
CO
NCL
USI
O
N
This
pa
per pre
s
ents a
sim
p
le and
highly effi
cien
t m
e
thod
of m
u
ltiplicatio
n m
a
inly using the “
U
rdhva
Tiryak
bh
yam
Su
tra” b
a
sed on
Ved
i
c m
a
th
e
m
atics. It is
a
meth
o
d
fo
r h
i
erarch
ical m
u
l
tip
lier d
e
si
g
n
wh
ich
cl
earl
y
i
ndi
cat
es t
h
e c
o
m
put
at
i
onal
ad
va
nt
ages
of
fere
d
by
Ve
di
c m
e
t
hod
s. T
h
e c
o
m
put
at
i
onal
pat
h
de
l
a
y
for
p
r
op
o
s
ed
1
6x16
b
it Ko
gg
e St
o
n
e
Ad
d
e
r is fo
und
to
b
e
8
.
95
5n
s. By co
m
p
aring
w
ith
th
e
trad
itio
n
a
l ad
ders, its
bet
t
e
r t
o
use t
h
e ab
ove l
ogi
c
f
o
r a
d
ders
f
o
r a
n
y
n
-
bi
t
n
u
m
b
ers,
beca
use
of
l
e
ss com
p
l
e
xi
t
y
, an
d fe
wer
n
u
m
b
er
o
f
slices, m
o
re
u
tilizatio
n
fact
o
r
, less
d
e
lay
wh
en
co
m
p
ared
with
carry loo
k
ah
ead
add
e
r.
ACKNOWLE
DGE
M
ENT
I si
ncer
el
y
t
h
ank t
o
m
y
pro
j
ect
gui
de
, w
h
o
hel
p
e
d
m
e
i
n
al
l
aspect
s of
m
y
proj
ect
t
o
com
p
l
e
t
e
i
n
sh
ort term
.
W
e
also
t
h
ank
KL Un
iv
ersity for
p
r
ov
id
ing
n
ecessary facilities to
ward
s carryin
g ou
t th
is wo
rk
.
REFERE
NC
ES
[1]
J.
Swa
m
i,
et
al
.
, “
V
edic
M
a
th
em
ati
c
s
,
”
Motilal
Banarsidas, Varnasi, India
, pp
. 40
-63, 1986
.
[2]
G. Sharma, “Delay
Comparison
of 4 b
y
4
Vedic
Multiplier
b
a
sed
on Differ
e
nt Ad
der Archit
ectures using VHDL,”
International Jo
urnal of IT, Eng
i
neer
ing and
App
lied
Sciences Research,
vol/issue: 2(6), 2013.
[3]
D. J. Udhan
i
,
“
I
m
p
lem
e
ntation
o
f
High Speed
Multipl
i
er
on FPGA,”
Internationa
l Journal of
S
c
ience, Engineerin
g
and Technolog
y
Research
, vol/is
sue: 3(2), 2014
.
[4]
A. W. R. Ahme
d, “FP
GA I
m
plementation of Vedic Multiplier U
s
ing VHDL,”
International
Journal of Emerging
Technology
and Advanced Engin
eering
, vol/issue: 4(2), 2014.
[5]
A. Chouhan and A. P.
Singh,
“I
m
p
lem
e
ntation o
f
an Effici
ent Multipl
i
er
based o
n
Vedic Mathem
ati
c
s Using High
s
p
eed add
e
r,
”
In
ternational Journ
a
l of Innovativ
e Scien
c
e,
Eng
i
neering
&
Technology
, vo
l/issue: 1
(
6), 2014
.
[6]
N. G. Nirmal, “Novel Delay
Eff
i
cient Approach
for Vedic Multip
lier with Gen
e
r
i
c Adder Module,”
In
ternationa
l
Journal of Engin
eering
Research
and
Applications
, vol/issue: 3(3),
pp. 1394-1396
,
2013.
[7]
M. Pradhan,
et al.
, “Speed C
o
m
p
arison of 1
6x16 Vedic Multipl
i
ers,”
Inter
national Journa
l of Computer
Applica
tions
, vo
l/issue: 21
(6), 20
11.
[8]
H. Go
y
a
l
and S. Akhter, “
VHDL Im
plem
entatio
n of Fast
Multiplier based on V
e
dic Math
em
ati
c
using Modified
Square Root Car
r
y
S
e
le
ct
Adder,
”
International Journal of
Comp
uter App
lica
tion
s
,
vol/issue: 127(
2), 2015
.
Evaluation Warning : The document was created with Spire.PDF for Python.