Inter
national
J
our
nal
of
Electrical
and
Computer
Engineering
(IJECE)
V
ol.
6,
No.
6,
December
2016,
pp.
3247
–
3254
ISSN:
2088-8708
3247
Lo
w
Common-Mode
Gain
Instrumentation
Amplifier
Ar
chitectur
e
Insensiti
v
e
to
Resistor
Mismatches
Zainul
Abidin
1
,
K
oichi
T
anno
2
,
Shota
Mago
3
,
and
Hir
oki
T
amura
4
1
Department
of
Materials
and
Informatics,
Uni
v
ersity
of
Miyazaki
2,3
Department
of
Electrical
and
System
Engineering,
Uni
v
ersity
of
Miyazaki
4
Department
of
En
vironmental
Robotics,
Uni
v
ersity
of
Miyazaki
Article
Inf
o
Article
history:
Recei
v
ed
Jun
29,
2016
Re
vised
Aug
18,
2016
Accepted
Sep
5,
2016
K
eyw
ord:
instrumentation
amplifier
dif
ferential
dif
ference
amplifier
resistor
mismatches
common-mode
v
oltage
biological
signal
ABSTRA
CT
In
this
paper
,
an
instrumentation
amplifier
architecture
for
biological
signal
is
pro-
posed.
First
stage
of
con
v
entional
instrumentation
amplifier
architecture
w
as
modified
by
using
fully
balanced
dif
ferential
dif
ference
amplifier
and
e
v
aluated
by
using
1P
2M
0.6
m
CMOS
process.
From
HSP
ICE
simulation
result,
lo
wer
common-mode
v
oltage
can
be
achie
v
ed
by
proposed
instrumentation
amplifier
architecture.
Actual
f
abrication
w
as
done
and
six
chips
were
e
v
aluated.
From
the
e
v
aluation
result,
a
v
erage
common-
mode
g
ain
of
proposed
instrumentation
amplifier
architecture
is
10
:
84
dB
lo
wer
than
that
of
con
v
entional
one
without
requiring
well-matched
resistors.
Therefore,
the
pro-
posed
instrumentation
amplifier
architecture
is
suitable
for
biologica
l
signal
process-
ing.
Copyright
c
2016
Institute
of
Advanced
Engineering
and
Science
.
All
rights
r
eserved.
Corresponding
A
uthor:
Zainul
Abidin
Department
of
Materials
and
Informatics,
Uni
v
ersity
of
Miyazaki
1-1,
Gakuen
Kibanadai
Nishi,
Miyazaki,
889-2192,
Japan
zainulelektro@gmail.com
1.
INTR
ODUCTION
Sensor
interf
ace
has
considerable
interests
in
medical
monitoring
and
health
care
systems.
Design
of
the
sensor
int
erf
ace
circuit
has
to
meet
some
stringent
requirements
of
analog
and
digital
blocks.
Biological
signals,
such
as
Electroencephalogram
(EEG),
Electrooculogram
(EOG),
Electrocardiogram
(ECG),
and
Elec-
tromyogram
(EMG)
are
widely
used
for
medical
and
health
care
applications
and
v
ery
weak
and
lo
w
frequenc
y
signals.
The
signals
amplitude
and
frequenc
y
spans
are
in
the
order
of
V
to
mV
and
from
DC
to
a
fe
w
kHz,
respecti
v
ely
[1]-[4].
In
order
to
acquire
and
process
the
biological
signals,
Instrumentation
Amplifier
(IA)
is
often
used
[5].
Con
v
entional
IA
architecture
sho
wn
in
Fig.
1a
is
often
emplo
yed
to
achie
v
e
high
signal-to-noise
ratio
in
first
block
of
sensor
interf
ace
[6],
[7].
It
consists
of
three
operational
amplifiers.
In
this
kind
of
IA
architecture,
lo
w
common-mode
g
ain
(
A
c
)
is
necessary
and
can
be
achie
v
ed
by
satisfying
well-matched
condition
of
resistors
netw
ork.
Ho
we
v
er
,
in
actual
f
abricated
chips,
resistor
mismatch
often
happens
and
deteriorates
the
A
c
[7].
In
this
paper
,
an
IA
architecture
which
its
A
c
is
lo
w
and
insensiti
v
e
to
resistor
mismatches
is
presented.
2.
PR
OBLEM
OF
CONVENTION
AL
INSTR
UMENT
A
TION
AMPLIFIER
ARCHITECTURE
As
mentioned
in
Chapter
1,
the
IA
architecture
sho
wn
in
Fig.1a
requires
well-matched
resistors
(
R
2
=
R
3
,
R
4
=
R
5
,
and
R
6
=
R
7
)
and
the
output
v
oltage
of
con
v
entional
IA
(
V
outc
)
can
be
determined
as
follo
ws
V
outc
=
R
7
R
5
2
R
3
R
1
+
1
(
V
in
2
V
in
1
)
(1)
J
ournal
Homepage:
http://iaesjournal.com/online/inde
x.php/IJECE
,
DOI:
10.11591/ijece.v6i6.11673
Evaluation Warning : The document was created with Spire.PDF for Python.
3248
ISSN:
2088-8708
Figure
1.
IA
architectures:
(a)
Con
v
entional
(b)
Proposed
The
V
in
1
and
V
in
2
are
defined
as
v
cm
v
dm
and
v
cm
+
v
dm
,
respecti
v
ely
(
v
cm
and
v
dm
are
common-mode
v
oltage
and
dif
ferential
input,
respecti
v
ely).
Defining
resistor
mismatch
of
R
i
as
R
i
+1
(1
+
i
+1
)
j
i
2
f
2
;
4
;
6
g
,
where
i
+1
is
mismatch
rate
of
R
i
+1
,
V
out
1
c
and
V
out
2
c
,
which
are
the
output
v
oltages
of
the
first
stage,
can
be
gi
v
en
by
V
out
1
c
=
2
R
3
(1
+
3
)
R
1
+
1
v
dm
+
v
cm
(2)
V
out
2
c
=
2
R
3
R
1
+
1
v
dm
+
v
cm
(3)
Inputting
the
V
out
1
c
and
V
out
2
c
to
the
second
stage,
which
is
the
subtractor
circuit,
V
outc
becomes
V
outc
=
R
7
R
5
2
R
3
R
1
(1
+
+
3
)
+
1
+
v
dm
+
R
7
R
5
(
1)
v
cm
(4)
where
is
coef
ficient
defined
as
follo
ws
=
R
5
+
R
7
R
5
(1+
5
)
1+
7
+
R
7
(5)
From
the
abo
v
e
deri
v
ation,
the
v
cm
cannot
be
rejected
by
the
first
stage.
From
Eq.
4,
we
can
find
the
v
cm
is
amplified
due
to
resistor
mismatches
of
the
second
stage.
Therefore,
the
resistor
mismatches
deteriorate
the
A
c
.
In
this
w
ay
,
the
A
c
of
the
con
v
entional
IA
architecture
is
sensiti
v
e
to
the
resistor
mismatches
.
3.
PR
OPOSED
INSTR
UMENT
A
TION
AMPLIFIER
ARCHITECTURE
Fig.
1b
sho
ws
the
proposed
IA
architecture.
The
proposed
IA
architecture
consists
of
2
stages;
first
stage
is
Fully
Balanced
Dif
ferential
Dif
ference
Amplifier
(FBDD
A)
with
2
ne
g
ati
v
e
feedbac
k
resistors
and
g
ain-setting
resistor
modified
from
[8]
and
second
stage
is
as
same
as
the
con
v
entional
one.
The
FBDD
A
consists
of
fully
dif
ferential
g
ain
stage
and
Common-Mode
Feed
Back
(CMFB)
circuit
and
the
output
v
oltages
of
FBDD
A
(
V
out
1
p;
2
p
)
can
be
determined
by
V
out
1
p;
2
p
=
A
f
(
V
in
2
V
in
3
)
(
V
in
1
V
in
4
)
g
(6)
where
A
is
the
amplification
of
FBDD
A,
and
should
be
v
ery
lar
ge
v
alue.
Ne
xt,
theoretical
analysis
of
the
proposed
IA
architecture
is
presented
using
the
same
manner
as
Chapter
2.
Using
(6)
and
the
V
in
1
;
2
defined
in
Chapter
2,
under
the
condition
of
well-matched
resistors,
the
output
v
oltage
of
proposed
IA
architecture
(
V
outp
)
can
be
deri
v
ed
as
same
as
Eq.
1
(
V
outc
).
Otherwise,
when
resistor
mismatches
occur
,
the
output
v
oltages
of
the
first
stage
(
V
out
1
p
and
V
out
2
p
sho
wn
in
Fig.
1b)
can
be
deri
v
ed
as
IJECE
V
ol.
6,
No.
6,
December
2016:
3247
–
3254
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
3249
Figure
2.
Circuit
schematic
of
FBDD
A
with
CMFB
circuit
follo
w
V
out
1
p
=
R
3
R
1
(2
+
3
)
+
1
v
dm
(7)
V
out
2
p
=
R
3
R
1
(2
+
3
)
+
1
v
dm
(8)
Therefore,
V
outp
in
consideration
of
resistor
mismatches
can
be
gi
v
en
as
follo
ws.
V
outp
=
R
7
R
5
R
3
R
1
(2
+
3
)
+
1
(1
+
)
v
dm
(9)
From
the
abo
v
e
deri
v
ation,
V
out
1
p
and
V
out
2
p
k
eep
the
balance
as
sho
wn
in
(7)
and
(8).
Theoretically
,
v
cm
is
rejected
perfectly
by
the
first
stage.
It
confirms
that
in
the
second
stage,
v
cm
is
also
rejected
perfectly
as
sho
wn
in
Eq.
9
e
v
en
the
resistor
mismatches
occur
.
In
this
case,
lo
w
A
c
can
be
achie
v
ed
by
the
proposed
IA
architecture.
Fig.
2
sho
ws
the
emplo
yed
FBDD
A,
which
is
modified
from
the
reference
[8].
The
FBDD
A
consis
ts
of
fully
dif
ferential
g
ain
stage
and
common-mode
feedback
(CMFB)
circuit.
T
w
o
stages
amplifier
is
emplo
yed
for
the
fully
dif
ferential
g
ain
stage,
therefore,
phase
compensation
circuits
(
R
c
2
,
R
c
3
,
C
c
2
and
C
c
3
)
are
added.
Furthermore,
CMFB
circuit
is
necessary
because
the
FBDD
A
has
dif
ferential
output.
In
this
design,
V
c
is
set
to
0
V
.
The
operational
amplifier
emplo
yed
in
second
stage,
which
is
widely
used,
is
sho
wn
in
Fig.
3
[9],
[10].
4.
EV
ALU
A
TION
In
this
chapter
,
simulation
result
and
e
v
aluation
of
actual
f
abricated
chip
are
presented.
The
IA
ar
-
chitectures
were
e
v
aluated
using
1P
2M
0
:
6
-
m
CMOS
process.
In
order
to
compare
the
performance
of
the
IA
architectures,
Fig.
3
w
as
also
emplo
yed
for
AMP1,
AMP2,
and
AMP3
in
the
con
v
entional
IA
architecture.
In
order
to
e
v
aluate
the
A
c
,
the
V
in
1
and
V
in
2
were
supplied
by
v
cm
which
is
represented
by
sine
w
a
v
e
signal
with
amplitude
of
50
mV
and
frequenc
y
of
60
Hz.
The
resistors
netw
ork
w
as
designed
by
R
1
=
51
k
and
R
2
=
R
3
=
R
4
=
R
5
=
R
6
=
R
7
=
250
k
.
Therefore,
the
ideal
total
dif
ferential
g
ain
is
20
:
7
dB.
4.1.
Simulation
r
esult
The
IA
architectures
were
simulated
using
HSPICE.
The
detailed
simulation
condition
is
sho
wn
in
T
able
1.
Representing
resistor
mismatches
condition
(
3
%),
HSPICE
si
mulation
w
as
done
under
the
mismatch
rates
5
and
7
are
estimated
to
3%
and
3%
,
respecti
v
ely
.
The
resistors
R
4
and
R
6
become
242
:
5
k
and
257
:
5
k
,
respecti
v
ely
.
Fig.
4a
sho
ws
the
FFT
simulation
result
of
V
outc
and
V
outp
.
At
frequenc
y
60
Hz,
the
Low
Common-Mode
Gain
Instrumentation
Amplifier
Ar
c
hitectur
e
Insensitive
to
...
(Zainul
Abidin)
Evaluation Warning : The document was created with Spire.PDF for Python.
3250
ISSN:
2088-8708
Figure
3.
Circuit
schematic
of
an
operational
amplifier
v
cm
of
the
con
v
entional
and
proposed
IA
architectures
reach
57
:
9
dBV
and
103
:
5
dBV
,
respecti
v
ely
.
The
proposed
IA
architecture
has
45
:
6
dBV
lo
wer
common-mode
v
oltage
than
the
con
v
entional
one.
Monte
Carlo
simulation
w
as
done
by
500
times
to
get
data
of
A
c
with
de
viation
of
resistor
mismatch
3
%
(
R
1
R
7
).
Fig.
4b
sho
ws
histogram
of
A
c
.
A
v
erage
A
c
of
the
proposed
and
con
v
entional
IA
architec-
tures
are
90
:
6
dB
and
44
:
9
dB,
respecti
v
ely
.
The
a
v
erage
A
c
of
the
proposed
IA
archi
tecture
is
lo
wer
than
that
of
the
con
v
entional
one.
Lastly
,
the
simulated
performance
of
the
IA
architectures
are
listed
in
T
able
2.
4.2.
Chip
e
v
aluation
In
order
to
confirm
the
actual
performance,
six
chips
of
the
IA
architectures
were
f
abricated.
Fig.
5
sho
ws
the
microphotograph
of
the
f
abricated
chip.
Due
to
the
number
of
transistors
used
in
FBDD
A,
the
chip
area
of
the
proposed
IA
architecture
is
lar
ger
than
that
of
the
con
v
entional
one.
Six
chips
were
e
v
aluated
by
gi
ving
v
cm
in
the
form
of
a
sine
w
a
v
e
with
100
mV
p
p
and
60
Hz.
Fig.
6
sho
ws
FFT
measurement
result
of
V
outc
and
V
outp
of
chip
no.
3
(see
T
able
3).
At
the
frequenc
y
of
60
Hz,
the
V
outp
and
V
outc
reach
88
dBV
and
74
dBV
,
respecti
v
ely
.
It
indicates
that
the
v
cm
of
V
outp
14
dBV
lo
wer
than
that
of
V
outc
.
Re
g
arding
the
gi
v
en
v
cm
v
alue,
the
A
c
of
the
six
chips
are
calculated
and
summarized
in
T
able
3.
A
v
erage
A
c
of
the
con
v
entional
and
proposed
IA
architectures
ar
e
42
:
8
dB
and
53
:
64
dB,
respecti
v
ely
.
From
these
results,
under
the
condition
of
actual
f
abrication
result
(random
resistor
mismatches),
the
A
c
of
the
proposed
IA
architecture
is
lo
wer
than
that
of
the
con
v
entional
one.
The
v
cm
of
proposed
IA
architecture
is
not
perfectl
y
rejected
as
mentioned
in
the
theoretical
analysis
because
transistor
mism
atch
w
as
Figure
4.
(a)
FFT
results
of
V
outc
and
V
outp
(b)
Histogram
of
A
c
(dBV)
based
on
Monte
Carlo
analysis
IJECE
V
ol.
6,
No.
6,
December
2016:
3247
–
3254
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
3251
T
able
1.
Simulation
Condition
Items
V
alue
CMOS
process
1P
2M
0
:
6
-
m
CMOS
V
dd
[V]
2
:
5
V
ss
[V]
2
:
5
V
c
[V]
0
R
bias
[k
]
295
M
1
;
2
[
m/
m]
1
:
3
/
2
,
M
=
2
M
3
10
[
m/
m]
1
:
3
/
2
,
M
=
4
M
11
20
[
m/
m]
16
:
1
/
3
,
M
=
2
M
21
29
[
m/
m]
3
:
3
/
2
,
M
=
2
R
c
1
3
[k
]
9
C
c
1
4
[pF]
0
:
5
Note:
M
means
the
number
of
parallel
connection
T
able
2.
Summary
of
the
Simulation
Results
P
arameters
Con
v
entional
IA
Proposed
IA
A
C
analysis
Dif
ferential
g
ain
[dB]
20
:
7
20
:
7
3
dB
g
ain
bandwidth
[KHz]
254
:
2
301
:
6
Po
wer
cons.
[W]
596
:
3
843
:
8
Monte
Carlo
analysis
A
v
e.
Ac
[dB]
44
:
9
90
:
6
Noise
perf
ormance
(PV)
Input
ref.
noise
[
V/
p
H
z
]
90
:
4
93
:
5
Output
ref.
noise
[
V/
p
H
z
]
972
:
4
1000
Note:
PV
=
Peak
V
alue
not
considered
in
this
paper
.
Radiated
po
wer
supply
noise
with
frequenc
y
of
60
Hz
is
also
actual
problem.
5.
CONCLUSION
In
this
paper
,
an
IA
architecture
based
on
FBDD
A
has
been
presented.
Resistor
mismatch
which
de
grades
the
performance
of
con
v
entional
IA
architecture
ha
v
e
been
identified
and
compared
in
theoretical
analysis,
simulation
and
actual
chip
f
abrication.
Its
ability
to
achie
v
e
lo
w
common-mode
g
ain
e
v
en
the
resistors
are
not
well-matched
mak
es
it
suitable
as
a
part
of
inte
grated
circuit
for
biological
signal
processing.
As
other
performance
parameters,
transistor
mismatch
ef
fect
and
of
fs
et
v
oltage
cancellation
are
considered
as
future
w
ork.
A
CKNO
WLEDGEMENT
This
w
ork
is
supported
by
VLSI
Design
and
Education
Center
(VDEC),
the
Uni
v
ersity
of
T
ok
yo
in
collaboration
with
Synopsys,
Inc.
and
Cadence
Design
Systems,
Inc.
REFERENCES
[1]
Xiaodan
Zou,
Xiao
yuan
Xu,
Libin
Y
ao,
and
Y
ong
Lian,
”A
1-V
450-nW
fully
inte
grated
programmable
biomedical
sensor
interf
ace
chip,
”
IEEE
J.
Solid-State
Circuits
,
v
ol.
44,
no.
4,
pp.
1067-1077,
Apr
.
2009.
[2]
Jos
Hulzink,
et
al.,
”An
Ultra
Lo
w
Ener
gy
Biomedical
Signal
Processing
System
Operating
at
Near
-
Threshold”.
IEEE
T
ransactions
On
Biomedical
Circuits
And
Systems
,
v
ol.
5,
no.
6,
pp.
546-554,
Dec.
2011.
[3]
Chih-Jen
Y
en,
W
en-Y
a
w
Chung
and
Mely
Chen
Chi.
”Micro-Po
wer
Lo
w
Of
fset
Instrumentation
Amplifier
IC
Design
F
or
Bio-Medical
System
Applications”.
IEEE
T
ransactions
On
Circuits
And
Systems-I:
Re
gular
Low
Common-Mode
Gain
Instrumentation
Amplifier
Ar
c
hitectur
e
Insensitive
to
...
(Zainul
Abidin)
Evaluation Warning : The document was created with Spire.PDF for Python.
3252
ISSN:
2088-8708
Figure
5.
Microphotograph
of
the
IA
architectures
T
able
3.
A
c
of
the
IA
Architectures
Chip
no.
Con
v
entional
(dB)
Proposed
(dB)
1
44
:
97
50
:
97
2
42
:
97
56
:
97
3
44
:
97
58
:
97
4
41
:
97
54
:
97
5
40
:
97
50
:
97
6
40
:
97
48
:
97
P
apers
,
v
ol.
51,
no.
4,
pp.
691-699,
Apr
.
2004.
[4]
Akshay
Goel
and
Gurmohan
Singh,
”A
No
v
el
Lo
w
Noise
High
Gain
CMOS
Instrumentation
Amplifier
for
Biomedical
Applications,
”
IAES
International
Journal
of
Electri
cal
and
Computer
Engineering
,
v
ol.
3,
no.
4,
pp.
516-523,
Aug.
2013.
[5]
N.
V
.
Helleputte,
et
al.,
”A
Multi-P
arameter
Signal-Acquisition
SoC
for
Connected
Personal
Health
Appli-
cations”,
IEEE
International
Solid-State
Circuits
Conference
,
pp.
314-315,
Febr
.
2014.
[6]
J.
Szyno
wski,
”CMRR
analysis
of
instrumentation
amplifiers,
”
Electronics
Letters
,
v
ol.
19,
no.
14,
pp.
547-549,
1983.
[7]
Hw
ang-
Cherng
Cho
w
and
Jia
-Y
u
W
ang,
”High
CMRR
instrumentation
amplifier
for
biomedical
appli-
cation,
”
Proc.
IEEE
International
Symposium
on
Signal
Processing
and
Its
Applications
,
pp.
1-4,
Febr
.
2007.
[8]
A.
Hussain
and
I.
Mohammed,
”
A
CMOS
fully
balanced
dif
ferential
dif
ference
amplifier
and
its
applica-
tions,
”
IEEE
T
rans.
on
Circuits
and
Systems-II:
Analog
and
Digital
Signal
Processing
,
V
ol.
48,
No.
6,
pp.
614-620,
June
2001.
[9]
P
.
E.
Allen
and
D.
R
.
Holber
g,
CMOS
Analog
Circuit
Design
,
Second
Edition.
Oxford
Uni
v
ersity
Press,
Ne
w
Y
ork,
2002.
[10]
N.
Mukahar
and
S.
H.
Ruslan,
”A
93.36
dB,
161
MHz
CMOS
Operational
T
ransconductance
Amplifier
(O
T
A)
for
a
16
Bit
Pipeline
Analog-to-Digital
Con
v
ert
er
(ADC)
,
”
IAES
International
Journal
of
Electrical
and
Computer
Engineering
,
v
ol.
2,
no.
1,
pp.
106-111,
Feb
.
2012.
IJECE
V
ol.
6,
No.
6,
December
2016:
3247
–
3254
Evaluation Warning : The document was created with Spire.PDF for Python.
IJECE
ISSN:
2088-8708
3253
Figure
6.
FFT
measurement
result
of
chip
no.
3
(
V
outc
and
V
outp
)
BIOGRAPHIES
OF
A
UTHORS
Zainul
Abidin
w
as
born
in
1986.
He
recei
v
ed
the
B.
Eng.
from
Uni
v
ersity
of
Bra
wijaya
and
M.
Eng.
from
Uni
v
ersity
of
Miyazaki
in
2008
and
2011,
respecti
v
ely
,
and
is
currently
w
orking
for
Uni
v
ersity
of
Bra
wijaya
and
to
w
ard
the
PhD
de
gree
in
Department
of
Materials
and
Informatics
at
Uni
v
ersity
of
Miyazaki.
He
has
been
in
v
olv
ed
with
design
of
analog
inte
grated
circuit
since
Master
De
gree.
His
current
research
interest
includes
analog
circuit
for
biological
signal
processing.
He
is
af
filiated
with
IEEE
as
student
member
.
K
oichi
T
anno
w
as
born
in
Miyazaki,
Japan,
on
A
pril
22,
1967.
He
rece
i
v
ed
B.
E.
and
M.
E
.
de-
grees
from
the
F
aculty
of
Engineering,
Uni
v
ersity
of
Miyazaki,
Miyazaki,
Japan,
in
1990
and
1992,
respecti
v
ely
,
and
Dr
.
Eng.
de
gree
from
Graduate
School
of
Science
and
T
echnology
,
K
umamoto
Uni
v
ersity
,
K
umamoto,
Japan,
in
1999.
From
1992
to
1993,
he
joined
the
Microelectroni
cs
Prod-
ucts
De
v
elopment
Laboratory
,
Hitachi,
Ltd.,
Y
ok
ohama,
Japan.
He
w
as
eng
aged
in
research
on
lo
w-v
oltage
and
lo
w-po
wer
equalizer
for
read
channel
LSI
of
hard
disk
dri
v
e
s.
In
1994,
he
joined
Uni
v
ersity
of
Miya
zaki,
where
he
is
currently
a
Professor
in
the
Department
of
Electrical
and
Sys-
tems
Engineering.
His
main
research
interests
are
in
analog
inte
grated
circuit
design
and
multiple-
v
alued
logic
circuit
design.
Dr
.
T
anno
is
a
member
of
IEEE
and
the
Ex
ecuti
v
e
Subcommittee
of
the
IEEE
Computer
Society
T
echnical
Committee
on
Multiple-V
alued
Logic.
Shota
Mago
w
as
born
in
1992.
He
recei
v
ed
the
B.Eng
from
Uni
v
ersity
of
Miyazaki
in
2015,
and
is
currently
studying
to
get
m
aster
de
gree
of
Electrical
and
Electronic
Engineering
at
Uni
v
ersity
of
Miyazaki.
His
current
research
is
Analog
CMOS
Inte
grated
Circuits.
Low
Common-Mode
Gain
Instrumentation
Amplifier
Ar
c
hitectur
e
Insensitive
to
...
(Zainul
Abidin)
Evaluation Warning : The document was created with Spire.PDF for Python.
3254
ISSN:
2088-8708
Hir
oki
T
amura
recei
v
ed
the
B.E
and
M.E
de
gree
from
Miyazaki
Uni
v
ersity
in
1998
and
2000,
respecti
v
ely
.
From
2000
to
2001,
He
w
as
an
Engineer
in
Asahi
Kasei
Corporation,
Japan.
In
2001,
He
joined
T
o
yama
Uni
v
ersity
,
T
o
yama,
Japan,
where
He
w
as
a
T
echnical
Of
ficial
in
Department
of
Intellectual
Inf
ormation
Systems.
In
2006,
He
joined
Miyazaki
Uni
v
ersity
,
Miyazaki,
Japan,
where
He
w
as
an
Assistant
Professor
in
Department
of
Electrical
and
Electronic
Engineering.
In
2012,
He
is
currently
an
Associate
Professor
in
the
Department
of
En
vironmental
Robotics.
His
main
research
interests
are
Neural
Netw
orks
and
Optimization
Problems.
In
recent
years,
He
has
the
interest
in
Biomedical
Signal
Processing
using
Soft
Computing.
IJECE
V
ol.
6,
No.
6,
December
2016:
3247
–
3254
Evaluation Warning : The document was created with Spire.PDF for Python.