Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
Vol.
4, No. 6, Decem
ber
2014, pp. 831~
836
I
S
SN
: 208
8-8
7
0
8
8
31
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Effect of
Parasiti
c El
ements on
the Performance of Buck-Boost
Converter for PV Systems
Subr
amanya Bhat*,
Nagar
aja H N
**
* Department of
Electronics and
Co
mmunication Engineering,
Canara Engi
n
eerin
g Coll
ege,
M
a
ng
alore
,
Ind
i
a
** Indus Institu
t
e
of
Technolog
y
and Eng
i
neering
,
Ahm
e
dabad
,
G
u
jarath, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Aug 16, 2014
Rev
i
sed
O
c
t 11
, 20
14
Accepted Oct 22, 2014
In the proposed
stud
y
,
MOSFET device us
ed in
buck-boost conv
erter
for PV
s
y
ste
m
s is studie
d
.
The
pa
ra
me
te
r of
MOSFET
Rds (on) is var
i
ed and
its
effect on outpu
t voltag
e
is studied.
Th
e p
a
ras
i
t
i
c
el
em
ents
in
in
ductor and
capacitor
such
as resistan
ce
on buc
k-boost
converter perfo
rmance ar
e
studied. From the proposed stud
y
it has been
foun
d that the effect
of parasitic
res
i
s
t
anc
e
in c
a
p
aci
tor is
les
s
a
s
com
p
ared to
paras
i
t
i
c res
i
s
t
a
n
ce eff
e
c
t
of
inductor
.
Also the proposed stud
y
gives be
t
t
er i
n
sight into paras
itic effect of
Printed Cir
c
uit
Board and l
o
sses incurre
d due
to the
sa
me
. In
PV sy
ste
m
s
buck-boost converter is used to convert
solar
energ
y
to electrical ener
g
y
which is
then s
t
ored in batte
r
y
t
o
drive the load
s
.
Thes
e paras
i
t
i
c
elem
ents
will h
a
ve
consi
d
erabl
e
effect o
n
the perform
an
ce of
buck-boos
t conv
erter
such as
efficien
cy
and ou
tput voltage
as validated
b
y
exper
i
mental
results.
Keyword:
Non
i
d
ealities
Parasitic resist
an
ce
Stray capacitance
Stray ind
u
c
tance
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Subram
anya Bhat
Depa
rt
m
e
nt
of
El
ect
roni
cs
an
d C
o
m
m
uni
cati
on
En
gi
nee
r
i
n
g
C
a
nara En
gi
ne
eri
n
g
C
o
l
l
e
ge
Ban
t
w
a
l, Mang
alor
e-5
7
4
21
9, Ind
i
a
Em
a
il: sb
h
a
t22@yaho
o.co
m
1.
INTRODUCTION
In
rece
nt years re
newa
ble e
n
ergy
has
g
a
ined
m
o
re im
p
o
r
tan
ce, du
e t
o
fo
ssil
fu
el exhau
s
tion
an
d
increase i
n
environm
ental problem
s becaus
e
of
conven
tional power
ge
neration. PV sy
ste
m
is one
of the
rene
wa
bl
e ene
r
gy
s
o
u
r
ces.
F
o
r c
o
nve
rt
i
n
g
sol
a
r e
n
er
gy
t
o
electrical energy a
go
od
ef
f
i
cien
t
b
u
c
k-
bo
o
s
t
conve
r
ter is ne
eded. In bu
ck-boost converte
r, a indu
ctor, a
capacitor and a MOSFET s
w
itch is used. In all
th
ese th
ere are p
a
rasitic elemen
ts wh
ich
affect th
e
p
e
rform
an
ce o
f
b
u
c
k
-
bo
o
s
t co
nv
erter. In
th
e
p
r
op
o
s
ed
stu
d
y
, effects
of
p
a
rasitic elemen
ts are
d
i
scu
ssed
in
d
e
ta
il. Th
e effect
o
f
filter ele
m
en
ts in
du
ctor and
cap
acito
r
on
t
h
e
per
f
o
rm
ance
of
b
u
c
k
c
o
n
v
e
r
t
e
r i
s
di
s
c
usse
d i
n
[
1
]
.
The
per
f
o
rm
ance pa
ram
e
t
e
rs suc
h
as
ri
p
p
l
e
cont
e
n
t
in
th
e
o
u
t
p
u
t
cu
rren
t an
d vo
ltag
e
, efficien
cy
an
d
reg
u
l
a
tion
are st
ud
ied
.
Bu
t th
e p
a
rasitic ele
m
en
ts effect on
t
h
e pe
rf
o
r
m
a
nce o
f
buc
k-
b
o
o
s
t
co
nve
rt
er i
s
not
di
sc
usse
d.
DC
-
D
C
s
w
i
t
c
h
i
ng c
o
nve
rt
ers
are
di
scusse
d i
n
[2]
an
d
h
e
re t
h
e effect o
f
p
a
rasitic ele
m
en
ts o
n
v
o
ltag
e
co
n
v
e
rsio
n
rati
o
is d
i
scu
ssed
.
Du
e t
o
p
a
rasitic ele
m
en
ts
v
o
ltag
e
g
a
in
red
u
c
es and
th
is
g
a
in
redu
ction
is av
o
i
d
e
d
b
y
li
m
i
tin
g
th
e du
t
y
ratio
. Du
e to
p
a
rasitic elem
e
n
t up
to
certain
v
a
l
u
e o
f
du
ty ratio th
e g
a
in
in
creases after
that
gain re
duces drastically. The effect of pa
rasitic
ele
m
en
ts in
ind
u
c
t
o
r is con
s
id
ered
. B
u
t the effect
o
f
p
a
rasitic ele
m
en
t
s
p
r
esen
t i
n
MOSFET swit
ch
an
d
cap
acito
r are
no
t con
s
i
d
ered
.
Nur M
o
h
a
mmad
et.
Al [3
] d
i
scu
ssed
o
n
p
a
rasitic effects on
th
e p
e
rfo
r
m
a
n
ce
of
DC
-
D
C
Si
n
g
l
e
En
ded
Pri
m
ary
In
duct
o
r C
o
nve
rt
er
(SEP
I
C
) i
n
P
hot
ov
ol
t
a
i
c
appl
i
cat
i
ons.
In t
h
i
s
pa
p
e
r, t
h
e
effect of p
a
rasi
tic ele
m
en
ts o
n
th
e p
e
rfo
rm
a
n
ce o
f
DC-DC
SEPIC in
PV
syste
m
s
is d
i
scu
ssed
.
Th
e
p
a
rasitic
el
em
ent
i
n
i
nduct
o
r use
d
i
n
con
v
e
r
t
e
r i
s
va
ri
ed an
d i
t
s
eff
ect
on o
u
t
p
ut
vol
t
a
ge
has be
en seen
. It
has
bee
n
foun
d
th
at th
e g
a
in
and
th
e efficien
cy are red
u
c
ed
.
In
th
is p
a
p
e
r it is
m
e
n
tio
n
e
d
th
at the effects o
f
p
a
rasitic
shoul
d
be c
onsidere
d
to im
prove
accu
racy,
perform
a
nce stability and
robust
ness
of t
h
e
conve
r
ter. B
u
t
only
in
du
ctor p
a
rasitic resistan
ces are con
s
id
ered an
d
cap
ac
itor
p
a
rasitic resistan
ces are no
t co
nsid
ered
.
Also
the
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE Vol. 4, No. 6, D
ecem
ber 2014
:
831 – 836
83
2
effects of p
a
rasitic ele
m
en
ts
p
r
esen
t in
MOSFET switc
h
are no
t co
n
s
i
d
ered
. Th
e vo
ltage d
e
grad
ation
wh
en
non idealities such a
s
pa
rasitic resist
ance of inductor
and
sour
ce re
sistanc
e
are take
n int
o
account is di
scusse
d
in
[4
]. Th
e p
a
p
e
r
d
i
scu
sses ab
ou
t efficien
cy d
e
grad
atio
n
of th
e con
v
e
rter wh
en
th
e p
a
rasitic resistan
ces are
co
nsid
ered
. B
u
t on
ly in
du
cto
r
an
d
sou
r
ce p
a
rasitic
resistan
ces are
co
nsid
ered
and
cap
acit
o
r
parasitic
resistan
ce is no
t con
s
id
ered. Also
the effects o
f
p
a
rasitic ele
m
en
ts p
r
esen
t in
MOSFET switch
are n
o
t
con
s
i
d
ere
d
.
Th
e sm
al
l
si
gnal
ac equi
val
e
nt
ci
rcui
t
m
odel
for
buc
k
-
b
o
o
st
con
v
e
r
t
e
r i
s
de
vel
o
ped i
n
[
5
]
.
The
ch
aracteristics ou
tpu
t
vo
ltage as a
fun
c
tion
o
f
du
ty ra
tio
is
n
o
n
lin
ear bu
t th
is
h
a
s
b
een lin
earised
wh
ile
devel
opi
ng t
h
e
m
odel
.
The ef
fect
of wi
n
d
i
n
g
resi
st
ance i
n
i
n
d
u
ct
o
r
i
s
co
ns
i
d
ere
d
w
h
i
l
e
devel
o
pi
n
g
t
h
e
m
odel
.
In t
h
e
pr
o
pose
d
st
u
d
y
,
M
O
S
F
ET m
odel
fr
om
Sim
u
li
nk i
s
consi
d
ere
d
.
The va
ri
o
u
s
pa
ram
e
t
e
rs i
n
MOSFE
T
m
o
d
e
l are d
i
scu
ssed
in
section
2. Effect
o
f
p
a
rasitic el
em
e
n
t in
MOSFET is d
i
scu
s
sed
i
n
Sectio
n
3
.
Effect o
f
p
a
rasitic elem
e
n
t in
ind
u
c
t
o
r i
s
d
i
scu
s
sed
in
Sectio
n
4
.
Effect o
f
p
a
rasitic ele
m
en
t in
cap
acito
r is d
i
scussed
in
Sect
i
on 5.
2.
EFFECT OF
PARASITI
C ELEMENT
IN MOSFET
For t
h
e pr
o
pos
ed w
o
r
k
t
h
e M
O
SFE
T m
odel
from
Sim
u
l
i
n
k has be
en c
h
o
s
en. T
h
e M
O
S
F
ET m
odel
an
d
its eq
u
i
v
a
l
e
n
t
circu
it is sh
own
in
Fi
gu
re 1
Th
e MOSFET d
e
v
i
ce is co
nn
ected in
p
a
rallel with
an
i
n
tern
al
diode that t
u
rns on
whe
n
t
h
e
MOSFET
device is reve
rse
biased. T
h
is internal
diode is
provide
d
t
o
protect
agai
nst
re
ve
rse
vol
t
a
ge
. T
h
e m
odel
i
s
done
usi
n
g an i
d
eal
swi
t
c
h an
d i
t
i
s
t
u
rne
d
ON
or
OFF
usi
n
g
a gat
e
sig
n
a
l
g
.
Th
e dio
d
e
is conn
ected
in p
a
rallel with
th
e switch.
Fi
gu
re
1.
M
O
S
F
ET a
n
d
i
t
s
eq
ui
val
e
nt
ci
rcui
t
Th
e
ON state vo
ltag
e
o
f
MOSFET
Vd
s will
v
a
ry acco
r
d
i
ng to
fo
llowing
asp
ects
W
h
en
M
O
SFET is tu
rn
ed
ON
Vd
s=R
d
s(on
)*
I
wh
er
e I
is th
e cur
r
e
n
t
f
l
ow
ing
thr
ough
th
e
d
e
v
i
ce
wh
en
it is t
u
rned
ON.
Wh
en
t
h
e
d
e
v
i
ce is tu
rn
ed
OFF, an
ti-p
a
rallel d
i
od
e starts con
d
u
c
ting
then
Vd
s = R
d
*I-Vf +Lon*
d
i/d
t
wh
ere Vf is th
e in
tern
al
di
o
d
e f
o
r
w
ar
d
vo
l
t
a
ge dr
op
. Th
e ant
i
-
pa
ral
l
e
l
di
o
d
e
i
n
d
u
ct
ance i
s
d
e
not
e
d
as Lo
n
and i
t
i
s
used
onl
y
f
o
r c
ont
i
n
uo
us sy
st
em
s.
For
di
scret
e
sy
st
em
s t
h
i
s
has been
set to
zero. The in
itial cu
rrent is d
e
n
o
t
ed
as
Ic and
it is
th
e in
itial v
a
lu
e o
f
cu
rren
t th
at fl
o
w
s i
n
th
e MOSFET.
Fo
r t
h
e stead
y
state an
alysis th
e in
itial cu
rren
t sh
ou
ld
b
e
co
n
s
i
d
ered
.
Sn
ubb
er
resistan
ce Rs and
Sn
ubb
er
capaci
t
a
nce C
s
are
use
d
i
n
t
h
e m
odel
t
o
gi
v
e
pr
ot
ect
i
o
n a
g
ai
nst
d
v
/
d
t
.
Th
e M
O
SF
ET
bl
ock
i
m
pl
em
ent
e
d i
n
si
m
u
lin
k
is a macr
o
m
o
d
e
l o
f
th
e MO
SFET. I
t
w
ill n
o
t
con
s
id
er
th
e dev
i
ce g
e
o
m
etr
y
a
n
d
co
m
p
lex
physical
p
r
o
cesses involv
e
d
in
f
a
br
icatio
n
of
th
e d
e
vice [
2
]. Th
e M
O
SFET b
l
o
c
k
av
ailab
l
e in
sim
u
l
i
n
k
shou
ld
n
o
t
b
e
connected in
series with
an in
du
ctor, a cu
rren
t sou
r
ce, un
less its snu
b
b
e
r circu
it is in
u
s
e.
Th
e d
e
si
gn
sp
ecification
of
b
u
c
k
-
bo
ost co
nv
erter is as fo
llo
ws:
-
In
p
u
t
v
o
l
t
a
ge =
5 t
o
20
V
-
Out
put
v
o
l
t
a
ge
= -
1
2V
-
Sw
itch
i
ng
f
r
e
qu
en
cy = 50
KH
z
-
Wattag
e
ratin
g
=
25
Watt
-
In
d
u
ct
or
ri
ppl
e
cu
rre
nt
(
∆
)
=
3% of
-
Out
put
V
o
l
t
a
g
e
R
i
ppl
e (
∆
) =
0.
01
*
=0.12
-
The
b
u
ck
-b
o
o
s
t
con
v
e
r
t
e
r i
s
d
e
si
gne
d a
n
d t
h
e val
u
e
s
obt
ai
n
e
d a
r
e
-
In
d
u
ct
or
L=
1.
5
-
Cap
acito
r C=22
0
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Effect o
f
Pa
ra
sitic Elemen
ts
on
th
e Performan
ce
o
f
Bu
ck-Boo
s
t Con
verter f
o
r … (Sub
ra
ma
n
y
a
Bha
t
)
83
3
Th
e
b
u
c
k-boo
st co
nv
erter is
si
m
u
lated
with th
ese
valu
es
an
d
it
h
a
s
b
e
en
fou
n
d
that it
m
eets th
e
sp
ecification
s
.
Th
e sim
u
latio
n
d
i
ag
ram
is s
h
own
in
Figur
e 2
.
Th
e p
a
rasitic resistan
ce Rd
s(o
n
) p
l
ays
a ro
le
wh
en
t
h
e switch
is cl
o
s
ed
. Th
e effect M
O
SFET
p
a
rasitic
resistan
ce R
d
s(on
) on
ou
tpu
t
vo
ltag
e
is
ob
served
and i
t
i
s
as sho
w
n i
n
Fi
g
u
r
e
3. R
d
s (
o
n)
com
put
es
power los
s
and efficiency
in a
circuit contai
ning a
M
O
SFET
s
w
i
t
c
h.
The
po
wer
di
ssi
pat
e
d
i
n
t
h
e M
O
S
F
ET i
s
gi
ve
n
by
t
h
e
pr
od
uct
of
R
d
s(
o
n
)
an
d
d
r
ai
n
cu
rre
nt
.
In Fig
u
re 3, se
ries
1 rep
r
ese
n
ts
fo
r
Rds
(
on
) value
e
q
ual
to 0
Ω
, se
ries 2
re
prese
n
ts f
o
r R
d
s(
o
n
)
value
e
qual t
o
0.
00
1
Ω
, se
ries 3 rep
r
ese
n
ts fo
r Rds(
o
n
) val
u
e equal to 0.
0
5
Ω
and seri
es 4
rep
r
ese
n
t
s
fo
r R
d
s(
on
) val
u
e equa
l
to
0.08
Ω
. I
t
h
a
s
b
e
en
ob
s
e
rv
ed
th
a
t
as
th
e v
a
lu
e
of
R
d
s(on) increases
the ou
tput voltage
decreases.
Fi
gu
re
2.
B
u
c
k
-B
o
o
st
C
onv
ert
e
r Sim
u
latio
n
Diagram
Fi
gu
re 3.
Ef
fec
t
of
R
d
s
(
O
n
) o
n
out
put
v
o
l
t
a
g
e
Tabl
e 1.
Ef
fec
t
of
R
d
s
(
O
n
) o
n
out
put
v
o
l
t
a
g
e
Rds(
on)
Output
voltage
Rds=0
Ω
-
11.
95V
Rds=0.
001
Ω
-
11.
85V
Rds=0.
05
Ω
-
11.
27V
Rds=0.
08
Ω
-
10.
92V
‐
14
‐
12
‐
10
‐
8
‐
6
‐
4
‐
2
0
2
1
384
767
1150
1533
1916
2299
2682
3065
3448
3831
4214
4597
4980
5363
5746
Output
Voltage
Time
samples
Series1
Series2
Series3
Series4
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE Vol. 4, No. 6, D
ecem
ber 2014
:
831 – 836
83
4
3.
EFFECT OF
PRI
N
TED
CI
RC
UIT BO
A
R
D
(P
CB)
PA
RA
SITIC
S
The co
nt
ri
but
i
on
of st
ray
i
n
d
u
ct
ances a
nd c
a
paci
t
a
n
ces are
prese
n
t in PC
BS. These a
r
e considere
d
as
p
a
rasitic elem
e
n
ts fro
m
PCB. Power l
o
ss
du
e to
tr
ace is g
i
v
e
n
b
y
Ptrace and
th
is is g
i
v
e
n
b
y
(1
)
Power l
o
ss
due
to stray i
n
duct
ance is called a
s
P
Lstra
y
an
d
it i
s
calcu
lated
as
(2
)
whe
r
e L
s
tray is calculated
from
2
∗
1
0
ln
0
.
2
0.
5
(3
)
The st
ray capa
c
itance is calculated as
0
.085
/
(4
)
The st
ray capa
c
itance power l
o
ss
P
cstra
y
i
s
gi
ven
by
2
(5
)
Th
e t
o
tal lo
ss i
n
PCB is g
i
v
e
n b
y
P
pcb
=P
trace
+P
Lstra
y
+ P
cstra
y
(6
)
Whe
r
e Le
is le
ngt
h
of PCB trace and
H is
he
ight
of PCB tra
ce and
W is
wi
dth
of PCB tra
ce,
r is
dielectric
constant
of ai
r, A is t
h
e a
r
ea
of
plates
an
d
d i
s
sepa
rat
i
o
n
be
t
w
een t
h
e
pl
at
es.
4.
EFFECT OF
PARASITI
C ELEMENT
IN
INDUCTOR
Th
e effect o
f
variatio
n
in
indu
ctor p
a
rasitic
resistan
ce on
ou
tpu
t
v
o
ltag
e
is sh
own
in
Figu
re
4
.
The
resul
t
s
are t
a
bu
l
a
t
e
d i
n
Tabl
e
2. T
h
e seri
es
1
rep
r
ese
n
t
s
t
h
e
out
put
vol
t
a
ge
vari
at
i
o
n f
o
r i
d
eal
i
nduct
o
r i
.
e
R
L
=
0
Ω
. The se
ri
es 2 repre
s
ent
s
t
h
e o
u
t
p
ut
vol
t
a
ge vari
at
i
o
n f
o
r i
n
duct
o
r wi
t
h
R
/
R
L
= 100 where R is the load
resistance. The
load resistance
v
a
lu
e is
equ
a
l to
R =
3
.
2
1
5
Ω
a
n
d we
get
R
L
=
0
.
03
215
Ω
. The series
3
represen
ts th
e o
u
t
p
u
t
vo
ltag
e
v
a
riatio
n
for in
du
ctor with
R/ R
L
= 80 an
d we get
R
L
=
0.
04
7
Ω
. T
h
e series
4
represen
ts th
e o
u
t
p
u
t
vo
ltag
e
v
a
riatio
n
for in
du
ctor with
R/ R
L
= 40 an
d we get
R
L
=
0.
09
3
Ω
. T
h
e series
5
rep
r
ese
n
t
s
t
h
e
out
put
v
o
l
t
a
ge
vari
at
i
o
n f
o
r i
n
duct
o
r
wi
t
h
R
/
R
L
= 8 a
n
d
we
get
R
L
=
0
.
46
7
Ω
.
Fig
u
re
4
.
Effect o
f
p
a
rasitic resistan
ce v
a
riatio
n of i
n
du
ctor
‐
12
‐
10
‐
8
‐
6
‐
4
‐
2
0
2
1
477
953
1429
1905
2381
2857
3333
3809
4285
4761
5237
5713
Output
voltage
in
volts
Time
samples
Series1
Series2
Series3
Series4
Series5
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Effect o
f
Pa
ra
sitic Elemen
ts
on
th
e Performan
ce
o
f
Bu
ck-Boo
s
t Con
verter f
o
r … (Sub
ra
ma
n
y
a
Bha
t
)
83
5
Fro
m
th
e
g
r
aph
it h
a
s
b
een ob
serv
ed
th
at as th
e
v
a
lu
e
of
parasitic resistan
ce
o
f
ind
u
c
t
o
r in
creases th
e vo
ltag
e
g
a
in
of b
u
c
k
-
bo
o
s
t
conv
erter
d
ecreases. Th
erefo
r
e, th
e v
a
l
u
e of
p
a
rasitic resistan
ce R
L
s
h
oul
d
be m
i
nim
u
m
as
p
o
s
sib
l
e.
Th
e id
eal efficien
cy
is un
ity and
the efficien
cy of
a bu
ck boo
st co
nv
erter
wh
en
p
a
rasitic elem
e
n
ts
are c
onsi
d
ere
d
i
s
gi
ve
n
by
1
1
1
1
1
(7
)
Tab
l
e
2
.
Effect of
p
a
rasitic resistan
ce v
a
riation
o
f
indu
cto
r
Parasitic
resistance
of inductor value
Output voltage
I
d
eal I
nductor
R
L =
0
-
12.
03V
R
L
=0.0321
5
Ω
-
11.
68V
R
L
=0.047
Ω
-
11.
29V
R
L
=0.093
Ω
-
10.
7V
R
L
=0.467
Ω
-7
.2
V
Whe
r
e Vs
n i
s
t
h
e O
N
st
at
e swi
t
c
h vol
t
a
ge d
r
op a
nd V
s
f O
F
F st
at
e swi
t
c
h
vol
t
a
ge
dr
o
p
, d
i
s
t
h
e dut
y
rat
i
o an
d
Vg is th
e source vo
ltag
e
α
=R
L
/R
β
= R
g
/R.
5.
EFFECT OF
PARASITIC
ELEMENT IN
CAPACIT
OR
Th
e p
a
rasitic resistan
ce in
a cap
acito
r
u
s
ed in
b
u
c
k
-
bo
ost co
nv
erter is varied
and
its effect on
th
e
p
e
rf
or
m
a
n
ce o
f
bu
ck-
boo
st co
nv
er
ter
is
seen
and
th
is is as sh
own
in
Figure 5
.
Th
e ou
tpu
t
v
o
ltag
e
v
a
lues are
tab
u
l
ated
i
n
Tab
l
e 3. It
h
a
s
b
e
en
fou
n
d
t
h
at th
e
p
a
ra
sitic resistan
ce in
cap
a
cito
r h
a
s n
o
sig
n
i
fican
ce
effect on
th
e ou
tpu
t
v
o
l
t
a
g
e
.
High
er th
e v
a
lu
e of
p
a
rasitic resistan
ce l
e
sser
will b
e
t
h
e ou
tpu
t
vo
ltage.
Fig
u
re
5
.
Effect o
f
p
a
rasitic
resistan
ce v
a
riatio
n of cap
acitor
Tabl
e 3.
Effect of
p
a
rasitic resistan
ce v
a
riation
o
f
cap
acitor
Parasitic R
e
sistance Value
Output voltage
R=0 -
12V
R=0.
001
Ω
-
11.
95V
R=0.
01
Ω
-
12.
13V
R=0.
05
Ω
-
11.
79V
‐
14
‐
12
‐
10
‐
8
‐
6
‐
4
‐
2
0
2
1
414
827
1240
1653
2066
2479
2892
3305
3718
4131
4544
4957
5370
5783
6196
6609
Output
voltage
Time
samples
Series1
Series2
Series3
Series4
Series5
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJECE Vol. 4, No. 6, D
ecem
ber 2014
:
831 – 836
83
6
6.
CO
NCL
USI
O
N
I
n
t
h
e pr
opo
sed
stud
y, th
e ef
f
ect of
p
a
r
a
si
tic
capacitances in a MOSFET su
ch
as
gate to
d
r
ai
n
capacitance, C
gd a
nd
gate to source cap
acit
a
nce Cgs are
not considere
d
.
It ha
s bee
n
also found that the effect
p
a
rasitic resistan
ce in
cap
acito
r on
ou
tpu
t
vo
ltag
e
is less a
s
co
m
p
ared
to
th
e effect o
f
parasitic resistan
ce o
f
in
du
ctor.
Also in
th
e
p
r
op
o
s
ed
stud
y th
e
p
a
rasitic e
ffects of PCB is exp
l
ain
e
d
.
While d
e
v
e
lop
i
ng
b
u
c
k
-
b
o
o
s
t
co
nv
erter on
a PCB th
ese effects sh
ou
ld
b
e
co
n
s
i
d
ered
. Th
e p
a
rasitic effect o
f
resistance an
d
capacitan
ces
fr
om
t
h
e sol
a
r
panel
al
s
o
s
h
o
u
l
d
be st
u
d
i
e
d
whi
c
h e
ffect
s t
h
e m
a
xim
u
m
powe
r
poi
nt
t
r
a
c
ki
n
g
.
The
p
r
o
pos
e
d
stu
d
y
h
a
s g
i
v
e
n
b
e
tter
insigh
t
in
to
p
a
rasitic
ele
m
en
ts
e
ffect
on
th
e performan
ce of
b
u
c
k-boo
st
conv
ert
e
r u
s
ed
in
PV system
s
.
Th
ese
p
a
rasitic ev
en
effects th
e
b
a
ttery
charg
i
n
g
u
s
ed in PV system
s. Du
e to
p
a
rasitic th
e
efficien
cy
d
e
g
r
ad
es and
th
erefo
r
e th
e effect
of
p
a
rasitic
should
b
e
m
i
n
i
mize
d
so
as to
im
p
r
o
v
e
th
e efficien
cy.
REFERE
NC
ES
[1]
Subram
an
y
a
Bh
at, Nag
a
raj
a
H N “Effect of filte
r el
em
ents on the perform
ance of bu
ck converter
”
IEEE
International Co
nference on Ad
vances in
Energy Conversion Technologies(
I
CAECT)
pp 169-173
, Manip
a
l, India
Jan. 2014
.
[2]
Mohan, N., T.M. Undeland
, and
W.P.
Robbins,
“Power Electron
i
cs: Convert
ers,
Applications, an
d Design”, John
Wiley
& Sons, I
n
c., New York,
1995.
[3]
Nur M
oham
m
a
d et.
a
l
., “
P
aras
it
ic
E
ffects on the
performance of
DC-DC SE
PIC i
n
Photovoltaic
Ma
xi
mum
Po
we
r
Point Tr
acking
Applica
tions’’,
I
n
ternational Jou
r
nal of Sm
art Gr
id and
Ren
e
wable En
ergy
, pp 11
3-121, 2013
.
[4]
V Ramanaray
a
n
“Lecture notes o
n
switched
mode power
conversi
on” IISC, Dec 2
007.
[5]
Robert W
Ericks
on, Drag
an Mak
s
imovic,
“Fundamentals of
power electronics”,
k
l
uwer academic
p
ublishers, 2000
.
[6]
AN11158, “Und
erstanding
Power MOSFET data
sheet
p
a
rameters NXP semiconduc
tors”, REV 4
Feb 2014
[7]
M. H. R
a
shid, “Power Electron
ics: Cir
c
uits, Dev
i
ces
and Applications”, 3rd
Ed
ition, pren
tice H
a
ll 2003.
[8]
www.
mathwork
s.
com
[9]
S. Maniktala, “Switching
Power
Supp
lies A to
Z,” Else- v
i
er
, Lon
don, 2003
[10]
Andrii Pazy
n
y
ch
, “A stud
y
of
the harmonic content of d
i
st
ribution
power grids with dist
ribute
d
PV
s
y
ste
m
s”
, M.
Sc
thesis,
Tampere
University
of
Technolog
y
,
2014.
BIOGRAP
HI
ES OF
AUTH
ORS
Subraman
y
a
Bh
at is currently
p
u
rsuing Ph.D,
under Visvesvaray
a
Tec
hno
logical University
,
Belgaum
,
Indi
a.
He is
currentl
y
working as
an As
s
o
ciate prof
es
s
o
r in the dep
a
rtm
e
nt of
Electronics & Communication Engineer
ing, Can
a
ra Engin
eer
ing College, Mangalore, India.
He has pr
esented more th
an
15 papers
in
N
a
tion
a
l
and In
ternational conf
erences
and
Journals. His research in
ter
e
sts include power
el
ectron
i
cs
, s
i
gna
l proce
ssing, control s
y
stems
and image processing. He has gi
ven more than 10
invited ta
lks in his research fi
eld. He was
awarded
with m
a
n
y
best
pap
e
r
a
w
ards in Na
tion
a
l
and In
terna
tio
nal
confer
ences
.
Dr. H.N. Nag
a
r
a
ja, presen
tl
y
w
o
rking as Dir
ector of Indus Ins
titut
e
of
Techn
o
log
y
and
Engineering, did
his graduation in Electrical
and
Electronics Engineering from Government
coll
ege of
Engin
eering
,
Dav
a
nag
e
re,
P
o
s
t
-gra
duation from Walchand college of
En
gineer
ing
,
Sangli, and Doctora
t
e from
Nation’s one of the prem
ier institute Indi
an Institute o
f
Techno
log
y
, Kharagpur-West B
e
ngal.
Dr. Nagaraja has
a v
a
st
experience of
2
7
y
ears
in
teaching
and 9
y
ears in
Research. He has
presented
40 p
a
pers in
the n
a
tion
a
l
and
intern
ation
a
l rep
u
ted journ
a
ls an
d conferen
ces.
He has also given 22 invited
talk
s at variou
s
Engineering
colleges. H
e
has
presented r
e
sear
ch
papers at Jap
a
n
Malasia and
Hongkong. His
field of in
terests
are Power supply
d
e
sign,
Power Electronics, R
e
ne
wable Energ
y
Sources,
M
i
croproces
s
o
rs
, Network
Anal
ys
is
, et
c.
Evaluation Warning : The document was created with Spire.PDF for Python.