Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
Vol
.
4
,
No
. 3,
J
une
2
0
1
4
,
pp
. 43
3~
44
0
I
S
SN
: 208
8-8
7
0
8
4
33
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Realizati
o
n of P
r
ogrammable B
P
S
K Dem
o
dulat
or-Bit
Synchronizer using Multirate Processing
Ansh
um
an Sh
arm
a
*, Abdul
Hafeez
Sye
d
, Midhu
n M, MR Ragh
avend
r
a
Spacecraf
t Ch
eckout Group,
ISRO Satellite C
e
ntr
e
Bangalore, 560
017, India
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Ja
n
2, 2014
Rev
i
sed
May
4, 201
4
Accepted
May 24, 2014
This pap
e
r pr
esents the design
and
implementation of programmable BPSK
demodulator an
d bit s
y
nchron
izer. Th
e
demodulator is based on
the Costas
loop design whereas the bit s
y
n
c
hronize
r is based on Gardner timing error
dete
ctor. T
h
e ad
vantag
e of this design
is that it of
fers program
m
a
bilit
y using
multi-rate processing and doe
s not rely
on comp
utation of f
ilter
coefficien
ts,
NCO angle inpu
t for each s
p
e
c
if
ic dat
a
rat
e
and
thus
avoids
com
putation
a
l
com
p
lexiti
es
.
T
h
e a
l
gorithm
an
d its
app
l
i
cat
io
n were v
e
rif
i
ed
on M
a
tl
ab-
S
i
m
u
link and was im
plem
ented
on ALTERA platform
. A 32 kHz BP
S
K
demodulator–bit sy
n
c
hronizer p
a
ir cate
ring for
data rates from
1 kbps to
8
kbps was implemented.
Keyword:
BPSK
Co
stas loop
FPGA
Gar
d
ner Ti
m
i
ng Det
ect
or
VH
DL
Copyright ©
201
4 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Ans
h
um
an Sha
r
m
a
,
Spacec
raft C
h
e
c
kout
Group, ISRO Satellite Centre
Ban
g
a
l
o
r
e
, 5600
17
, Ind
i
a
Em
a
il: an
sh
u
m
an
@isac.go
v.in
1.
INTRODUCTION
B
i
pol
ar
p
h
ase
shi
f
t
key
i
ng
(B
PSK
) m
odul
at
i
on i
s
wi
del
y
us
ed m
odul
at
i
o
n
schem
e
i
n
t
e
l
e
m
e
t
r
y
chai
n
of s
a
tellites due to its
powe
r efiiciency. T
h
e m
odula
tion schem
e
em
ployed
for telem
e
try transm
ission i
s
PC
M
/
PSK/
P
M
.
Wher
eas t
h
e
PM
m
odul
at
i
o
n i
s
do
ne at
S-
ban
d
/
C
-
b
an
d
f
r
eq
ue
nci
e
s, t
h
e
PS
K s
ubca
rri
e
r
s are
basi
cal
l
y
at
32 kHz a
nd
12
8 k
H
z.
W
i
t
h
t
h
e e
v
er i
n
c
r
easi
n
g
com
p
l
e
x i
n
t
e
rp
l
a
net
a
ry
m
i
ssi
on bei
n
g ex
pl
o
r
ed by
ISR
O
t
h
e t
e
l
e
m
e
t
r
y
dat
a
rates have va
ri
ed
from
100 b
p
s
t
o
8 kb
ps o
n
t
h
e subc
ar
ri
ers
.
Thi
s
wo
r
k
di
scusse
s
abo
u
t
an i
m
plem
ent
a
t
i
on schem
e
of pro
g
r
am
m
a
bl
e B
P
SK
d
e
m
o
du
lato
r-b
it syn
c
hron
izer p
a
ir in
d
i
g
ital
dom
ai
n
w
h
i
c
h can be dy
nam
i
cal
l
y
confi
g
u
r
e
d
fo
r vari
a
b
l
e
d
a
t
a
rat
e
s.
The B
P
S
K
de
m
odul
at
or i
s
C
o
st
as l
o
op
bas
e
d de
si
g
n
. T
h
e
bl
oc
k
di
agr
a
m
of C
o
st
as l
o
o
p
i
s
gi
ven
i
n
Fig
u
re 1. Th
ere are ex
isting
so
lu
tion
s
fo
r imp
l
em
en
tatio
n
o
f
BPSK
m
o
d
e
m [
1
],
[
2
],
[3
], [
4
].
Th
e Co
stas lo
op
extracts the de
m
odulated signal at the “in-pha
se” bra
n
c
h
of the loop. T
h
e Num
e
rically controlled Oscillator
(NC
O
) w
h
i
c
h can be
i
m
pl
em
ent
e
d usi
n
g
t
h
e
Co
-o
rd
in
ate
R
ot
at
i
o
n
Di
g
ital
C
om
put
er (
C
OR
DIC
)
al
g
o
ri
t
h
m
)
[5]
l
o
c
k
s
o
n
t
o
i
n
c
o
m
i
ng si
gnal
a
n
d si
m
u
l
t
a
neou
sl
y
ge
n
e
rat
e
s t
h
e
dem
o
d
u
l
a
t
e
d
o
u
t
p
u
t
. The
o
u
t
p
ut
of
t
h
e
dem
odul
at
o
r
i
s
gi
v
e
n
t
o
bi
t
s
y
nch
r
o
n
i
zer
f
o
r cl
oc
k
rec
ove
ry
,
dat
a
e
x
t
r
ac
t
i
on.
The
bi
t
s
y
nch
r
o
n
i
zer
ca
n
be
i
m
p
l
e
m
en
ted
u
s
in
g
th
e Gard
ner ti
m
i
n
g
-
error d
e
tecto
r
[6
]. To
in
tro
d
u
ce prog
ramm
ab
ilit
y in
th
is d
e
sig
n
th
e
arm
filters, lo
o
p
filters and
NCOs h
a
v
e
t
o
b
e
t
u
n
e
d
as
p
e
r t
h
e
d
a
ta rates. Th
e tun
a
b
l
e filters
h
a
ve b
e
en
discussed in [7]. All this retuni
ng calls for a co
m
puter interface where
new filter coe
f
ficients, NCO
angle
i
n
p
u
t
can
be
re
com
put
ed a
n
d
passe
d
on
t
o
t
h
e FP
GA
desi
gn
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
4, No
. 3,
J
u
ne 2
0
1
4
:
43
3 – 4
4
0
43
4
Fi
gu
re
1.
B
a
si
c C
o
st
as L
o
op
In this work,
we use m
u
ltirate sa
m
p
ling [8] to configure
the dem
odul
ator-bit synchronizer pair for
an
y d
a
ta rate
fro
m
1
kbp
s to
8 kb
ps.
Th
is app
r
o
a
ch
is
b
a
sed
o
n
th
e con
c
ep
t of ach
i
ev
i
ng reco
nfigu
r
ab
ility b
y
vary
i
n
g t
h
e sa
m
p
li
ng
fre
qu
en
cy
rat
h
er
t
h
a
n
r
ecom
puting coefficients
fo
r r
econ
f
ig
uri
n
g
.
In t
h
e n
e
xt
sect
i
on
we
di
scuss
t
h
e basi
c c
o
nce
p
t
an
d
desi
g
n
o
f
t
h
e
dem
odul
a
t
or-
b
i
t
sy
nc
hr
o
n
i
zer
pai
r
.
Su
bseq
ue
nt
l
y
we prese
n
t
t
h
e
im
pl
em
ent
a
t
i
o
n of
t
h
e desi
g
n
o
n
har
d
ware.
2.
R
E
SEARC
H M
ETHOD
2.1.
T
h
e
Concept
As explaine
d earlier the foc
u
s of this work is
to achie
ve program
m
ab
ility without
repeatitive
com
put
at
i
onal
bu
r
d
en
s w
h
i
l
e
desi
g
n
i
n
g a
pr
o
g
ram
m
abl
e
B
PSK
dem
o
d
u
l
a
t
o
r
-
bi
t
sy
nc
hr
o
n
i
zer. T
h
e
wh
ol
e
conce
p
t
i
s
bas
e
d o
n
t
h
e
fact
t
h
at
i
n
di
gi
t
a
l
si
gnal
p
r
oce
ssi
ng
(D
SP
) a
l
l
t
h
e com
put
at
i
ons are
bas
e
d o
n
sam
p
lin
g
freq
u
en
cy. A
filter
work
i
n
g
at sam
p
l
i
n
g
freq
u
e
ncy f1
with
p
a
ssb
a
nd
freq
u
e
n
c
y o
f
f
pass
a
nd st
op ba
nd
fre
que
ncy
of
f
stop
can
b
e
m
a
d
e
to
work as
filter with a
d
i
ffere
n
t
p
a
ssb
a
n
d
and stop
b
a
n
d
frequ
e
n
c
y
ju
st
by
changing t
h
e s
a
m
p
ling
fre
que
n
cy to
f2
, si
n
c
e bo
th
f
pass
and
f
stop
are norm
alized
wrt
sam
p
l
i
n
g
f
r
eq
ue
ncy
.
As an
ex
am
p
l
e refer to
th
e table 1
,
a 16
tap
FIR filter is d
e
si
g
n
e
d
u
s
ing
Kai
s
er wi
n
dow fo
r 6
-
d
B
p
a
ss
ban
d
f
r
e
que
nc
y
of 1
0
kHz at
a sam
p
l
i
ng rat
e
of
10
0
kHz
.
T
h
e rat
i
o
of
pass
ban
d
t
o
sam
p
l
i
ng f
r
e
que
ncy
i
s
0.
1
.
Next
t
h
e
sam
e
coef
fi
ci
ent
s
ar
e sam
p
l
e
d at
a rat
e
of
8
0
k
H
z and t
h
ey
p
r
o
v
i
d
e
6-
dB
pa
ss
ban
d
fre
que
nc
y
of
8
kHz a
g
ai
n t
h
e
sam
e
rati
o of
0.
1 i
s
m
a
i
n
t
a
ined
. T
h
i
s
co
nc
ept
f
o
rm
s t
h
e basi
s o
f
t
h
i
s
w
o
r
k
a
nd i
t
has
been
fu
rt
he
r di
scuss
e
d.
Tab
l
e 1
.
Filter ch
aracteristics
wrt
sam
p
lin
g
frequ
e
n
c
y
Sim
i
l
a
rl
y t
h
e
NC
O can
be m
odi
fi
ed t
o
gi
ve o
u
t
p
ut
at
di
ffere
nt
fre
q
u
e
n
cy
by
sim
p
l
e
vari
at
i
on o
f
sam
p
lin
g
frequen
c
y. Thu
s
, chan
g
i
n
g
the sam
p
l
i
n
g
frequ
e
n
c
y av
o
i
d
s
re-co
m
p
u
t
atio
n
of filter co
efficien
ts and
NCO ang
l
e inpu
t fo
r v
a
rying
d
a
ta rates.
Fig
u
r
e
2
d
e
p
i
cts g
e
ner
a
l ph
ase lo
ck
loop
(PLL)
ar
ch
itectu
r
e in
d
i
g
ital do
main
. In
th
e
PLL if
th
e loop
filter ch
aracteristics are to
be ch
an
g
e
d
it can
be don
e
b
y
two ways- eith
er b
y
reco
m
p
u
t
atio
n
o
f
filter
coefficients
or as stated
above,
by
c
h
an
gi
n
g
t
h
e
sam
p
l
i
n
g
fre
q
u
ency
.
B
u
t
chan
gi
n
g
t
h
e
sam
p
l
i
ng f
r
eq
uency
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Rea
liza
tion
o
f
Prog
rammab
le
BPS
K
Demo
du
la
tor-Bit
S
y
n
c
h
r
on
izer u
s
i
n
g Mu
ltira
t
e
…
(An
s
human
Sh
arma
)
43
5
will ch
ang
e
the free
runn
ing
freq
u
e
n
c
y of t
h
e NC
O an
d
ch
ang
i
ng
co
effi
cien
ts requ
ire
re-co
m
p
u
t
atio
n. So
a
n
e
w arch
itecture fo
r PLL was th
ou
gh
t as dep
i
cted
in
fi
g
u
re 3
.
Th
e fi
rst NCO-m
u
ltip
lie
r p
a
ir
d
o
wn
con
v
e
rt
s
th
e inp
u
t
sign
al to
clo
s
e to zero frequ
e
n
c
y an
d th
e
PL
L
the
r
eafter corrects
for t
h
e
phase and
freque
ncy errors
.
Th
e loop
filter ch
aracteristics can
b
e
easily m
o
d
i
fied
b
y
ch
ang
i
ng
t
h
e sam
p
l
i
n
g
freq
u
e
n
c
y. Th
is ch
ang
e
in
sam
p
l
i
ng fre
q
u
e
ncy
does
not
chan
ge
t
h
e
o
u
t
put
f
r
eq
ue
ncy
of
t
h
e
seco
n
d
NC
O
as i
t
i
s
c
o
n
f
i
g
ure
d
t
o
w
o
r
k
a
t
zero
fre
q
u
ency
. Thi
s
w
o
rk
d
e
m
onst
r
at
es t
h
i
s
conce
p
t
o
n
FPG
A
har
d
wa
re w
h
i
c
h i
s
di
scusse
d i
n
s
u
b
s
eque
nt
sect
i
on.
Figure
2. Phas
e lock loop
Fi
gu
re
3.
M
o
di
fi
ed
Phase
l
o
c
k
l
o
o
p
2.2. I
m
plementation
2.
2.
1. Cl
oc
k
G
e
nera
ti
on
To f
o
rm
ul
at
e the co
nce
p
t
we
di
d t
h
e
fu
nct
i
o
nal
sim
u
l
a
t
i
on on M
A
TL
AB
-
S
im
ul
i
nk an
d i
m
pl
em
ent
e
d
t
h
e p
r
o
g
ram
m
abl
e
B
PSK
dem
o
d
u
l
a
t
o
r-
bi
t
sy
nch
r
oni
zer
pai
r
on a
n
Al
t
e
ra
FPG
A. T
h
e
ba
si
c bl
oc
k di
a
g
r
a
m
i
s
prese
n
t
e
d
i
n
Fi
gu
res
5,
8
an
d
9.
The
desi
gn
i
s
base
d
o
n
P
L
L.
R
e
fer t
o
t
a
bl
e 2;
t
h
e i
n
put
sa
m
p
li
ng f
r
eq
ue
ncy
i
s
22
4
kHz
.
Fo
r t
h
e
dat
a
rat
e
s fr
om
8 k
bps t
o
1
k
b
p
s
t
h
e sam
p
l
i
ng fre
que
ncy
i
s
scal
ed d
o
w
n
f
r
o
m
112 k
H
z t
o
1
4
k
H
z. T
h
e cor
r
esp
o
ndi
n
g
i
n
t
e
r
pol
at
i
o
n
and
decim
a
tion val
u
es a
r
e indicated.
All alon
g
,
th
e ratio of samp
lin
g frequ
e
n
c
y to
d
a
ta rate i
s
m
a
in
tain
ed
as 14
t
o
pr
o
v
i
d
e s
u
f
f
i
c
i
e
nt
sam
p
l
e
s fo
r bi
t
sy
nc
hr
o
n
i
zer t
o
l
o
ck
. E
v
en t
h
ou
g
h
bi
t
sy
nch
r
o
n
i
zer
i
s
base
d o
n
G
a
rd
ner
t
i
m
i
ng det
ect
o
r
whi
c
h re
qui
r
e
s onl
y
t
w
o s
a
m
p
l
e
s per bi
t
we are t
a
ki
n
g
14 sam
p
l
e
s per bi
t
as we are n
o
t
ad
ju
sting
our sa
m
p
lin
g
in
stants b
u
t
rath
er selectin
g
th
e
samp
le p
a
ir wh
ich
g
i
v
e
s th
e
b
e
st Sig
n
a
l to
No
ise ratio.
So
, su
fficien
t
n
u
m
b
e
r of sam
p
les
is req
u
i
red
for g
e
ttin
g
th
e b
e
st strobin
g
in
stan
t. For 8
kbp
s d
a
ta
rate th
e
sam
p
lin
g
r
a
te af
ter
in
ter
p
o
l
atio
n
is 1
.
792 MH
z. Th
e
max
i
m
u
m
c
l
o
c
k
f
r
e
qu
en
cy
co
rr
esp
ond
ing to
th
i
s
sam
p
lin
g
frequen
c
y is 32
.25
6
MHz. Th
is clock
freq
u
e
n
c
y is
requ
ired
for t
h
e an
ti-aliasin
g
filter in
b
e
tween
th
e
in
terpo
l
ator and
the
d
ecim
a
to
r,
refer t
o
figu
re 5
.
Th
e
f
ilter
is a 64 tap
,
Kaiser wi
nd
ow
FIR filter. It
h
a
s b
e
en
im
pl
em
ent
e
d wi
t
h
cert
a
i
n
a
m
ount
of pa
ral
l
e
l
i
s
m
so cl
ock
freq
u
e
n
cy
of
16 t
i
m
es as com
p
ared t
o
t
h
e sam
p
l
i
n
g
f
r
e
q
u
e
n
c
y is req
u
i
r
e
d.
W
e
h
a
v
e
k
e
p
t
two
cl
o
c
k cycles
as
b
u
f
f
e
r
,
(3
2.256/1
.
792
=18)
. This clo
c
k
is
g
e
ner
a
ted
b
y
an
onb
o
a
rd
Crystal o
s
cillat
o
r. All th
e clo
c
k
s
requ
ired
for p
r
o
g
ramm
ab
il
ity are g
e
n
e
rat
e
d
b
y
onb
o
a
rd
PLL
o
n
th
e FPGA, rou
t
ed to
m
u
ltip
lex
e
r t
o
wh
i
c
h
selection
is p
r
ov
id
ed
throu
g
h
i
n
pu
t/ou
t
pu
t (I/O) lin
es
o
f
t
h
e
FPGA, as ind
i
cated
in
Figu
re
4
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
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08
IJEC
E V
o
l
.
4, No
. 3,
J
u
ne 2
0
1
4
:
43
3 – 4
4
0
43
6
Tab
l
e
2
.
Data
rates and
th
e clo
c
k requ
irem
e
n
t
Fi
gu
re 4.
C
l
oc
k gene
rat
i
o
n o
n
F
P
G
A
2.
2.
2. B
u
i
l
d
i
n
g bl
ocks
R
e
fer t
o
t
h
e fi
g
u
re
5, t
h
e i
n
c
o
m
i
ng 32
kHz
B
PSK m
odul
at
ed si
g
n
al
i
n
t
h
e form
of
()
ICos
x
(I is th
e
m
odulating
NRZ-M bi
pola
r
data) is
pass
ed through
a
n
Anti-aliasing filter(AAF)
whic
h is a
6
th
or
de
r
Butterw
ort
h
fil
t
er p
r
o
v
idi
n
g
n
ecessary
re
ject
ion at
(fs
)s
ampling freque
nc
y/2. The an
al
og
sign
al is conv
er
ted
t
o
di
gi
t
a
l
si
gna
l
wi
t
h
sam
p
l
i
ng f
r
e
que
ncy
(
f
s
)
of
2
2
4
kHz
u
s
ing
a
10
-b
it p
i
p
e
lin
ed
(ADC) an
al
o
g
to
dig
ital
co
nv
er
ter
.
Th
i
s
sign
al is t
h
en
b
r
ou
gh
t
dow
n to clo
s
e to
“
0
” i
n
term
ediate f
r
eq
ue
nc
y
(IF
) i
n
t
h
e
fo
rm
of
()
IC
os
x
and
()
IS
i
n
x
(
x
is th
e in
stan
tan
e
o
u
s
phase an
d
frequ
e
n
cy error
bet
w
een t
h
e between the
i
n
com
i
ng si
gn
al
and t
h
e NC
O) by
t
h
e f
r
o
n
t
end I
Q
det
ect
or i
m
pl
em
ent
e
d i
n
di
gi
t
a
l
dom
ai
n usi
n
g
NC
O
(ru
n
n
i
ng
at sam
p
l
i
n
g
freq
u
e
n
c
y of 224
k
H
z) and
m
u
ltip
li
ers. Th
e
wh
o
l
e id
ea of seg
r
egatin
g
th
e C
o
stas loop
has
bee
n
e
xpl
a
i
ned ea
rl
i
e
r.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Rea
liza
tion
o
f
Prog
rammab
le
BPS
K
Demo
du
la
tor-Bit
S
y
n
c
h
r
on
izer u
s
i
n
g Mu
ltira
t
e
…
(An
s
human
Sh
arma
)
43
7
Th
e d
e
riv
e
d
I an
d
Q o
u
t
p
u
t
s
are
t
h
en p
a
ssed
thro
ugh
a b
a
nk
of
in
terpo
l
ato
r
, filter
an
d
d
e
cim
a
to
r
wh
ich
allo
w
sa
m
p
lin
g
rate co
nv
ersion
b
y
no
n-in
teg
e
r
facto
r
. Th
e an
ti-aliasin
g
FIR
filter presen
t in
b
e
tween
th
e in
terpo
l
ator an
d th
e
d
eci
mato
r is as exp
l
ain
e
d earlie
r a
Kaiser
wi
n
d
o
w
, 6
4
tap
filter d
e
sign
ed
to p
r
ov
id
e
su
fficien
t
attenu
atio
n
at stop
b
a
nd
freq
u
e
n
c
y o
f
fs/
2
.
Figures 6, 7
sh
ow
th
e am
p
l
i
t
u
d
e
respon
se of the filter
si
m
u
lated
in
M
A
TLAB for sam
p
l
i
n
g
frequ
en
cies
o
f
112
,
98
k
H
z resp
ecti
v
ely. It
u
s
es same filter co
effi
cien
ts
but
gi
ve
s t
h
e
d
e
si
red
pe
rf
orm
a
nce
wi
t
h
c
h
a
n
gi
n
g
sam
p
l
i
ng
fre
que
nci
e
s.
Fi
gu
re 5.
Dem
o
d
u
l
a
t
o
r
f
r
ont
end
Fig
u
re 6
.
Kaiser
filter repon
se for
sam
p
lin
g
freq
u
e
n
c
y o
f
112
k
H
z
Fig
u
re 7
.
Kaiser
filter repon
se for
sam
p
lin
g
freq
u
e
n
c
y o
f
98
k
H
z
R
e
fer t
o
t
h
e
fi
gu
re
8, t
h
e
I a
n
d
Q
o
u
t
p
ut
s
aft
e
r t
h
e
deci
m
a
t
o
r are
gi
ve
n t
o
t
h
e
PLL
bl
oc
k
whi
c
h
cor
r
ect
s fo
r an
y
resi
dual
p
h
as
e and f
r
eq
ue
nc
y
offset
bet
w
e
e
n t
h
e i
n
com
i
ng si
gnal
a
nd t
h
e fro
nt
en
d N
C
O i
n
th
e IQ d
e
tect
o
r
. Th
e NC
O in
th
is b
l
o
c
k
is con
f
i
g
ured
to
work at “0” frequency. Th
e in-phase arm
of the PLL
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
4, No
. 3,
J
u
ne 2
0
1
4
:
43
3 – 4
4
0
43
8
b
l
o
c
k
g
i
v
e
s the d
e
m
o
du
lated ou
tpu
t
. Th
a
arm
filters ar
e
1
6
tap
,
Kaiser windo
w FIR
filters wh
ich also
g
e
t
recon
f
i
g
ured
with
the ch
ang
e
in sam
p
lin
g
freq
u
e
n
c
y.
Th
e
ou
tpu
t
is
rou
t
ed to
an 8 b
it
Dig
ital to An
alog
C
o
n
v
ert
e
r (
D
AC
)
fo
r m
oni
t
o
ri
n
g
p
u
r
p
o
s
e
an
d al
so
pa
r
a
l
l
e
l
y
t
o
t
h
e bi
t
sy
nc
hr
oni
z
e
r f
o
r
cl
oc
k a
n
d
dat
a
recovery.
Fi
gu
re 9 s
h
ow
s t
h
e bl
oc
k
di
agram
of t
h
e
bi
t
sy
nch
r
o
n
i
z
er. T
h
e bi
t
sy
nch
r
oni
zer
d
o
e
s t
h
e cl
oc
k
reco
very
a
n
d
a
l
so rec
ove
rs t
h
e dat
a
. G
a
r
dne
r al
g
o
ri
t
h
m
is
u
s
ed
fo
r Tim
i
n
g
Erro
r
Detectio
n. Th
is algo
ri
th
m
is
sui
t
a
bl
e f
o
r
b
o
t
h t
r
acki
ng a
n
d acq
ui
si
t
i
on
m
odes of
ope
r
a
t
i
on.
Al
so
, t
h
e cl
ock
reco
ve
ry
doe
s n
o
t
de
pen
d
on
carrier phase
.
In this algorit
hm
,
only two sam
p
les
of
the signal are re
quired for
each dat
a
sym
bol. And also,
one
of t
h
e t
w
o
sam
p
l
e
s i
s
used f
o
r sy
m
bol
st
ro
bi
n
g
(i
.e.
,
t
h
e sam
p
l
e
on w
h
i
c
h t
h
e sy
m
bol
deci
si
o
n
i
s
m
a
de).
The t
i
m
i
ng er
r
o
r
det
ect
or
o
p
e
r
at
es u
p
o
n
sam
p
l
e
s an
d
gene
r
a
t
e
s one e
r
r
o
r
sam
p
l
e
for eac
h sy
m
bol
. Thi
s
err
o
r
sequ
en
ce is smo
o
t
h
e
n
e
d
b
y
a lo
op
filter and
th
en
u
s
ed
t
o
adj
u
st a ti
min
g
error correct
o
r
, wh
ich
in
th
is case is
an
NC
O. The NCO is con
f
i
g
u
r
ed
to
run
at a frequ
en
cy wh
ich
is d
oub
le th
e d
i
screte d
a
ta rates as p
e
r th
e tab
l
e
2.
W
i
t
h
cha
n
ge
in the sam
p
ling freque
ncy, the NCO
out
put
fre
que
ncy cha
nge
s accordi
n
g to the sam
p
ling rate
an
d
t
h
e PLL lock
s for all th
e
d
a
ta rates
b
e
tween
1 kbp
s to
8 k
b
p
s
as th
e loo
p
filter is d
e
si
g
n
e
d
to ach
ieve wid
e
acq
u
i
sition
b
a
nd
wi
d
t
h
[9
]. Fo
r d
e
tails on
Gard
n
e
r tim
in
g
d
e
t
ecto
r
, refer t
o
[6
].
Al
l
t
h
e l
o
o
p
fi
l
t
e
rs bot
h i
n
d
e
m
odul
at
o
r
an
d bi
t
sy
nch
r
o
n
i
zer are fi
rst
o
r
der l
ead
-l
ag fi
l
t
ers deri
ved
from
their anal
og coun
ter-pa
rt
usi
n
g
bilinea
r trans
f
orm
a
tion m
e
thod.
Fi
gu
re 8.
The
PLL bl
oc
k
Fi
gu
re
9.
B
i
t
sy
nch
r
o
n
i
zer
bl
ock
di
a
g
ram
3.
R
E
SU
LTS AN
D ANA
LY
SIS
The dem
odula
t
or-bit
sync
hronizer was
im
plem
ente
d on F
P
GA and the
functionality was veri
fied.
Fi
gu
re 1
0
sh
o
w
s t
h
e o
u
t
p
ut
of t
h
e B
P
S
K
d
e
m
odul
at
o
r
f
o
r
8 kb
ps dat
a
ra
t
e
, ro
ut
ed t
h
r
o
ug
h D
A
C
.
T
h
e
out
p
u
t
is seen
witho
u
t an
an
ti-im
ag
in
g
filte
r, so
t
h
e sam
p
lin
g
step
s
o
f
11
2 kHz are seen
.
To
v
e
ri
fy th
e
en
ti
re
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Rea
liza
tion
o
f
Prog
rammab
le
BPS
K
Demo
du
la
tor-Bit
S
y
n
c
h
r
on
izer u
s
i
n
g Mu
ltira
t
e
…
(An
s
human
Sh
arma
)
43
9
fun
c
tion
a
lity a
si
m
u
lated
m
o
d
u
l
ated
d
a
ta with
k
n
o
w
n
Frame syn
c
h
r
on
izatio
n
cod
e
was g
i
v
e
n
as an
inp
u
t
t
o
t
h
e sy
st
em
and t
h
e bi
t
sy
nc dat
a
and cl
ock
o
u
t
p
ut
was gi
ve
n t
o
an ext
e
rna
l
fram
e
sy
nchr
oni
ze
r an
d co
n
t
i
nou
s
fram
e
sy
nc l
o
c
k
was
veri
fi
ed
fo
r al
l
dat
a
rat
e
s fr
om
1
kb
ps t
o
8
kb
ps.
Fi
gu
re
1
0
. T
h
e
B
PSK
dem
o
d
u
l
a
t
o
r
-
Out
put
Ey
e di
ag
ram
3.
1.
Pr
ogr
am
mabi
l
t
y for
D
a
t
a
Ra
tes bel
o
w
1
k
bps
Due t
o
res
o
urc
e
const
r
aints on the FP
GA, program
m
ability for
data rates
from
8 kbps
up to 100 bps
coul
d
n
o
t
be veri
fi
e
d
on h
a
rd
ware
.
B
u
t
i
ndi
vi
dual
l
y
s
e
l
ect
i
on f
o
r
1
00
b
p
s
dat
a
r
a
t
e
usi
n
g t
h
e
sam
e
archi
t
ect
u
r
e w
a
s veri
fi
e
d
o
n
t
h
e FP
GA
. Th
e cl
ock re
q
u
i
r
e
m
ent
for
10
0
b
p
s dat
a
rat
e
i
s
sho
w
n i
n
t
a
bl
e
3. A
s
we see t
h
at
t
h
e
rat
i
o
f
o
r i
n
t
e
r
p
ol
at
i
on t
o
deci
m
a
t
i
on i
s
1/
1
6
0
, a
d
di
t
i
onal
d
ecim
a
t
i
on bl
oc
k
of
1
60
was
r
e
qui
red
for th
is
d
a
ta rat
e
. Also
, a
d
i
fferen
t an
ti-aliasin
g
filter h
a
d
to b
e
u
s
ed
with
sto
p
b
a
nd
frequen
c
y at (fs1)/(2
)
and
pass
ba
nd
f
r
eq
uency
at
t
h
e
da
t
a
rat
e
.
Tabl
e 3.
C
l
oc
k req
u
i
r
em
ent
fo
r 10
0 b
p
s dat
a
rat
e
4.
CO
NCL
USI
O
N
A det
a
i
l
e
d
des
i
gn a
nd
de
vel
opm
ent
of
pr
o
g
ram
m
abl
e
B
P
SK
dem
odul
at
or
- bi
t
sy
nc
hr
oni
ze
r us
i
n
g
m
u
l
tirate p
r
ocessin
g
h
a
s b
e
en d
e
m
o
n
s
trated
as a p
a
rt
o
f
t
h
is wo
rk
. Th
is
wo
rk
will b
e
scaled
fo
r o
t
h
e
r carrier
fre
que
nci
e
s a
n
d
ot
her
dat
a
r
a
t
e
s i
n
d
u
e c
o
urse
. T
h
e
wh
o
l
e foc
u
s
of
t
h
i
s
w
o
r
k
i
s
pr
o
g
ram
m
abi
l
i
t
y
but
t
h
e
h
i
gh
er clo
c
k
req
u
i
rem
e
n
t
o
f
3
2
.
2
5
6
MHz can
still b
e
fu
rth
e
r o
p
tim
ized
to
a lo
wer clo
c
k
if th
e FIR filter in
the
dem
odul
at
o
r
f
r
ont
e
n
d
i
s
im
pl
em
ent
e
d wi
t
h
f
u
rt
her
paral
l
e
l
i
s
m
and al
so t
h
e bi
t
sy
nch
r
oni
zer i
s
m
a
de t
o
wo
rk
with
ex
actly two sam
p
les p
e
r
b
it.
ACKNOWLE
DGE
M
ENTS
We
would
like
to
express
our
si
n
cere
g
r
atitude
to M
r
.
K.
V.
G
ovi
nda
,
Dep
u
t
y
Directo
r
IC
A, M
r
.
K.B
.
A.R
.
Sarm
a, G
r
ou
p
Di
re
ct
or
SC
G,
M
r
.
R
a
j
u
Sa
gi
,
S
c
i
-
En
g “
G
” a
n
d M
r
s
U.
Vasa
nt
ha
K
u
m
a
ri
, Head
SRCD/SCG,
for all the e
n
coura
g
em
ent
and
t
echni
cal
g
u
i
d
ance d
u
r
i
n
g t
h
e cou
r
se
of
des
i
gn a
nd
de
vel
o
pm
ent
.
We wo
ul
d
l
i
k
e t
o
s
p
eci
fi
cal
l
y
t
h
an
k
M
r
s. Vas
uki
E. fo
r preci
si
on
fa
bri
cat
i
o
n
e
xpe
rt
i
s
e.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
IJEC
E V
o
l
.
4, No
. 3,
J
u
ne 2
0
1
4
:
43
3 – 4
4
0
44
0
REFERE
NC
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,
Goran Stim
ac
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plem
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i
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y
Environments,”
MIPRO 2011
,
M
a
y
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[2]
Yuan,
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[4]
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,
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Vol. COM-25, No. 2
,
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19
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[5]
Ray
Andraka
, “
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RDIC algorithms for FPGA based computers
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Flo
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l
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A
S
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e d
e
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ph
as
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ita
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i
lters
wi
th var
i
ab
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c
t
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(
N
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Jose
Fra
n
c
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e
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M
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R. Ragh
aven
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y
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BIOGRAP
HI
ES OF
AUTH
ORS
Anshuman Sharma is a Scie
ntist
at ISRO Sate
llite Centr
e
. H
e
jo
in
ed ISRO
in
the
year 2005
. He did
his Masters fro
m
Indian Institu
t
e
of
Techno
log
y
-Madras in Com
m
unication
S
y
t
e
m
s
. His research
inter
e
st in
clud
es
Digital
signa
l pr
ocessing, RF
co
mmunication.
Abdul Hafeez S
y
ed
is a Scientist at ISRO Sa
tellite Centr
e
. He jo
ined ISRO in the
y
ear 2011
. He
did his Masters from
National In
stitute of
Tech
n
o
lo
g
y
-C
ali
c
ut in
the
y
e
ar 2007 i
n
Digital s
y
stem
s
and Com
m
unication
.
His rese
arch in
ter
e
st in
cludes Communication s
y
s
t
em. Digital sign
al
processing, D
e
sign and D
e
velop
m
ent of
d
e
modulators
and b
it s
ynchronizers.
Midhun M is a Scientist
at ISR
O
Sa
tellite C
e
ntre. He
joined IS
RO
in the
y
e
ar
2008. His resear
ch
inter
e
st includ
es Comm
unicatio
n sy
st
em
, Digi
tal signal pro
ces
sing and baseband data cod
i
ng-
decoding
.
M R Raghavend
ra
is
a Scientist at ISRO Satellite Centr
e
. He jo
ined ISRO in th
e
y
ear 1992
. His
res
earch in
ter
e
s
t
includes
RF
Com
m
unication s
y
ste
m
s,
Digita
l signa
l
processing, Design and
development
of analog and
digital
demodulators. Presently
,
h
e
is
the head of Ch
eckout B
a
seban
d
and RF Division
(CBRD) at
ISRO Satellite C
e
ntr
e
.
Evaluation Warning : The document was created with Spire.PDF for Python.