Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
Vol
.
5
,
No
. 5, Oct
o
ber
2
0
1
5
,
pp
. 97
5~
98
3
I
S
SN
: 208
8-8
7
0
8
9
75
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
Multilevel MPSoC Performance
Evaluation, new ISSPT model
A. Alali, I. As
say
a
d
,
M.
Sa
d
i
k
Department o
f
Electrical Engin
e
eri
ng,
RTSE
Team,
HASSA
N II University
,
Ecol
e Nat
i
ona
le
S
upérieure
d’E
l
e
c
tri
c
it
é
et d
e
M
é
caniqu
e
,
Cas
a
bl
a
n
ca,
M
o
rocco
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Apr 8, 2015
Rev
i
sed
Jun
26,
201
5
Accepte
d
J
u
l 10, 2015
To dep
l
o
y
th
e
enorm
ous hardware resour
ces
avai
labl
e in
Multi-Proc
essor
S
y
s
t
em
s
-
on-Chip (M
P
S
o
C) efficientl
y,
rap
i
dl
y
a
nd accur
a
t
e
l
y
,
Des
i
gn S
p
ac
e
Exploration (D
SE) methods are need
ed
to
assess the differ
e
nt design
alt
e
rnat
ives
. In t
h
is
paper, we pr
es
ent a pl
atform
that m
a
kes
fas
t
s
i
m
u
lation
and performance evalu
a
tion of M
PSoC possi
ble early
in th
e desig
n
flow, thus
reducing
the
ti
m
e
-to-m
a
rket.
I
n
this fr
am
ework and wi
thin
th
e Tr
ansac
tion
Level Modeling
(TLM) approach
, we pres
ent a n
e
w definition of Instruction
Set simulation
(ISS) level b
y
intr
oducing
two complementar
y modeling
suble
v
e
l
s ISST
a
nd ISSPT
.
T
h
is late
r,
tha
t
we
illustra
t
e
a
n
a
r
bite
r mode
ling
approach th
at allows a high perfo
rmance MPSo
C communicatio
n. A round-
robin m
e
thod is chosen because
it is sim
p
le, m
i
nim
i
zes the com
m
unicatio
n
latency
and has an accepted speed-up. Tw
o applications are tested and used
to valida
t
e our platform
: Gam
e
of lif
e and J
P
EG
Encoder
.
The pe
rform
ance
of the proposed
approach
has b
e
en an
aly
z
ed
in
our platform MPSoC based
on multi-Micro
B
laze. Simulatio
n results
show
with ISSPT subl
evels gives a
high simulation
speedup f
actor
of up to
32 with a n
e
glig
ible
performance
estim
ation
error
m
a
rgin.
Keyword:
CABA
Est
i
m
a
t
i
on of
per
f
o
r
m
a
nce
ISS
MPSoC
Mu
ltip
ro
cessor syste
m
s
Priority m
a
n
a
ge
m
e
n
t
System
C
TLM
Copyright ©
201
5 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
A. AL
ALI
,
Depa
rtem
ent of Elect
ri
cal
E
n
gi
nee
r
i
n
g,
HASSAN II
Un
iv
ersity, Eco
l
e Nation
a
le Su
p
é
rieu
re
d’Electricité et d
e
Mécan
iqu
e
.
R
out
e
D'
El
Jad
i
da, C
a
sa
bl
anc
a
, M
o
rocc
o.
Em
a
il: h
a
k
i
m
.
alali@g
m
a
il.co
m
1.
INTRODUCTION
Th
e literature shows th
at
m
u
ch
o
f
th
e
d
e
sign
tim
e is
sp
en
t in th
e
p
e
rform
a
n
ce ev
alu
a
tion
.
In
ad
d
ition
,
th
e it
eratio
n
s
in th
e d
e
si
g
n
fl
o
w
beco
m
e
p
r
oh
ib
it
iv
e fo
r co
m
p
le
x
system
s. Th
erefo
r
e, ach
i
ev
emen
t
o
f
h
i
g
h
p
e
rfo
r
man
ce MPSo
Cs is a ch
allen
g
e. Th
e so
lu
tio
n
is st
rong
ly lin
k
e
d
t
o
th
e availab
ility o
f
fast and
accurate m
e
thods for t
h
e de
sign a
n
d pe
rform
a
nce
evaluati
on [1]. A
m
o
deling
approac
h
to re
duce t
h
e tim
e
of
desi
g
n
a
nd
val
i
d
at
i
on t
i
m
e for
M
PSoC
s
i
s
t
o
use t
h
e
Tra
n
sa
ct
i
on Le
vel
M
odel
i
n
g m
odel
s
(TLM
)
[
2
]
.
S
o
wi
t
h
TLM
, we
can
val
i
d
at
e t
h
e
be
havi
or
f
o
r
b
o
t
h
t
h
e
har
d
wa
re
and
t
h
e s
o
ft
wa
re c
o
m
pone
nt
s of
M
P
S
o
C
pl
at
form
as well as t
h
e i
n
teraction
between them
.
B
e
si
des, T
L
M
cosi
m
u
l
a
t
i
on
al
so al
l
o
ws t
h
e pe
rf
or
m
a
nce evaluati
on of the
whole sy
ste
m
at the
earl
i
e
r st
ages o
f
t
h
e desi
g
n
fl
ow
bef
o
re m
a
ki
ng a p
r
ot
ot
y
p
e
, whi
c
h i
s
fas
t
er t
h
an H
D
L r
e
gi
st
er-t
ra
ns
fer
l
e
vel
(
R
TL) sim
u
lati
o
n
[3
] [4
].
For t
h
is work,
an ope
n
source
ISS is
used a
n
d
co
m
p
on
en
ts
m
o
d
e
led
with
Syste
m
C lan
g
u
ag
e Version
2.
2.
0
[5]
a
n
d
T
L
M
m
e
t
hod
ol
o
g
y
,
deri
ved
f
r
o
m
SocLi
b
[
6
]
.
We ad
opt
a st
rat
e
gy
fo
r est
i
m
at
i
ng t
h
e per
f
o
r
m
a
n
ce at
two levels: Cycle Accurate
Bit Accurate
(CABA) a
n
d
Instruction Set
Sim
u
lator
with priority m
a
nagem
e
nt and ti
m
i
ng ISSPT
.
Our o
b
j
ectiv
es in
th
is pu
b
licatio
n
are:
•
t
o
de
vel
o
p a
r
a
pi
d e
x
pl
o
r
at
i
o
n
of
pe
rf
orm
a
nce o
f
desi
g
n
M
PSoC
t
o
ol
;
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 5
,
N
o
. 5
,
O
c
tob
e
r
20
15
:
975
–
9
83
97
6
• to
sh
ow t
h
at t
h
e
ISSPT m
o
del o
f
fers a
b
e
tter altern
ativ
e t
h
an (a:
fast si
m
u
la
tio
n
an
d im
p
r
ecise) and
(b: sim
u
lation with an inc
r
eas
ed
accuracy but at the cost of
longer
sim
u
lation), but
at
the
cost of an a
ddi
tional
m
odeling effort. This latest ef
fort is
neve
rthe
less quite acce
ptable in cont
rast to the
loss
of
accuracy in
(a)
or
loss of sim
u
lation s
p
eed i
n
(b). In sp
ite of these losses,
(a)
and
(b) are
no
w widely u
s
ed
in
syste
m
ev
al
u
a
tio
n,
th
is is on
ly b
e
cau
s
e it lack
ed
a b
e
tter altern
ativ
e.
The
rest
o
f
t
h
i
s
pa
per
i
s
o
r
g
a
ni
zed a
s
f
o
l
l
o
ws:
an
o
v
e
r
vi
e
w
of
rel
a
t
e
d
w
o
r
k
on
ex
-i
st
i
n
g
pl
at
fo
rm
of
si
m
u
latio
n
with
TLM for MPSo
C is p
r
o
v
i
d
e
d
in
section
2
.
Section
3
d
e
scrib
e
s th
e arch
itectu
r
e of the
m
u
lti-
MicroBlaze syste
m
. Section
4 prese
n
ts the
sim
u
lation
pl
atform
and modeling
of
ISSPT with
round-robi
n
app
r
oach
. Se
ct
i
on 5
desc
ri
bes t
h
e
per
f
o
r
m
ance est
i
m
a
ti
on i
n
IS
SPT.
Sect
i
on
6
pre
s
ent
s
t
h
e e
x
e
m
pl
es of
so
ft
ware. Fi
n
a
lly in
sectio
n 7
d
e
scri
b
e
s t
h
e resu
lts of t
h
e app
licatio
n
s
ru
nnin
g
on
th
e p
l
atfo
rm
.
2.
RELATED WORK
A l
o
t
o
f
w
o
r
k
s on
desi
g
n
e
x
pl
o
r
at
i
on a
n
d per
f
o
r
m
a
nce eval
uat
i
o
n f
o
r e
m
bedded sy
st
e
m
s M
PSoC
have
bee
n
co
n
duct
e
d. A
s
a r
e
sul
t
of t
h
ese
r
e
searche
s
, m
a
ny
of ex
pl
o
r
at
i
o
n en
vi
r
onm
ent
s
are pr
o
pose
d
, suc
h
as M
I
L
A
N
[
7
]
,
STAR
SoC
[8]
a
n
d Si
m
S
oC
[
9
]
.
The
wo
rk
prese
n
t
e
d i
n
t
h
i
s
pa
p
e
r ca
n
be
see
n
as
com
p
le
m
e
ntary to these
environm
ents.
Since the
first
appeara
n
ce
of TLM in
2000 [10], a
n
i
n
cre
a
si
ng n
u
m
b
er of resea
r
ch
p
r
oject
s
ha
ve
ex
am
in
ed
th
e
p
r
ob
lem
o
f
its
d
e
fi
n
itio
n
,
wh
ich
led to
sev
e
ral fram
ework
s
[1
1
]
[12
]
[13
]
and
a m
u
ltitu
d
e
versi
o
n
s
l
a
t
e
st
i
s
TLM
2
.
0
.
1
.
Al
l
t
h
ese st
udi
es ha
ve t
w
o
fa
ct
ors i
n
c
o
m
m
on:
1)
T
L
M
i
s
fea
t
ure
d
on
seve
ra
l
l
e
vel
s
;
2)
The
as
pect
s
of
com
m
uni
cat
i
on a
n
d c
o
m
put
i
ng
pl
at
fo
rm
s are se
parat
e
d.
Vi
au
d an
d al
.
[1
4]
were t
h
e
fi
rst
w
ho
p
r
o
p
o
se
d ha
ve an
effi
ci
ent
TLM
wi
t
h
t
i
m
i
ng m
odel
i
ng an
d
si
m
u
latio
n
environ
m
en
t b
a
sed
o
n
parallel d
i
screte ev
en
t
p
r
in
cip
l
es.
Th
ey
o
b
t
ain
e
d a long
run
tim
es si
mu
lation
factor but they
did
not m
eas
ure t
h
is
runtimes on real a
p
plications. T
h
eir
m
odel
i
s
al
so di
f
f
ere
n
t
f
r
om
o
u
r
s
.
Fi
rst
l
y
, wi
t
h
o
u
r a
p
pr
oac
h
w
e
can
be a
ppl
i
e
d f
o
r hi
e
r
arc
h
i
cal
or
di
st
ri
b
u
t
e
d M
P
S
o
C
des
i
gn,
an
d sec
o
n
d
l
y
, i
t
i
s
o
p
e
n-
sour
ce.
Ki
m
[15]
an
d B
o
uk
hec
h
e
m
[8]
pr
op
os
ed a ne
w t
echni
que
fo
r
H
W
/
S
W c
o
-si
m
ul
at
i
on f
o
r
het
e
r
oge
ne
ous
M
PSoC
pl
at
fo
rm
s i
n
t
i
m
i
ng
m
odel
PVT,
w
e
ha
ve al
l
ad
v
a
nt
ages
o
f
P
V
T t
h
at
we
re
fi
ned
i
n
or
der
t
o
a
d
d i
t
as a
pri
o
ri
t
y
m
a
nagem
e
nt
. Al
so
we i
n
t
e
grat
e
d
c
o
m
put
at
i
on
and
com
m
uni
cat
i
on si
m
u
l
a
t
i
on.
3.
AR
CHITE
C
T
URE
The
basi
c a
r
c
h
i
t
ect
ure o
f
t
h
e
pl
at
fo
rm
im
pl
em
ent
e
d i
n
V
H
D
L a
n
d
ge
nera
t
e
d f
r
o
m
Xi
l
i
nx Pl
at
f
o
rm
Studi
o, c
o
nsists of: 1, 2 or
3
MicroBlazes e
ach
one
conne
c
ted with a
pri
v
ate m
e
m
o
ry 64
KB BRAM
via the
LM
B
bus
p
r
o
c
essor
s
. P
r
ocess
o
rs a
r
e al
s
o
c
o
nnect
e
d
t
o
t
h
e
OPB
bus
[
17]
,
SR
AM
m
e
m
o
ry
of
3
2
M
B
[
1
6]
, an
in
terru
p
t
h
a
nd
l
e
r, VGA con
t
ro
ller, tim
er a
n
d
GPIO. A
high-le
v
el vie
w
of the ar
c
h
i
t
ecture of m
u
lti-core
MicroBlaze is
illustrated in Fi
gure
1.
Figure 1.
Multi-MicroBlaze basic
architecture
Th
e sam
e
co
n
cep
t th
at is i
m
p
l
e
m
en
ted
i
n
VHDL, it i
s
i
m
p
l
e
m
en
ted
in
Syste
m
C
en
v
i
ron
m
en
t.
Fi
gu
re
2 s
u
m
m
a
ri
zes o
u
r
f
r
am
ewo
r
k
pr
op
osa
l
.
Share
d
Mem
o
ry
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Multilevel MPSoC
Performance Ev
aluation, new
ISSPT
model
(A. Ala
li)
97
7
Master so
ck
et
(in
itiato
r)
Slave s
o
c
k
et (t
arget)
I
n
t
e
rru
p
t
in
p
u
t
Figure
2. Platform
archit
ecture
with 2 proces
sors
In o
u
r
case st
udy
, i
n
IS
S (I
nst
r
uct
i
on S
e
t
Sim
u
l
a
t
o
r) sim
u
l
a
t
i
on and
by
usi
n
g i
n
t
e
r-
pr
oce
s
s
com
m
uni
cat
i
on, we c
o
n
n
ect
t
w
o I
SSs (t
wo
pr
ocess
o
rs
) wi
t
h
Sy
st
em
C
com
m
uni
cat
i
on m
odel
s
. Theref
ore
,
i
t
is
easy
t
o
add
or
t
o
rem
ove a pr
ocess
o
r
fr
om
the M
P
S
o
C
des
i
gn. T
h
e i
n
t
e
rc
on
nect
i
o
n i
s
ba
sed o
n
OPB
b
u
s
[1
7]
descri
bed i
n
T
L
M
Sy
st
em
C
.
C
o
m
m
uni
cat
i
o
n m
odel
uses com
m
uni
cat
i
on m
echani
s
m
for t
h
e share
d
m
e
m
o
ry
,
th
e bu
s arb
itratio
n
m
ech
an
ism
is
m
a
n
a
g
e
d
b
y
bu
s arb
iter
wh
ich
im
p
l
e
m
en
ted
b
y
the ro
und
-rob
in arbitratio
n
p
o
licy (d
escribed
in Net
w
ork
in
terconn
ection
m
o
d
e
l section
)
.
4.
SYSTE
M
C SI
MUL
A
TIO
N
PLATFO
RM
Prov
i
d
e a state
m
en
t th
at what is ex
p
ected
, as st
ated
in
th
e "In
t
rodu
ctio
n
"
ch
ap
ter can
u
ltim
a
t
el
y
resu
lt in
"Resu
lts and
Discussio
n
"
ch
ap
ter, so
th
ere
is co
m
p
atib
ilit
y. Mo
reo
v
e
r, it can
also
b
e
add
e
d
t
h
e
pr
os
pect
of t
h
e devel
o
pm
ent
of resea
r
ch r
e
sul
t
s
and a
p
p
l
i
cat
i
on pr
ospe
ct
s of fu
rt
he
r st
udi
es i
n
t
o
t
h
e ne
x
t
(base
d
on resul
t
and
disc
ussi
on).
4.
1.
Process
o
r
Model and Simul
a
ti
on
W
i
t
h
t
h
e TLM
app
r
oac
h
, t
h
e
beha
vi
o
r
o
f
a
pr
ocess
o
r
has
t
w
o m
a
jor de
scri
pt
i
o
ns I
SS
and C
A
B
A
(Cycle Accu
rate/Bit Accu
rat
e
).
In th
e ISS, th
e
p
r
o
ces
sor
d
e
scri
p
tio
n is
m
o
d
e
led
with
a sp
ecific in
stru
ctio
n
lev
e
l si
m
u
lato
r. In
st
ru
ction
s
are ex
ecu
t
ed
seq
u
e
n-tially
without re
fere
ncing t
o
the m
i
cr
o-a
r
chitecture
of the
com
pone
nt. C
A
BA m
odels t
h
e beha
vior
of the system
at each cycle sim
ilar to the RTL level,
Inde
ed, t
h
e
C
A
B
A
l
e
vel
m
odel
i
ng i
s
ba
sed o
n
t
h
e t
h
e
o
ry
o
f
"fi
n
i
t
e
st
at
e
m
achi
n
e (FSM
) i
n
t
e
rc
o
nnect
e
d
sy
nc
h
r
o
n
ous"
(Sy
n
c
h
r
o
no
us
C
o
m
m
uni
cat
i
n
g Fi
ni
t
e
St
at
e
M
achi
n
es
) [
1
9]
[
20]
[2
1]
.
The estim
ated
perform
a
nce in ne
w ISSPT
(Instruc
tion
Set Sim
u
lat
i
o
n
with
timin
g
an
d
priority
m
a
nagem
e
nt
) l
e
vel
ret
u
r
n
s t
o
eval
uat
e
per
f
o
r
m
ance o
f
t
w
o
part
s cal
c
u
l
a
-t
i
o
n
an
d c
o
m
m
u
n
i
cat
i
on t
i
m
e.
For calc
u
lation time, to assess the
tim
e
of each task we
us
ed the
sim
u
lator Micro-Blaz
e process
o
r
ISS lev
e
l
b
u
t
ad
d
i
n
g
tim
e. Fo
r th
is
we m
a
i
n
ly id
en
tif
ied
the num
b
er a
n
d type
of i
n
structions e
x
ecut
e
d as
relev
a
n
t
activ
ities in
th
e processo
r co
m
p
on
ent.
Tim
i
ng exec
ution inst
ructions
of MicroBlaze
process
o
r is e
s
tim
a
ted from
the
tech-nical
doc
um
entation provide
d
by R
e
fere
nce
Gui
d
e
of MicroBlaze [16].
Belo
w is an
exa
m
p
l
e o
f
ou
r t
h
read
im
p
l
e
m
e
n
tatio
n
to
im
p
l
e
m
en
t th
e fun
c
tio
n
a
lity o
f
th
e calcu
latio
n
part (
p
roces
so
r)
descri
bed
in level I
SSP
T. F
o
r
co
mmu
n
i
cation
tim
e
is d
e
tailed
in
Bu
s and
Network
in
terconn
ection
m
o
d
e
l section
.
void MicroBlazeIss::step(void) {
/* decode of instruction outstanding */
IDecode(m_ir, &ins_opcode, &ins_rd, &ins_ra, &ins_rb, &ins_imm);
switch (ins_opcode) {
//execution of instruction
case OP_ADD:
next_pc = r_npc + 4;
Wait(ADD_delay,sc_core::SC_NS)
break;
T
w
o distinct L
i
nux
processes
Sy
ste
m
C envir
onm
ent
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 5
,
N
o
. 5
,
O
c
tob
e
r
20
15
:
975
–
9
83
97
8
………
//load of data
case OP_LW:
…..
LOAD(READ_WORD, addr, time);
next_pc = r_npc + 4;
Wait(Transaction_delay,sc_core::SC_NS)
break;
………….
}
}
4.
2.
Mem
o
ry
M
o
d
e
l
The m
e
m
o
ry
m
odul
e t
h
at
w
e
desi
g
n
e
d
i
s
a passi
ve "sl
a
ve
" com
pone
nt
com
posed
of t
w
o co
nc
ur
ren
t
part
s, one fo
r
i
n
st
ruct
i
o
ns and one fo
r dat
a
.
A
m
e
mory transaction includes
t
w
o m
e
t
hod
s:
re
ad and
write. This structure allows
us to
accelerat
e the sim
u
lation. These tw
o
m
e
thods are
called and e
x
e
c
uted
d
i
rectly in
th
e th
read
i
n
itiato
r
co
nn
ected to the m
e
m
o
ry co
mp
on
en
t.
In ou
r en
v
i
ronmen
t, th
e target p
o
rt
is con
n
ected
d
i
rectly to
th
e bu
s. Data p
a
rt m
e
m
o
ry is sh
ared
betwee
n the
process
o
rs
. Acce
ss tim
e
and cycle time pa
rameters are added
to
th
e co
mp
on
en
t d
e
scriptio
n
to
estim
a
te performance.
4.
3.
Bus and
Netw
ork I
n
terc
on
n
ection
Model
Our a
r
chitecture platform
is designe
d
a
r
ound
t
h
e OPB
bus (On-C
h
ip Pe
ripheral
Bus)
whos
e
archi
t
ect
u
r
e
wa
s devel
ope
d b
y
IB
M
[17]
. T
h
e b
u
s s
u
p
p
o
rt
s vari
o
u
s
feat
u
r
es de
pe
ndi
ng
on t
h
e
desi
re
d
bus
o
p
e
ration
s
: sing
le cycle read
/
w
rite, m
u
ltip
le m
a
sters, b
l
o
c
k
transfer. In
o
u
r work, we u
s
e
OPB
Bu
s
co
nn
ected
Xilinx MicroB
laze process
o
r.
In t
h
i
s
pa
per
,
we ha
ve l
i
m
ited de
vel
o
p an
i
n
t
e
grat
ed B
u
s cross
b
ar
, w
h
i
c
h i
s
based o
n
t
w
o m
a
i
n
feat
ure
s
ro
ut
i
n
g an
d ar
bi
t
r
at
i
on see Fi
gu
re 3 an
d 4. T
h
e r
out
e
r
i
s
a gene
ri
c com
pone
nt
t
h
at
di
rect
s a reque
st
fro
m
an
in
itiat
o
r to
t
h
e targ
et in
qu
estio
n, usin
g
a
rou
ting
tab
l
e sp
ecified.
W
h
en
a
n
e
w t
r
an
saction
g
e
t fro
m
in
itiato
r, th
e rou
t
er
reads th
e
co
rresp
ond
ing
ad
dresses and
selects an
o
u
t
pu
t port, th
is
pro
cess is illu
strated
in
Fi
gu
re 3.
Fi
gu
re
3.
R
o
ut
er c
o
m
pone
nt
To
m
a
n
a
g
e
con
f
licts b
e
tween
m
u
lt
ip
le si
mu
ltan
e
ou
s requests to
a targ
et, we d
e
v
e
l
o
p
e
d
an
activ
e
com
pone
nt cal
led “arbiter” t
o
sc
he
dule t
h
e
access to
s
h
a
r
ed res
o
urces
.
When initiator needs
access
to a
sh
ar
ed
targ
et, v
i
a th
e in
ter
c
on
n
ection
n
e
t
w
o
r
k
,
it sen
d
s a r
e
qu
est u
s
ing th
e co
r
r
e
spond
ing
co
mm
u
n
i
catio
n
ch
ann
e
l and
waits for t
h
e
resp
on
se.
At th
e arb
iter,
on
e
t
h
rea
d
rea
d
s queries
pres
en
t
in
th
e FIFO
of each
co
mm
u
n
i
catio
n
ch
ann
e
l an
d
selects th
e pr
i
o
r
ity r
e
q
u
e
st based
o
n
th
e arb
itr
atio
n ro
und-
ro
b
i
n
str
a
teg
y
. Af
ter
p
r
o
cessi
n
g
b
y
th
e targ
et, th
e
arb
iter tran
sm
i
t
s th
e re
sp
onse
i
n
t
h
e corre
sp
on
di
n
g
FI
FO
o
f
t
h
e com
m
uni
cat
i
on
channel.
Th
e in
itiato
r retriev
e
s th
e respo
n
s
e and
co
m
p
letes th
e tran
sactio
n
.
Th
is commu
n
i
catio
n
man
a
g
e
m
e
n
t
bl
oc
ks a
r
o
ut
er
d
u
ri
ng
t
h
e
p
r
o
cessi
ng
o
f
t
h
e
req
u
est
by
t
h
e
t
a
rget
,
w
h
i
c
h
c
a
n
be a
d
r
a
w
b
ack.
H
o
we
ve
r,
i
t
has
t
h
e adva
nt
age
,
sim
p
l
i
f
i
cati
o
n
of t
h
e pr
ot
oc
ol
and re
duce
d the num
b
er of port
s. T
h
e
s
e two factors
can
Run()
{
Read_ne
w_a
ddre
ss()
Switch (address){
Select_port();
}
}
To sl
ave 0
To sl
ave 1
To slave N
Por
t
0
Por
t
2
Por
t
N
Fro
m
initia
tor
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Multilevel MPSoC
Performance Ev
aluation, new
ISSPT
model
(A. Ala
li)
97
9
accelerate the sim
u
lation. Our arbiter pl
ays a second role very im
portant,
is
used for the estim
a
tion of
delays
in
th
e i
n
terco
n
n
ectio
n n
e
t
w
o
r
k
.
Fi
gu
re
4.
A
r
bi
t
e
r c
o
m
pone
nt
Fi
gu
re
5 s
h
ow
s t
h
e i
m
pl
em
ent
a
t
i
o
n
o
f
a c
r
oss
b
ar
f
r
om
t
h
e t
w
o
m
odul
es
"r
out
er"
an
d
"arbi
t
e
r".
T
h
i
s
arch
itecture is relativ
ely si
m
p
le, b
u
t
sufficien
t to
ach
iev
e
ou
r
o
b
j
ectiv
e to o
b
s
erv
e
the restrain
ts and
ret
r
iev
e
in
fo
rm
atio
n
abo
u
t
latencies. Sev
e
ral i
n
terco
n
n
ectio
n
topo
log
i
es can
b
e
d
e
sig
n
e
d
as m
u
lti-
stag
e
n
e
two
r
k
.
Fi
gu
re
5.
C
r
oss
b
ar
i
m
pl
em
ent
a
t
i
o
n
5.
PERFORMANCE E
S
TIMATION IN ISSPT
The m
o
m
e
nt when a
proce
ssor pe
rform
s
its corr
es
ponding
me
m
o
ry access can a
ffect the
access tim
e
o
f
th
e
o
t
h
e
r pro
cessor in
a
co
llisio
n
.
Fi
gure 6
sh
ow
s an
ex
am
p
l
e o
f
co
n
t
en
tio
n
detectio
n
error in
th
e
in
terconn
ection
n
e
twork
d
u
e to
n
o
n
-com
p
l
ian
ce with
the deadlines
events (Pac
k
e
t
set
up, R
o
ut
i
ng an
d
Arb
itratio
n).
Wh
en
t
h
e tran
smit
ted
p
a
ck
et from
process
o
r
1 arrives at t
h
e
ro
uter
(R &
A in Figure
6), t
h
ere is
n
o
po
ssib
ility o
f
d
e
tectin
g
t
h
e o
ccup
a
tion
of th
e rou
t
er
b
y
th
e pro
cessing
o
f
t
h
e p
a
ck
et co
m
i
n
g
fro
m
p
r
o
cesso
r
0
.
In effect, ev
en
ts i
n
th
e sub
-
lev
e
l ISST are in
stan
tly
executed (zero delay).
Th
is
ab
stractio
n
ch
an
ges th
e
beha
vi
o
r
o
f
t
h
e part
y
i
n
t
h
e com
m
uni
cat
i
on sy
st
em
, whi
c
h re
duces t
h
e
preci
si
o
n
o
f
pe
rf
orm
a
nce est
i
m
at
i
on.
To
so
lv
e th
is
prob
lem
,
we h
a
v
e
im
p
r
ov
ed the sub
l
ev
el
ISS
b
y
in
trod
u
c
i
n
g syn
c
h
r
o
n
i
zatio
n in
stru
ction
s
. Th
ey
tak
e
in
to
acco
u
n
t
th
e ti
m
e
o
f
co
m
p
on
en
t activ
ities, d
e
lays in
forward
i
ng
p
a
ckets an
d
fi
n
a
lly th
e
com
m
uni
cat
i
on
pr
ot
oc
ol
. T
h
e
s
e are t
h
e
ch
aracteristics o
f
the ISSPT lev
e
l.
To com
p
are the estim
a
tion error betwee
n ISSPT leve
l
an
d C
A
B
A
l
e
vel
i
n
o
u
r
pl
at
fo
rm
, we ha
d t
o
im
pl
em
ent
t
h
e speci
fi
cat
i
o
ns
o
f
t
h
e
O
P
B
p
r
ot
ocol
.
T
o
e
m
ul
at
e t
h
e sa
m
e
beha
vi
o
r
o
f
t
h
e
O
P
B
pr
o
t
ocol
i
n
Router
Arbiter
Shared
me
mo
r
y
B
i
directional
Cha
n
ne
l
Fro
m
initiator1
Fro
m
initia
tor
N
Run()
{
Receive_r
eque
st( e
v
0 and
…
and ev
N);
Arb
i
t
r
at
e
();
Sen
d
();
}
To
s
l
av
e
From
in
it
ia
to
r 0
Processors
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 5
,
N
o
. 5
,
O
c
tob
e
r
20
15
:
975
–
9
83
98
0
ISSP
T su
bl
e
v
e
l
and
ob
ser
v
e
t
h
e be
ha
vi
or
o
f
com
p
o
n
ent
s
,
t
h
e wai
t
(
)
st
at
em
ent
s
have
been
ad
de
d i
n
t
h
e
descri
pt
i
o
n
o
f
t
h
e com
p
o
n
e
n
t
s
an
d
bef
o
r
e
t
h
e t
r
an
sm
i
s
si
on
of
o
r
de
rs
and a
n
s
w
er
que
ri
es. T
h
e
wai
t
()
state
m
ents added re
quire a
r
guments expresse
d in units of
ti
me su
ch
as
n
a
no
seco
nd
s (n
s)
o
r
nu
m
b
er
of
cycles.
In
our expe
riments, these a
r
gum
e
nt
s are
measured from
CABA platform
. Tabl
e 1
sh
ows
t
i
m
e
m
a
de i
n
t
h
e
ISSPT lev
e
l.
LT0
: Local
Tim
e
r 0;
LT1
:
L
o
cal Tim
e
r 1;
DRe
q
: Data R
e
q
u
e
st
Pkset
: Packet Setup;
R&
A
: Ro
u
ting
and
Arb
itration
;
Acc
e
: Me
m
o
ry Ac
cess
TPkset
: Pack
et Setu
p tim
e
;
TNet
: Netwo
r
k
t
i
m
e
Fi
gu
re
6.
Ti
m
i
ng
est
i
m
at
i
on i
n
ISSP
T s
ubl
e
v
el
Tab
l
e
1
.
Tim
e
activ
ities u
s
ed
in
th
e exp
e
rimen
t
s
Act
i
viti
es
Ti
m
e
(cyc
les
)
Pr
epar
ing an
OPB co
m
m
and r
e
ques
t
4
Pr
epar
ing a r
e
spon
se
OPB r
e
quest
5
Execution
of an ins
t
ruction
1
read
m
e
m
o
r
y
acc
es
s
2
writ
e m
e
m
o
r
y
a
cce
ss
2
VGA 360000
6.
SOFTWARE
INTEGRATION
Th
e app
licatio
n
layer
h
a
s t
w
o software
s a
n
d
was tested in t
h
e
platform
:
• The gam
e
of
life is an infi
nite two-dim
e
nsional
or
t
h
ogona
l grid
of s
q
uare cells, each of whic
h is i
n
one
of t
w
o
pos
s
ible states, alive or dea
d
. E
v
ery cell inte
racts with
its eig
h
t n
e
ig
hbo
rs, wh
ich
are t
h
e cells th
at
are horizontally,
ve
rtically,
or diagonally adjacent [18],
• JPEG En
co
der is a m
i
n
i
ma
listic JPEG enco
d
e
r
wr
itten
i
n
C. It is
b
o
t
h “p
ortab
l
e”
(tested
on
x
86
and MicroBlaze) and “light
weight” (a
round 600 LOC
)
.
Application
allows
us to
writ
e JPEG c
o
m
p
ressed
im
ages fr
om
i
nput
i
m
age dat
a
o
n
m
e
m
o
ry
. It
w
o
r
k
s
i
n
“
g
ra
y
s
cal
e onl
y
”
(
m
onoch
r
om
e JPEG
fi
l
e
):
t
h
er
e i
s
n
o
sup
p
o
rt
f
o
r c
o
l
o
r
so
fa
r,
*
I
t
pr
odu
ces baselin
e, D
C
T-based
(
S
O
F
0
)
,
JFI
F
1
.
01
(
A
PP0
)
JPEG
-
s
,
*
I
t
supp
or
ts “8
x8
b
l
o
c
k
s
on
l
y
”,
*
It in
clud
es
d
e
fau
lt
q
u
a
n
tizatio
n and
Hu
ffm
a
n
tab
l
es th
at are no
t custo
m
iz
ab
le at run
t
i
m
e
.
Gene
rally, for
each a
pplication, it exec
uted
by 1, 2
or 3
pr
ocess
o
rs
, it is store
d
in t
h
eir l
o
cal m
e
m
o
r
y
and they e
x
ec
uted in
pa
rallel and sync
hronized
by the
sam
e
clock system
.
7.
RESULTS
A
N
D
DI
SC
US
S
I
ON
We presen
t resu
lts th
at we carried
ou
t to
v
a
lid
at
e ou
r pl
at
f
o
rm
and e
v
al
u
a
t
e
i
t
s
perf
orm
a
nces.
We
al
so c
o
m
p
are p
e
rf
orm
a
nces a
m
ong t
h
e
di
f
f
e
r
ent
a
b
st
ract
i
o
n l
e
vel
s
.
The sam
e
envi
ro
nm
ent
was em
pl
oy
ed for si
m
u
l
a
t
i
on o
n
di
ffe
rent
ab
st
ract
i
on l
e
vel
s
.
The
resul
t
s
o
f
sim
u
l
a
t
i
on wer
e
got
t
e
n by
r
u
n
n
i
n
g t
h
e pl
at
fo
rm
on a core 2
du
o wi
t
h
a R
A
M
m
e
m
o
ry
si
ze of 1GB
,
ba
sed o
n
Lin
u
x
Fedo
ra
8
C
o
re
3
.
1
.
ISS was
bu
ilt b
y
t
h
e
GNU cross-co
m
p
iler (GC
C
v
e
rsion
3
.
4
.
6).
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Multilevel MPSoC
Performance Ev
aluation, new
ISSPT
model
(A. Ala
li)
98
1
7
.
1
Simula
ti
on Results in CABA, ISST and ISSPT.
Fi
gu
re 7 a
n
d 8
sho
w
s S
p
ee
d
up a
n
d p
r
eci
si
on si
m
u
l
a
t
i
on
resul
t
s
f
o
r C
A
B
A
, I
SST a
n
d
ISSP
T wi
t
h
Gam
e
of Li
fe
as a s
o
ft
war
e
, an
d t
h
e sam
e
si
m
u
l
a
ti
on s
h
o
w
n i
n
Fi
g
u
r
e 1
0
a
n
d
11
wi
t
h
J
P
EG
E
n
code
r.
Sp
eed
u
p
corresp
ond
s t
o
th
e
si
m
u
latio
n
or
ex
ecu
tion ti
m
e
of so
ft
ware at
th
e
d
i
fferen
t si
m
u
latio
n
ab
st
ractio
n
lev
e
ls.
t2
=
‘end
tim
e’, t1
= ‘start ti
me’.
Spee
d-
u
p
f
o
rm
ul
a:
x
bi
t
Precision formula:
∆
x -
∆
b
it
W
i
t
h
‘x
’
= ‘C
ABA
’
,’
I
SST
’ or
‘
I
SSP
T’.
Fi
gu
re
7.
S
p
ee
du
p si
m
u
l
a
t
i
o
n
res
u
l
t
s
f
o
r
C
A
B
A
,
ISST
a
n
d
ISSP
T, s
o
ftware use
d
:
Gam
e
of life
Fi
gu
re
8.
Preci
si
on
si
m
u
l
a
t
i
on res
u
l
t
s
f
o
r
C
A
B
A
,
ISST
a
n
d
ISSP
T, s
o
ft
war
e
use
d
:
Gam
e
of
l
i
f
e
Fi
gu
re
9.
S
p
ee
du
p si
m
u
l
a
t
i
o
n
res
u
l
t
s
f
o
r
C
A
B
A
,
ISST
a
n
d
ISSP
T, s
o
ft
war
e
use
d
:
JP
EG
Enc
ode
r
Evaluation Warning : The document was created with Spire.PDF for Python.
I
S
SN
:
2
088
-87
08
I
J
ECE Vo
l. 5
,
N
o
. 5
,
O
c
tob
e
r
20
15
:
975
–
9
83
98
2
Fi
gu
re 1
0
. Prec
i
s
i
on
si
m
u
l
a
t
i
on resul
t
s
fo
r
C
A
B
A
,
I
SST
a
n
d ISSP
T,
s
o
ft
w
a
re used:
JPE
G
Enc
o
der
Mo
d
e
ls were
si
m
u
lated
:
ISSPT, ISST an
d CABA
,
we tested
CABA
m
o
d
e
l b
y
its
co
m
p
arin
g
a
sy
nt
hesi
zabl
e
R
TL
m
odel
(
u
si
n
g
V
H
D
L
gene
rat
e
d
fr
om
Xi
l
i
nx Pl
at
form
St
udi
o
and si
m
u
l
a
t
e
d wi
t
h
M
odel
S
i
m
) [1
9]
. Th
e fi
rst
t
w
o m
odel
s
a
r
e
use
d
t
o
va
lidate the softwa
re and the
syst
e
m
architecture (they
i
n
cl
ude
t
h
e
IS
Ss,
bu
s m
odel
at
t
r
ansact
i
o
n
l
e
vel
,
a
n
d
m
odel
s
o
f
ot
he
r c
o
m
pone
nt
s, al
l
bl
oc
ks
use
Sy
st
em
C
m
odel
s
).
We val
i
d
at
e
d
t
h
e si
m
u
l
a
ti
on by
t
h
e sam
e
Test
benc
h
e
s, after runn
ing
th
e en
v
i
ron
m
en
t
we ob
tain
ed
th
ese ex
p
e
rim
e
n
t
al resu
lts:
The C
A
B
A
ha
s an
i
m
port
a
nt
preci
si
o
n
[
19]
.
ISSPT m
o
d
e
l is abou
t 20
tim
e
s
faster th
an
the CABA m
o
d
e
l.
ISSPT m
o
d
e
l is abou
t 2 ti
m
e
s
faster th
an
th
e ISST m
o
d
e
l.
The a
d
dition
of new
proce
ssors in the
system
increas
es t
h
e acceleration
factor,
whic
h i
s
explaine
d
by the
am
pl
i
f
i
cat
i
on o
f
t
h
e
com
m
uni
cat
i
on
bet
w
ee
n
t
h
e
pr
ocess
o
r
s
an
d s
h
are
d
m
e
m
o
ry
m
odul
es.
The
nat
u
re
of
t
h
e s
o
ft
ware
r
u
nni
ng
o
n
t
h
e
pl
at
form
im
pact
s pe
rf
orm
a
nce i
n
di
ffe
re
nces l
e
vel
s
.
A precise analysis of the trac
e produce
d
by the
SystemC si
m
u
la
to
r shows
th
at 8
0
% of the si
m
u
latio
n
ti
m
e
is
m
a
d
e
fo
r t
h
e ex
ecu
tion
of th
e
fun
c
ti
o
n
of th
e
b
u
s
wh
ile th
e sim
u
latio
n
ti
m
e
o
f
th
e calcu
lation
p
a
rt is
low w
h
ich refl
ects
o
u
r
c
h
oice
to treat t
h
e cas
e of ISSPT.
7.
2 Mo
del
i
n
g E
f
f
o
rt
So fa
r we
ha
ve
shown the
use
f
ul
ness of our
appro
ach i
n
term
s
of accelerat
ion
of the simulation a
nd
i
n
t
e
rm
s of per
f
o
r
m
a
nce est
i
m
a
t
i
on. H
o
we
ver
,
t
h
i
s
ap
pr
o
ach has
pr
o
v
en
effect
i
v
e al
so
i
n
t
e
rm
s of
m
odel
i
n
g
eff
o
rt
.
It
al
l
o
w
s
desi
gne
rs t
h
e
de
vel
o
pm
ent
and
val
i
d
a
tion
o
f
MPSo
C
syste
m
s in
less time. Tab
l
e I2
presen
ts
t
h
e m
odel
i
ng
eff
o
rt
e
x
presse
d i
n
t
e
rm
s of l
i
nes o
f
c
o
de (
L
OC
)
nee
d
e
d
t
o
desi
g
n
an
M
PSoC
sy
st
e
m
i
n
t
h
e
CABA and IS
SPT levels. Ac
cording to
the results, the m
odeling effort with
ISSPT is re
duce
d
of a factor of
5
9
%. Th
e u
s
e
o
f
a m
u
lti-lev
e
l si
m
u
lat
i
o
n
strateg
y
(with
ob
j
ectives)
q
u
i
ck
ly allo
ws fo
cu
sing
on
a subset o
f
M
PSoC
sy
st
e
m
s wi
t
hout
ha
vi
n
g
t
o
i
n
c
r
eas
e t
h
e m
odel
i
n
g
eff
o
rt
s f
o
r
eac
h l
e
vel
o
f
a
b
st
r
act
i
on.
Tabl
e
1. C
o
m
p
ari
n
g t
h
e
m
odel
i
ng e
f
f
o
rt
Abstra
ct
level
CABA
ISS
P
T
M
odeling effor
t
(LOC)
Pr
oces
sor
1578
1259
Bus 399
170
M
e
m
o
ry 312
133
VGA 650
167
T
i
m
e
r 340
231
T
o
tal 3279
1960
Reduction (
%
)
5
9
%
8.
CO
NCL
USI
O
N
In t
h
i
s
pa
per
,
we ha
ve prese
n
t
e
d an
d val
i
d
at
ed ou
r m
e
t
h
o
dol
ogy
f
o
r M
P
SoC
cosi
m
u
l
a
ti
on at
a hi
g
h
l
e
vel
of abst
ra
ct
i
on (Sy
s
t
e
m
C
-TLM
) wi
t
h
i
n
a si
ngl
e sim
u
l
a
t
i
on en
vi
r
o
nm
ent
based o
n
Sy
st
em
C
l
a
ngua
ge
.
Our environm
ent is based on the use of open source
ISSs models of MicroBlaze
wrapped under SystemC by
usi
n
g U
N
I
X i
n
t
e
r-
p
r
oces
s c
o
m
m
uni
cat
i
on.
C
o
m
p
ari
ng t
h
ree
di
f
f
ere
n
t
abst
ract
i
o
n l
e
vel
s
,
nam
e
ly
, ISSP
T
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
Multilevel MPSoC
Performance Ev
aluation, new
ISSPT
model
(A. Ala
li)
98
3
wh
ich
im
p
l
e
m
en
t ISS
(In
s
tructio
n
Set Simu
lato
r) with
p
r
i
o
ri
t
y
and t
i
m
ing m
a
nagem
e
nt
, IS
ST l
e
vel
whi
c
h
i
m
p
l
e
m
en
t ISS with
tim
in
g
and
fin
a
lly, CAB
A
Cycle Accu
rate Bit Accurate.
The experim
e
ntal results show that the us
e th
e ISSPT a
p
proach wit
h
System
C-TLM reduce
s
the
design
validation tim
e
and
perm
it de
velopi
ng m
odels ra
pidly with a
n
a
cceptable
prec
ision. This
m
o
tivates
ou
r ch
oi
ce fo
r Sy
st
em
C
and
TLM
as a sy
stem
desi
gn m
e
thodology, de
dicated to ar
chit
ecture exploration i
n
o
u
r
p
r
oj
ect
wh
ich
is th
e m
a
in
con
t
ri
b
u
tion of th
is wo
rk
. As p
e
rsp
ective, we th
i
n
k to d
e
v
e
lop
m
o
dels for
est
i
m
a
ti
ng t
h
e
ener
gy
c
ons
um
pt
i
o
n
at
di
ffe
re
nt
l
e
vel
s
.
REFERE
NC
ES
[1]
L. B
e
nini et al.
MPAR
M: Explo
r
ing
th
e M
u
lt
i-P
r
oces
s
o
r S
o
C Des
i
gn S
p
ac
e wi
th S
y
stem C
.
Spr
i
nger J. of VLSI
Signal Processing, 2005
.
[2]
FRANK G
H
EN
ASSIA
“TLM with S
y
stemC Concepts and
Applications for Embedde
d S
y
s
t
ems”.
Nov 2005,
Springer
[3]
A.
A.
Jerray
a
,
A.
Bouchhima
, and F. P´
etrot, “Progr
amming
models and HW-SW
interfaces abstraction fo
r
m
u
ltiprocessor SoC”,
in Proceedi
ngs of the 43rd
Annual Confer
ence on D
e
sign
Autom
a
tion (DAC ’06), pp. 28
0–
285, San
Francis
c
o, C
a
lif, USA, July
2006
.
[4]
K.
Hines and G.
Borriello,
“
Dyna
mic communication models in
embedded system
co-simulation
”, i
n
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r
oceedings
o
f
the 34
th Design
Automation Con
f
erence (DAC ’9
7), pp
. 395–400
, Anaheim, Calif, USA, June 199
7.
[5]
S
y
stemc homepage,
http
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sy
stemc.
org/.
[6]
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ac/d
e
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i/Component
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S
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M
ohant
y, V.K. P
r
as
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.
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i
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e
rog
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d
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y
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ch
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u
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a
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il
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tools for
embedded s
y
s
t
ems, Berlin
, Ger
m
an
y
,
2002.
[8]
S Boukhechem
, EB Bourennane
. TLM platform
based on s
y
stem
C for STARSoC d
e
sign space exp
l
oration
.
In AHS
'
08. NASA/ESA Conference. No
ordwijk
[9]
C Helmstetter
,
V Joloboff. SimSoC: A S
y
stemC TLM in
te
grated ISS for full s
y
stem simulation, in APCCAS 2008,
M
acao,
Chin
a
[10]
D. Gajski et al.
SpecC:S
pecification
Languag
e
and Methodolog
y. Kluwer
, 2000
.
[11]
A.
Donlin.
T
r
a
n
s
a
c
t
ion le
vel: flows a
nd use
mo
de
ls.
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S+ISSS ’04,
Stoc
kholm,
Swe
d
e
n
.
[12]
L
.
Ca
i a
n
d a
l
.
T
r
a
n
sa
c
t
ion le
vel
mode
ling:
a
n
ove
r
vie
w
. In COD
E
S+
ISSS ’03,
Ne
w York,
USA.
[13]
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i
et a
l
.
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y
stem
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u
lation
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ula
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u
ltipro
cessor S
o
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puter, vol
. 36, n
o
.
4, April 2003.
[14]
E. Viaud, F. Pecheux, and
A. Greiner
.
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nd simulation environmen
t based on parallel
dis
c
ret
e
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