Internati
o
nal
Journal of Ele
c
trical
and Computer
Engineering
(IJE
CE)
Vol.
6, No. 6, Decem
ber
2016, pp. 2688~
2
697
I
S
SN
: 208
8-8
7
0
8
,
D
O
I
:
10.115
91
/ij
ece.v6
i
6.1
204
0
2
688
Jo
urn
a
l
h
o
me
pa
ge
: h
ttp
://iaesjo
u
r
na
l.com/
o
n
lin
e/ind
e
x.ph
p
/
IJECE
FPGA Hardware Reali
z
at
ion: Add
i
tion of Two Di
gital Sign
als
Based on Walsh Transforms
Z
u
lfika
r
1
, Shu
ja A.
A
b
b
a
si
2
,
Abd
u
l
r
ahm
a
n
M.
Al
am
oud
3
1
Department
of
Electrical and
C
o
mputer Engin
e
eri
ng, S
y
iah
Kuala Univ
ersity
, Banda Aceh
,
Indon
esia
2,3
Department of
Electr
i
cal
Engin
eering
,
King
Sau
d
Universit
y
,
R
i
yadh
, Saud
i Ara
b
ia
Article Info
A
B
STRAC
T
Article histo
r
y:
Received Aug 2, 2016
Rev
i
sed
Sep
19
, 20
16
Accepte
d Oct 2, 2016
This paper pr
ese
n
ts hardware re
a
liz
ati
on of
an ad
dition of two dig
ital sign
als
based on Walsh transforms and inverse
W
a
lsh
transform
s
targe
t
ed to th
e
Xilinx FPGA
Spartan 3 board
.
The re
ali
zat
ion
utili
zes W
a
lsh T
r
ansform
to
convert th
e inp
u
t data to the
fre
quency
domain and the inverse Walsh
transform to r
e
convert
the d
a
ta
from
the fr
equency
domain. Th
e design
ed
s
y
stem is capab
l
e of p
e
rformin
g addi
tion, subtraction,
m
u
lt
ipli
cat
ion an
d
Arbitrar
y W
a
vef
o
rm
Generation (AW
G
). However, in the pr
esen
t work, the
hardware realization of additio
n onl
y
has been demonstrated. The Clock
frequency
for realization in
to
th
e board is supplied b
y
an
extern
al function
generator. Outp
ut results are captured
using a logic analy
zer
. I
nput data to
the board (s
y
s
tem) is passed ma
nuall
y
through the available slid
e switches
on-board.
Keyword:
Dig
ital sign
al
FPGA
Hard
ware realizatio
n
System
-on-chi
p
Walsh transfo
r
m
s
Copyright ©
201
6 Institut
e
o
f
Ad
vanced
Engin
eer
ing and S
c
i
e
nce.
All rights re
se
rve
d
.
Co
rresp
ond
i
ng
Autho
r
:
Zu
lfik
ar,
Depa
rt
m
e
nt
of
El
ect
ri
cal
and
C
o
m
put
er E
ngi
neeri
n
g
,
Syiah
Ku
ala
Un
iv
ersity,
Jl Syech
Ab
du
l Rau
f
No
. 7,
Dar
u
ss
alam
, Banda
Aceh-23111, Indonesia.
Em
a
il: zu
lfik
arsafri
n
a
@u
nsyiah
.ac.i
d
1.
INTRODUCTION
Th
e sim
p
licity
op
eration
s
of
Walsh transfo
r
m
s
at
tract
ed m
a
ny
sci
e
nt
i
s
t
s
t
o
devel
o
p
,
use
,
ap
pl
y
a
n
d
ev
en
co
m
b
in
e it with
o
t
h
e
r tran
sform
’
s
m
o
d
e
ls. Histo
r
ically, th
e fu
nd
am
en
tal th
eo
ry of Walsh
tran
sform
s
h
a
s
been
p
r
o
p
o
se
d
si
nce l
o
n
g
t
i
m
e ag
o [
1
-3]
.
Sev
e
ral
n
o
v
el
desi
gns
o
f
ho
w t
o
r
eal
i
ze W
a
l
s
h t
r
ansf
o
r
m
s
have
bee
n
introduced in t
h
e last se
veral
decade
s
.
In
197
6, Fino
an
d
Alg
azi p
r
op
o
s
ed
how to
ach
ie
v
e
W
a
lsh tran
sfo
r
m
u
s
in
g
ad
d
ition
and
sub
t
raction
technique [4]. The idea attracted
m
a
ny
researche
r
s for ha
rdwa
re realiza
t
i
on of W
a
l
s
h
t
r
ansf
o
r
m
s
.
Howeve
r
,
the
m
e
thod re
qui
red a
ddition an
d subtract
ion of sam
p
les in word leve
l. Later, a
m
e
thod of the
bit level
sy
st
ol
i
c
array
i
s
de
vel
o
pe
d t
o
i
n
crease t
h
e s
p
eed [
5
]
.
T
h
e
n
,
Nay
a
k a
n
d M
e
her
p
r
o
p
o
sed
a
ful
l
y
pi
pel
i
n
e
d
t
w
o-
d
i
m
e
n
s
io
n
a
l (2D)
b
it-lev
e
l
systo
lic arch
itect
u
r
e to
ach
i
ev
e
a m
o
re efficient i
m
p
l
e
m
en
tati
o
n
[6
].
Am
i
r
a et al
. prop
ose
d
a ne
w
way
of i
m
pl
em
ent
i
ng
W
a
l
s
h
t
r
ansf
orm
s
i
n
y
ears 20
0
0
an
d 2
0
0
1
based
on
Hadam
a
rd
m
a
t
r
i
ces cal
l
e
d Fast
Ha
dam
a
rd T
r
an
sf
orm
(FHT
) [
7
-
9
]
.
A m
o
re i
n
t
e
ns
e researc
h
has
been
carri
ed
o
u
t
d
u
r
i
ng l
a
st
deca
de
. Fo
r exam
pl
e,
a
m
e
t
hod
of
h
o
w t
o
ge
ne
rat
e
W
a
l
s
h
fu
nct
i
o
ns i
n
fo
ur
di
f
f
e
rent
or
deri
ng
s has
been i
n
t
r
od
uce
d
[
10]
. L
a
t
e
r,
C
h
an
dra
s
eka
r
a
n
p
r
o
p
o
se
d p
o
w
er a
n
al
y
s
i
s
o
f
W
a
l
s
h t
r
a
n
sf
orm
s
[1
1]
. The
n
, a t
echni
que
of e
f
fi
ci
ent
archi
t
e
c
t
ure o
f
W
a
l
s
h t
r
ans
f
o
r
m
s
was devel
ope
d i
n
20
08
[1
2]
be
si
des
m
a
ny
ot
he
r des
i
gns
t
h
at
has b
een pu
bl
i
s
he
d.
Th
e con
cep
t
of app
licatio
n of
Walsh tran
sfo
r
m
s
fo
r add
itio
n and
m
u
ltip
licatio
n
o
f
two
d
i
gital sig
n
a
ls
was desc
ri
be
d
earl
i
e
r [13
-
1
4
]
.
A m
o
re int
e
nsi
v
e wo
r
k
s on t
h
i
s
al
so
has been
pu
bl
i
s
he
d. M
o
st
of t
h
e
researc
h
er
s an
d sci
e
nt
i
s
t
s
fo
cus o
n
de
vel
o
pi
n
g
W
a
l
s
h t
r
a
n
sf
orm
s
onl
y
.
Ho
we
ver
,
eve
n
l
e
ss, a t
echn
i
que
o
f
i
nve
rt
i
n
g
W
a
l
s
h t
r
a
n
s
f
o
r
m
s
i
s
al
so
ha
ve
been
de
vel
o
ped
[
1
5
-
1
6
]
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
208
8-8
7
0
8
FPGA Ha
rd
ware Rea
liza
tio
n: Add
itio
n o
f
Two
Di
g
ita
l
S
i
gn
a
l
s Based on
Wa
lsh Tra
n
sforms (Zu
lfika
r
)
2
689
Th
e sim
p
lic
ity
o
f
W
a
lsh
transform
s
, co
m
b
in
es with
th
e po
werfu
lly o
f
Fo
urier tran
sfo
r
m
s
resu
lt in
a
m
o
re effi
ci
ent
t
r
ans
f
o
r
m
al
gori
t
h
m
was avai
l
a
bl
e [
1
7
-
1
9
]
.
A m
e
t
hod
o
f
c
a
l
c
ul
at
i
ng
b
o
t
h
DFT
a
n
d
WH
T i
s
devel
ope
d t
h
r
o
ug
h t
h
e
fact
o
r
i
zat
i
on o
f
i
n
t
e
r
m
edi
a
t
e
t
r
ansf
orm
T by
B
o
u
s
asakt
a
an
d
H
o
l
t
[1
7]
. A
n
e
f
fi
ci
ent
al
go
ri
t
h
m
whi
c
h com
b
i
n
es t
h
e
cal
cul
a
t
i
on of
DFT an
d
WH
T was al
so i
n
t
r
od
uce
d
. T
h
e t
echni
que i
s
bas
e
d o
n
t
h
e de
vel
o
pm
ent
o
f
radi
x-
4
f
a
st
W
a
l
s
h
Ha
dam
a
rd Tra
n
s
f
orm
(F
WHT
)
[1
8]
.
An
ot
he
r
effi
ci
ent
m
e
t
hod
o
f
calcu
latin
g
b
o
t
h
DFT
an
d WHT u
s
ing
rad
i
x
-
2
was p
u
b
lish
e
d
[1
9
]
.
Th
e n
e
w
i
d
ea
th
at u
tilizes
Rad
e
mach
er
fu
nctio
ns f
o
r
g
e
neratin
g
Discrete Fo
urie
r Tr
ansf
o
r
m
s
(DFT) has
bee
n
ca
rried
o
u
t [2
0
-
2
1
]
.
This
wo
r
k
s
pr
o
v
e
d
a st
ro
ng l
i
n
k
bet
w
ee
n D
F
T
and
WH
T si
n
ce bot
h o
f
t
h
e
m
can be ge
n
e
rat
e
d by
a
ppl
y
i
ng t
h
e p
r
od
uct
of
Radem
acher functions.
In
t
h
e pres
ent
wo
rk
,
we use Wal
s
h
t
r
a
n
s
f
o
r
m
s
for
ha
r
d
wa
re
real
i
zat
i
on o
f
t
h
e
ad
di
t
i
on of
t
w
o
di
gi
t
a
l
sig
n
a
ls
targ
eted
to
Xilin
x
Spartan
3
b
o
a
rd. Th
e rest
of
th
e p
a
p
e
r is
o
r
g
a
nized
as fo
llows. Section
2 d
e
als with
t
h
e b
r
i
e
f
t
h
e
o
r
y
of
W
a
l
s
h
or
deri
ng
. Sect
i
o
n
3 c
o
vers
sy
st
em
desi
gn c
onc
ept
,
Sect
i
o
n
4
deal
s
wi
t
h
har
d
wa
r
e
real
i
zat
i
on. Se
ct
i
on 5 prese
n
t
s
si
g
n
i
f
i
cant
c
o
ncl
u
si
ons
.
2.
WALS
H O
R
DERI
NG
Wal
s
h t
r
a
n
sf
or
m
s
i
s
a uni
que
t
r
ansf
orm
s
m
odel
;
t
h
e coef
f
i
ci
ent
m
a
y
be
or
dere
d i
n
di
f
f
e
rent
seri
es
.
Th
er
e ar
e about f
o
ur
w
e
ll-kn
ow
n
o
r
d
e
r
i
ng
s w
h
ich
ar
e seq
u
en
cy (W
alsh
),
d
y
ad
ic (
P
aley), n
a
tu
r
a
l (H
ad
amar
d
)
and
l
o
gi
c
[1]
.
The
ori
g
i
n
al
Wal
s
h
f
u
nct
i
o
ns t
h
at
are
us
ed t
o
gene
rat
e
W
a
l
s
h t
r
a
n
s
f
orm
s
are
or
de
red
i
n
seq
u
ency
.
M
eanw
h
i
l
e
,
Hada
m
a
rd
or
deri
ng
i
s
o
f
t
e
n c
r
ea
t
e
d ba
sed
o
n
Hadam
a
rd m
a
t
r
i
ces. T
h
en
,
Pal
e
y
or
deri
ng
can b
e
pr
o
duce
d
by
appl
y
i
n
g
bi
t
re
versal
of
t
h
e
H
a
dam
a
rd o
r
de
ri
ng
. T
h
e l
a
st
o
r
deri
ng m
odel
i
s
m
o
r
e
con
v
e
n
i
e
nt
w
h
en i
t
i
s
generat
e
d base
d o
n
t
h
e com
pone
nt
-
w
i
s
e pr
o
duct
o
f
R
a
dem
acher fu
nct
i
o
ns [
22]
.
Logi
c
or
deri
ng
m
odel
o
r
de
rs t
h
e c
o
e
ffi
ci
ent
s
i
n
t
h
e
i
n
creasi
n
g
n
u
m
b
er
o
f
c
o
m
pon
ent
s
of R
a
dem
acher
f
unct
i
ons
.
Tabl
e 1 s
h
ow
s
fo
ur
di
f
f
ere
n
t
W
a
l
s
h
or
de
ri
ng
f
o
r m
=
3 R
a
dem
acher f
u
n
c
t
i
ons f
o
r a t
o
t
a
l
w=2
m
=8
pos
si
bl
e of
di
s
c
ret
e
W
a
l
s
h fu
nct
i
o
n
s
[
1
]
.
Tabl
e
1.
Or
de
ri
ngs
o
f
Wal
s
h F
unct
i
o
ns
R
e
p
r
e
s
ent
e
d
as P
r
od
uct
o
f
R
a
dem
a
cher
F
unct
i
o
ns
Or
der
i
ng
w W
a
lsh
Paley
Hadam
a
r
d
L
ogic
0 R
0
R
0
R
0
R
0
1 R
1
R
1
R
3
R
1
2 R
1
R
2
R
2
R
2
R
2
3 R
2
R
2
R
3
R
2
R
3
R
3
4 R
2
R
3
R
3
R
1
R
1
R
2
5 R
1
R
2
R
3
R
1
R
3
R
1
R
3
R
1
R
3
6 R
1
R
3
R
2
R
3
R
1
R
2
R
2
R
3
7 R
3
R
1
R
2
R
3
R
1
R
2
R
3
R
1
R
2
R
3
3.
SYSTE
M
DESIGN
(ADDI
TION)
Th
e d
e
sign
of an
in
tegrated syste
m
co
v
e
rin
g
add
itio
n
,
su
b
t
ractio
n, m
u
ltip
licatio
n
an
d
AWG
h
a
s
b
een
pr
esen
ted ear
lier
[1
3-
16]. H
o
w
e
ver
,
t
h
e d
e
sign
r
e
q
u
i
r
es a very
si
gni
fi
cant
ha
rd
wa
r
e
and
he
nce i
t
need
s
qui
t
e
ex
pe
nsi
v
e FPG
As.
Al
so
, onl
y
ad
di
t
i
on
of t
w
o di
gi
t
a
l
si
gnal
s
i
s
desi
re
d. T
hus t
h
e sy
st
em
i
s
redesi
gn
ed t
o
offer hardware
realizati
on of addition only. This desi
gn c
a
n easily be accomm
odated in the sim
p
lest
and
cheape
s
t
FP
G
A
boa
r
d
– t
h
e
Spa
r
t
a
n
3
b
o
ar
d.
Th
us a
hi
ghl
y
econ
o
m
i
cal
sy
st
em
i
s
m
a
de avai
l
a
bl
e.
Fi
gu
re 1 vi
e
w
s
desi
gn
of i
n
t
e
grat
e
d
sy
st
em
f
o
r t
r
a
n
sf
orm
l
e
ngt
hs N=
4 an
d
i
nput
w
o
r
d
l
e
n
g
t
h
s
WI=
4.
C
hoi
ce
an
d
Or
derin
g
a
r
e use
d
to
select the
suitable proces
se
s an
d
Wal
s
h
or
deri
ng
s res
p
ect
i
v
el
y
.
Si
gna
l
Enter
is u
s
ed
to
pa
ss
t
h
e i
n
put
si
g
n
a
l
s X a
n
d G
.
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEC
E
2
690
Out
p
u
Out
p
u
Tabl
e
4.
H
4.
1.
to
cle
X, G
or
der
i
E
Vo
l.
6
,
N
o
.
Signal Pa
s
u
t. Conv
er
sel
y
u
t.
Tabl
e 2 s
h
e
3 vi
ews al
l
p
H
AR
DWAR
E
B
e
ha
vi
or
al
S
Fi
gu
res 2
ar all buf
fers
an
d out
p
u
t
a
d
i
ng
are
sh
ow
n
6, Decem
ber
2
Figure
1
s
s is u
s
ed
to
c
o
y
, whe
n
Pa
ss
h
ow
s
pos
si
bl
e
ossi
bl
e c
h
oi
c
e
Addit
i
Subtr
a
Multi
p
AW
G
Hada
m
Paley
Seque
n
E
REALIZ
A
S
im
u
l
a
t
io
n
a
nd 3
sh
ow
b
in
th
e syste
m
d
d
itio
n
resu
lt
v
n
i
n
Fi
gu
re
3.
Figur
e
2
016
:
2
688
–
1
. D
e
sig
n
of
I
n
o
nt
r
o
l
t
h
e out
p
= 1,
t
h
e Wa
l
e
ch
oi
c
e
of
D
S
e
s of
a
n
d W
a
l
s
Table
2
i
on
a
ction
p
lication
Table 3
.
m
ar
d
n
cy
TION
b
eha
v
i
o
r sim
u
m
. Inputs X a
n
v
iew in
Figu
r
e
2.
Ent
r
y
an
d
–
2
697
n
teg
r
ated
Sys
p
ut
vi
ew, i
f
P
l
sh c
o
efficie
n
SP proc
esses
sh or
deri
ng
,
e
2
. List
of DS
P
Choi
c
0
1
1
0
. Wals
h
Or
de
r
Or
der
i
ng
0
0
1
u
latio
n
resu
lts
n
d
G are pass
e
r
e 2,
m
eanwh
i
d
Out
put
Si
gn
a
tem
fo
r N =
4
ass
= 0, the
r
e
n
ts o
f
X, G a
n
fo
r sim
p
licit
y
e
xcept for
l
o
g
i
P
Process
e
s
c
e (1
)
C
h
0
1
1
0
r
i
n
g C
hoi
ces
(1
)
Or
d
of t
h
e d
e
si
g
n
e
d
in
to
th
e s
y
i
le coefficien
t
a
ls fo
r N =
4
a
and
WI =
4
e
s
u
l
t
i
ng si
gna
l
n
d resu
lt sig
n
y
realiza
tio
n
i
i
c or
d
e
r
i
ng
.
h
o
i
ce (0
)
0
0
1
0
d
er
ing (
0
)
0
1
0
n
e
d
system
. I
n
st
em
cont
rol
l
e
t
s
of X, G
an
d
a
nd
W
I
= 4
ISS
N
:
2
l
will b
e
avail
n
als are
a
v
ail
a
i
nt
o FP
GA
,
m
n
itially,
Reset
ed by
Enter.
E
d
o
u
t
p
ut
base
d
2
088
-87
08
a
ble at the
a
bl
e a
t
t
h
e
m
eanwhile,
goes hi
gh
E
nt
r
y
dat
a
d
on
Pal
e
y
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEC
E
4.
2.
avail
a
It ca
n
slices
and
2
realiz
out
p
u
synth
e
Numb
e
Numb
e
Numb
e
Numb
e
Numb
e
Numb
e
Numb
e
Speed
Mi
n
Mi
n
Ma
x
Ma
x
4.
3.
u
pon
out
p
u
vary
f
req
u
i
r
Clock
-----
-
Desti
n
-----
-
Outpu
t
Outpu
t
Outpu
t
Outpu
t
Outpu
t
Outpu
t
Outpu
t
Outpu
t
Outpu
t
Outpu
t
-----
-
4.
4.
Xilin
x
min
i
m
arou
n
E
F
PGA
Ha
r
Fig
u
S
y
n
t
hesis R
e
The ne
xt
a
ble afte
r
im
p
l
n
be
see
n
t
h
at
, 1
77
sl
i
ce fl
i
p
2
Gcl
k
s.
Bas
e
ation ca
n
cap
t
u
t p
o
rt
a
f
t
e
r 6.
2
e
size Selecte
d
e
r of Slices:
e
r of Slice F
l
e
r of 4 input
e
r of IOs:
e
r of bonded
I
e
r of MULT18X
1
e
r of GCLKs:
Grade: -5
n
imum period:
n
imum input a
r
x
imum output
r
x
imum combina
t
Clock
t
o
P
a
d
An
ot
he
r i
m
locati
o
n of
e
a
u
ts shou
ld b
e
a
f
ro
m
6
.
403
n
s
r
e for
im
ple
m
e
Clock to Pad
-
------+-----
-
| clk
(
n
ation | to
-
------+-----
-
t
<1> | 6
.
t
<2> | 6
.
t
<3> | 6
.
t
<4> | 6
.
t
<5> | 6
.
t
<6> | 6
.
t
<7> | 6
.
t
<8> | 6
.
t
<9> | 6
.
t
<10> | 6
.
-
------+-----
-
Hardw
a
re A
The synt
h
x
ISE
s
o
f
t
wa
r
m
i
ze devi
at
i
o
n
n
d 6.4 n
s
.
So
m
r
dw
a
r
e Real
i
z
a
u
re 3.
W
a
l
s
h
C
e
po
rt
ste
p
is to
e
x
l
e
m
en
tatio
n
s
t
the selected
d
p
-f
lop
s
, 694
o
e
d
on
th
is re
q
t
ur
e inpu
t dat
a
2
16
n
s
.
d
Device : 3s
l
ip Flops:
LUTs:
I
OBs:
1
8s:
31.493ns (Ma
r
rival time b
r
equired time
t
ional path
d
d
m
por
t
a
nt
dat
a
a
ch output
p
a
a
s sm
all as
p
o
s
to
6
.
40
5 ns
a
e
nt
i
ng t
h
e
de
s
-
------+-----
(
edge) |
PAD |Inter
-
------+-----
.
404(R)|Cloc
k
.
405(R)|Cloc
k
.
404(R)|Cloc
k
.
405(R)|Cloc
k
.
404(R)|Cloc
k
.
404(R)|Cloc
k
.
403(R)|Cloc
k
.
404(R)|Cloc
k
.
404(R)|Cloc
k
.
403(R)|Cloc
k
-
------+-----
d
j
ustments
h
esis resu
lts
v
r
e. I
n
ot
her
w
n
o
f
cl
oc
k t
o
p
m
e adjustm
e
nt
s
I
a
tio
n: Add
iti
o
C
o
e
fficien
t
s o
x
tract som
e
i
m
t
ag
e
.
So
me
o
f
d
ev
ice is su
it
a
o
f
4
inpu
t LU
T
q
ui
rem
e
nt
, t
h
a
with
arriv
a
l
200ft256-4
381 out of
177 out of
694 out of
26
26 out of
12 out of
2 out of
ximum Freque
n
efore clock:
after clock:
elay: No pat
h
a
af
te
r
i
m
p
l
e
m
a
th in
si
d
e
the
o
ssible t
o
a
v
o
a
n
d
t
h
e
de
vi
a
t
s
ign system
.
------------
-
nal Clock(s)
------------
-
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP
_
BUFGP |
------------
-
v
iewed in
th
e
w
ord
s
, t
h
e in
p
p
a
d
del
a
y
or t
i
s
are
re
quire
d
I
SSN
:
208
8-8
7
o
n
of
T
w
o Di
g
o
f En
tr
y and
O
m
port
a
nt
i
n
f
o
f
t
h
e im
p
o
r
ta
n
a
ble f
o
r ca
rry
i
T
s, 26
I/
Os (a
h
e design sys
t
tim
e
befo
re
9
1920 19%
3840 4%
3840 18%
173 15%
12 100%
8 25%
n
cy: 31.753MH
z
9.276ns
6.216ns
h
found
m
en
tatio
n
ste
p
chip. T
h
e
de
v
o
id
g
litch
e
s.
A
t
i
on i
s
m
i
nus
c
-
+--------+
| Clock |
| Phase |
-
+--------+
| 0.000|
| 0.000|
| 0.000|
| 0.000|
| 0.000|
| 0.000|
| 0.000|
| 0.000|
| 0.000|
0.000|
-
+--------+
previ
o
us sec
p
ut
a
n
d o
u
t
p
u
i
m
e
. It can be
fo
r m
a
t
c
hi
ng
7
08
ita
l S
i
gn
a
l
s
B
O
u
t
pu
t Sign
als
o
rm
atio
n
th
ro
u
n
t d
a
ta
of th
e i
m
i
ng
o
u
t
t
h
e
d
e
l
l o
f
th
em
are
t
e
m
can run
9
.
2
7
6
ns a
n
d t
h
z
)
p
is cl
o
c
k to
p
v
iatio
n
of
th
e
A
s can be
see
n
c
ule (m
axim
u
m
t
i
on a
r
e base
d
u
t p
o
r
t
s
a
r
e s
e
seen that the
the I/
O a
v
ail
a
a
sed on
Wa
ls
h
fo
r N
= 4 an
d
u
gh sy
nt
hesi
s
m
pl
em
ent
e
d
s
si
g
n
add
ition
b
ond
ed)
,
12
m
up
to
m
a
x
i
m
h
e
out
put
dat
a
p
ad
d
e
la
ys
.
T
h
e
se
d
e
la
ys
co
r
n
bel
o
w,
t
h
e
d
m
0.
0
02
ns
).
T
d
on
au
toma
t
e
lected aut
o
m
cl
ock t
o
pa
d
d
a
bilit
y in
Spa
r
h
Tr
ansforms
d
WI
= 4
s
re
po
rt.
Thi
s
s
yste
m
are gi
v
sy
ste
m
. It re
q
mu
ltip
liers (1
m
u
m
31.
75
3
M
a
will b
e
av
ail
hi
s
del
a
y
i
s
v
r
r
e
sp
ond
ing
t
o
d
el
ays of di
f
fe
T
h
e
r
e
i
s
n
o
c
l
t
ic
selectio
n
o
m
at
ic
ally
b
y s
o
d
elays of all
o
r
tan
3
bo
ard
.
(Zu
lfika
r
)
2
691
s
re
po
rt is
v
en
b
e
low.
q
u
i
res 381
8
x
18 bi
t
s
)
M
Hz. Th
e
a
ble a
t
the
v
ary
base
d
o
di
f
f
ere
n
t
fe
r
e
nt p
a
ds
l
ock
pha
se
o
f I/Os
b
y
o
ftwa
re t
o
o
utputs are
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEC
E
2
692
in
pu
t
BTN
2
K1
4,
K
b
e av
b
eca
u
C6
,
E
out
p
u
man
u
4.
5.
exter
n
th
ro
u
g
vi
ew
s
num
b
coeff
i
to
-6
w
in
cl
o
com
p
listed
E
Vo
l.
6
,
N
o
.
Tabl
e 4
s
h
an
d o
u
t
p
ut
o
f
2
),
Pass
(
M
13
K
13/
S
W
7 t
o
S
ai
l
a
bl
e c
ont
i
n
u
se eac
h
of th
e
E
7, C7,
D7, C
u
t resu
lts to
l
o
al ve
rific
a
tio
n
Reset
En
ter
Pass
X (1,
2
G (1,
2
Outpu
t
Hardw
a
re
R
Har
d
w
a
re
n
al fun
c
tio
n
g
g
h
8 sl
i
d
e
sw
i
s
fo
ur
v
a
lu
es
o
Figure
4
Fi
gu
re 5
b
ers; th
e first
i
cients of sig
n
A close e
x
w
hic
h
are th
e
o
ck to
pads d
e
ared t
o
the s
y
i
n
Ta
bl
e
4, c
a
6, Decem
ber
2
h
ows all co
n
f
f
FPGA
boar
d
/ Pu
sh
Bu
t
t
o
n
S
W4
)a
n
d
G
(
F
n
uo
usly b
e
f
o
r
e
e
m i
s
f
o
r
m
at
t
8/
Pi
n 5 t
o
12
o
gic a
n
alyzer
n
.
Tabl
e 4. O
u
t
2
, 3,
4)
2
, 3,
4)
t
(
1
,
2,
3,
4,
5,
6,
R
es
u
l
t
s
reali
zation h
a
g
en
er
a
t
or
at a
i
tch
e
s as liste
d
o
f sign
al
ou
tp
u
4
. Ou
tpu
t
S
i
g
n
sh
ows
th
e
W
four {
2
,
-8,
-
n
al
G a
n
d the
l
x
am
i
n
atio
n
is
e
s
e
co
nd
an
d
t
e
lays. As mar
k
y
nt
hesi
s res
u
l
t
a
bl
e del
a
y
an
d
2
016
:
2
688
–
f
i
g
ur
at
i
ons
f
o
.
Th
r
e
e pu
sh
b
n
B
T
N0
) and
E
F
12
, G1
2, H
1
4
e
signal Ent
e
r
ed in t
h
e
for
m
of E
x
pansi
o
n
. Th
e ou
tput
t
put an
d So
m
e
Pin / P
o
L
13 / P
u
M
13 /
P
M
14 /
P
J14,
J1
3
F12,
G
1
7,
10)
D5, C5
,
E
xpans
a
s bee
n
d
one
f
r
eq
ue
ncy
o
f
d
i
n
Tabl
e 4
a
u
t H = {0
,
4,
8
n
al
of
I
n
t
e
gra
t
W
alsh c
o
effici
e
-
18
,
0} are
c
o
l
ast f
our
n
u
m
b
s
h
ow
n i
n
Fi
g
t
he t
h
i
r
d
co
e
ff
k
ed
in
Figure
t
wh
ich
is aro
u
d
del
a
y
of
L
o
g
–
2
697
o
r
i
n
put
and
o
b
u
tton
switch
e
E
nt
e
r
(M
1
4
/
P
4, H
13/
S
W
3
t
r
g
o
es hi
gh
.
E
m
of 4
bi
t
nu
m
n
C
o
nn
ector
A
resu
lt is als
o
e
In
pu
ts Sele
c
o
sition on Boar
d
P
ush button
BT
N
2
P
ush button
BT
N
P
ush button
BT
N
3
,
K14,
K13 / S
W
1
2,
H14,
H13 / S
W
, D6
, C6
,
E
7
, C7
,
s
ion Co
nnec
t
or
A
2
usi
n
g Spa
r
t
a
n
f
2
0
M
H
z
.
I
n
a
nd
o
u
t
p
ut
i
s
8
,
2} as
a re
s
u
t
ed
S
y
s
t
e
m
(
A
e
nt
s of t
h
e
i
n
o
efficients of
b
ers
{14, 2,
-
6
g
ur
e 6.
Th
e f
i
g
ff
icien
t
s o
f
si
g
6, t
h
e l
o
nge
s
t
u
n
d
6.
4 ns.
T
g
ic Analyzer.
o
u
t
pu
t. This
s
e
s a
r
e assi
gne
P
ush
B
u
t
t
on
B
t
o
SW
0)
r
e
qu
i
E
i
ght
s
w
i
t
c
he
s
m
ber. I
n
ot
he
r
A
2)
, an
exp
a
n
o
di
s
p
l
a
y
e
d i
n
c
tion
fo
r
H
a
r
d
w
2
N
0
N
1
W
7 to
SW4
W
3 to SW
0
,
D7, C8 /
Pin 5 t
2
n
3
boa
r
d
. T
h
n
put
X
an
d G
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pplicati
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.
Algazi,
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.C. W
u
, A
l
.
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. 3
,
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.
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her, H
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B
ouridane, P.
n
cipl
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r
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eirut, Lebanon
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ouridane, P.
M
i
ng
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Proc. of
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ouridane, P.
M
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ng
,
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coustics,
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.
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Ro
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ified Algorith
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stola
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and Related
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H
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t
ment of the F
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.
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plem
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a
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chit
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h
IEEE Intern
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la
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ovel F
P
G
m
age, and Sign
a
.
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ula, an F
P
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S
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g
nal Proce
s
UT, 2001,
pp
.
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to
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LSI)
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rt
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alyze
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p
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ar
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P
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for Sci
e
Technology,
y
, Ministry o
f
5/
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Logic and It
s
2
008
F
unctions with
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n Lt
d
, London
,
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st Wa
lsh-Ha
d
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tation
of discr
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n
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tion
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l
Confere
G
A Im
plementa
t
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l Processing, 2
G
A im
plem
ent
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s
sing
, 2001.
P
1105-
1108 vol
.
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hFunctio
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n Vision, Ima
g
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sed on
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, Feb 17, 20
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s
,
Tran
saction
transfor
ms usi
n
o
l. 46
, n
o
. 5. p
p
a
ns
fo
r
m
us
in
g
D
o
nics
, Circuit
&
H
adama
r
d Tra
n
-
Hadamard tra
n
I
CASSP '
01)
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2
if
ferent Orderi
n
P
rocessing, 20
0
H
T for Signal
P
6–295
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(Zu
lfika
r
)
2
695
=
4;
=
-10
(
d
ec)
b
een
do
ne
d
us
i
ng
an
f
ha
r
d
wa
re
t
ho
ugh
th
e
l
i
zat
i
on o
f
I
nn
ov
ation
i
a, Awa
rd
n
d Hi
g
h
er
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n
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cy
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o
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istributed
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st
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r
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001 IEEE
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P
roce
ssing”,
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BIOGRAP
HI
ES OF
AUTH
ORS
Z
u
lfikar,
he was born in Beureunuen, Aceh
, Indonesia,
in 1975.
He receiv
e
d his B.Sc. degr
ee in
Electrical Engin
eering
from North Sumatera Univ
ersity
, M
e
dan, I
ndonesia, the M. Sc. Degr
ee
in
Electrical Engin
eering from Kin
g
Saud Univer
sity
, Riy
a
dh, Sau
d
i Arabia, in 19
99 and 2011,
res
p
ect
ivel
y.
He joined as
t
each
ing s
t
aff i
n
the Departm
e
nt of Ele
c
tron
ics
at P
o
lit
ekni
k Caltex Ri
au,
Pekanbaru, Indo
nesia in
2003.
He served
as head
of Industrial
Control Laborator
y
,
Politekni
k
Caltex Riau fro
m 2003 to 2006.
In 2006, he join
ed
the Electrical
Engineering Dep
a
rtment, S
y
iah
Kuala Universi
t
y
. H
e
has been
a
ppointed
as head
of Digital
Labor
ator
y
for two su
ccessive
y
e
ars.
His c
u
rre
nt re
searc
h
inte
re
sts include
VL
SI d
e
sign
and S
y
stem on
Chips (SoC).
Shuja A.
Abba
si,
he was born
at Amroha, In
dia
in 1950
. He obtained
the d
e
grees of
B.Sc.
Engineering and
M.Sc. Engineering in Electr
ical Engineering in
1970 and 1972 respectiv
ely
from
Aligarh M
u
slim
Universit
y
(AMU), Aligar
h,
Indi
a with
the
first posit
ion in
the Univ
ersit
y
.
He didPh.D. fro
m University
of
Southampt
on, England
in 1980
in
Microelectronics.
He joined as Assistant Professor in the Departm
e
nt of Ele
c
tri
c
a
l
Engine
ering at
Aligarh Muslim
University
, Alig
arh, India in 19
71, was promot
ed to the positions of Associate Professor and
Professor in 1982 and 1986 r
e
spectively
.
He shif
ted to
the newly
cr
eated
Department of
Electronics Engineering
at AMU as Professor in
1988. He served
as Chairman, D
e
partment of
Electronics Engineer
ing, AMU
from 1996 to
1
999.
He held man
y
Academic/Administrativ
e
positions in
the
past at AMU and outside. He
jo
in
ed as
P
r
of
es
s
o
r of El
ec
tronics Engineering at
College of
Engineering
,
King Saud University
,
Ri
y
a
dh, Saudi A
r
abia in 1999 an
d is continuing
there since th
en
. He h
a
s more
than 100
resear
ch
publications
to his
cred
it so far. He h
a
s
completed man
y
client funded pr
ojects from various organization
s
. His current in
terests in
clud
e
VLSI design
and
technolog
y
.
Evaluation Warning : The document was created with Spire.PDF for Python.
I
J
ECE
I
S
SN
:
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8-8
7
0
8
FPGA Ha
rd
ware Rea
liza
tio
n: Add
itio
n o
f
Two
Di
g
ita
l
S
i
gn
a
l
s Based on
Wa
lsh Tra
n
sforms (Zu
lfika
r
)
2
697
Abd
u
lrahman A.
Alamoud,
he was born in
Onaizah
, Saudi
Arabia on Sept. 21, 1946. He
earned his B.Sc. degree in Electrical Eng
i
neer
ing, Colleg
e
of
Engineer
ing (COE) from th
e
Univers
i
t
y
of Ri
yadh (r
enam
ed l
a
ter as
KS
U). He earned his
M
.
S
c
., in M
i
cro
e
le
ctroni
cs
, and
Ph.D., in photovoltaic solar cells, from
West Vir
g
inia University
,
Morgantown, W.V., USA in
1974 and 1984 r
e
spectively
.
In J
une 1984, h
e
jo
ined
the Department of Electr
i
cal Eng
i
neering,
KSU and was p
r
omoted to the r
a
nk of Professor in 1999. In 199
1 he took a one
y
e
ar leave of
abs
e
nce
from
KS
U and joined t
h
e Advanc
ed El
ectron
i
cs
Com
p
an
y
AEC)
, Ri
ya
d
h
, S
a
udi Arab
ia
as the Special Projects Director
. In1992 he was
appointed as Director
, Resear
ch Center
, COE,
KSU for a two
t
e
rm
period
in Ju
ne 1996. In
the
acad
em
ic
y
e
ar
June 1996- Sep
t
1997 he was
a
Vis
iting Res
ear
ch As
s
o
ciate P
r
ofes
s
o
r,Nation
a
l Renewab
l
e Energ
y
Labor
at
or
y, Golden,
Colorado, USA (July
15-Dec.15
,
97) where he w
o
rked on the development of th
in films CdTe
Solar Cells and
characterization
of
materials (such as semiconducto
rs thin films and Saudi white
s
a
nd rocks
)
and
a Vis
iting Res
e
a
r
ch As
s
o
ciate P
r
ofes
s
o
r, VLS
I
Res
earch Group
,
Department of
Ele
c
tri
cal
and
C
o
m
puter Engin
e
ering,
Univers
i
ty
of
Water
l
oo,
Waterl
oo, ON,
Canada. Worked
on the design of VLSI circuits using Cadence (M
ar.9-Aug.22
, 97)
. He was chosen to be the Vice
Dean for Administrativ
e Affair
s, COE, KSU dur
ing the per
i
od
of June 1999-
June 2005. His
res
earch in
ter
e
s
t
s
are in both m
i
croele
ctroni
cs
, Solar Cells and Materials, and Photovoltai
c
S
y
ste
m
s.
Evaluation Warning : The document was created with Spire.PDF for Python.