TELKOM
NIKA Indonesia
n
Journal of
Electrical En
gineering
Vol.12, No.7, July 201
4, pp
. 5197 ~ 52
0
3
DOI: 10.115
9
1
/telkomni
ka.
v
12i7.553
9
5197
Re
cei
v
ed
De
cem
ber 3
1
, 2013; Re
vi
sed
F
ebruary 28,
2014; Accept
ed March 2
0
, 2014
Design of 3-Bit ADC in 0.18µm CMOS Process
Mohammad
Marufuzzam
an*, Sy
ar
izal Z. Abidin, M
a
mun Bin Ibne Rea
z
, Lab
onnah Far
z
a
n
a
Rahm
an
Dep
a
rtment of Electrical, El
ec
tronic an
d S
y
st
ems Engi
ne
eri
ng,
F
a
cult
y
of Engi
neer
ing a
nd Bu
ilt Enviro
nment
Univers
i
ti Keb
a
ngsa
an Mal
a
ys
ia, 436
00 Ba
ng
i, Selan
gor, Ma
la
ysia
*Corres
p
o
ndi
n
g
author, e-ma
i
l
: marufsust@g
m
ail.com
A
b
st
r
a
ct
Anal
og-to-d
ig
ital co
nverters (
A
DCs) are r
e
q
u
ire
d
to conv
e
r
t the real w
o
r
l
d a
nal
og si
gn
als int
o
digit
a
l s
i
gn
als,
as d
i
gita
l si
gn
als
are
more r
obust
an
d
e
a
si
er
to han
dl
e. Sign
al proc
ess
i
ng
is incre
a
si
ngl
y
bei
ng
do
ne
in
t
he
dig
i
tal
d
o
m
ain
al
on
g w
i
th
the esc
a
l
a
ting
l
e
vels
of
integr
ation
h
a
ve f
o
rc
ed A
DC t
o
res
i
de
on the s
a
me c
h
ip as
di
gital c
i
rcuits. T
he stu
d
y de
scri
bes t
he d
e
sig
n
met
hod
of 3-bit A
DC usi
ng CE
D
E
C
0.18
μ
m CMO
S
process. T
h
e des
ign
ed A
DC co
nsists of
; voltage
div
i
d
e
r, compar
ator
and
7-bit
enc
ode
r
circuits. T
he
pr
e-si
mul
a
tio
n
h
a
s
do
ne w
i
th E
L
DO si
mul
a
tor
w
i
th low
pow
er
sup
p
ly v
o
ltag
e
(VDD)
1.8 V.
T
he
simulat
ed resu
l
t
s show
ed that the desi
g
n
ed 3
-
bit ADC is ab
l
e
to convert an
alo
g
sign
als to
digit
a
l sig
nals.
Ke
y
w
ords
:
C
M
OS, ADC, vo
mp
arator, enc
o
der, voltag
e div
i
der
Copy
right
©
2014 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
The trend to
ward in
crea
sed integ
r
atio
n of
an
alog
and
di
gital ci
rcuit
r
y
re
quires data
conve
r
ters th
at ca
n b
e
e
m
bedd
ed i
n
l
a
rge
digital
ICs [1-8]. Mix
ed-sign
al a
p
p
lication
s
su
ch
as
Partial Re
sp
o
n
se Maxim
u
m-Li
kelih
ood
(PRML
)
re
ad
cha
nnel
s an
d
gigabit Ethernet requi
re hi
gh
-
spe
ed lo
w-re
solutio
n
ADCs, which a
r
e
usu
a
lly
imple
m
ented
with
the flash a
r
chitecture. Th
ese
appli
c
ation
s
rely
h
eavily on DSP,
wh
ich pe
rfor
m
s
be
st
when
implem
ente
d
on
the
fin
e
st
geomet
ry CM
OS process [
9
-15].
On
th
e
othe
r h
and,
ADCs
with a
nalog
ci
rcuits in g
ene
ral, t
end
to
fu
n
c
tion
be
s
t
w
h
en
fa
br
ic
a
t
ed
on
mo
r
e
ma
tu
re
C
M
O
S
p
r
oc
es
s
.
C
M
O
S
ba
s
e
d
ADCs
a
r
e
utilized in a n
u
mbe
r
of appl
ication
s
a
s
the sou
r
ce
s of
store d
a
ta in RFID a
pplication [16-2
3
].
An Analog to
Digital Conve
r
ter (A
DC), whic
h
conve
r
ts the analog
si
gnal to digital
output,
is compo
s
e
d
of three diffe
rent stag
es th
at con
s
i
s
t of voltage divid
e
r, co
mpa
r
at
or an
d en
co
d
e
r.
Comp
arators are the
ke
y analog b
u
i
l
ding blo
c
k
of any flash
ADC a
nd
strongly influe
nce
perfo
rman
ce.
A hig
h
d
e
g
r
ee of
compa
r
ator
accu
ra
cy is
esse
ntial
for
goo
d A
D
C p
e
rfo
r
ma
n
c
e
.
Ho
wever, int
egratio
n of analo
g
circui
try in low voltage scal
e
VLSI technologie
s
re
sul
t
s in
degrade
d pre
c
isi
on due to large d
e
vice
mismat
ch an
d limited voltage swing. Redu
ced p
r
e
c
isio
n
can be comp
ensated
for offset
co
rrect
i
on
sch
e
me
s. Analog offset corre
c
tion
techni
que
s
are
typically u
s
e
d
, but th
ese
sche
me
s a
r
e in
crea
singl
y difficult to
impleme
n
t in
mod
e
rn
CM
OS
pro
c
e
s
ses. T
herefo
r
e, the
issue of co
m
parato
r
offset
is becomin
g a bottlene
ck i
n
the desi
gn
of
flash ADCs [2
5-29].
This
study prese
n
ts an im
proved
3-bit
s
ADC ci
rcuit, which is d
e
signed u
s
in
g CEDE
C
0.18
μ
m
CM
OS pro
c
e
s
s. The d
e
si
gn
ed ADC
circui
t has th
re
e
sub
ci
rcuits;
voltage divi
der,
comp
arator
a
nd the e
n
cod
e
r
circuit. Thi
s
pa
pe
r is
organi
zed with the
archite
c
tu
re
of
the 3-bi
ts
ADC
circuit.
Then, the
de
sign
metho
d
o
l
ogy of the
compa
r
ator,
e
n
co
der ci
rcuits a
r
e
pre
s
e
n
ted.
After that, the s
i
mulated res
u
lts
,
th
e
co
mpari
s
o
n
stu
d
y amon
g ot
her de
sign
ed
ADC
circuits and
con
c
lu
sio
n
s a
r
e given, re
sp
ectively.
2. Architectu
r
e
A typical flash ADC blo
c
k
diagram i
s
sh
own i
n
Fig
u
re
1. The i
nput
sign
al is com
pare
d
to
the 2
n
node
s of resi
stor a
nd the
sampl
ed in
put valu
e is de
co
ded
into bi
na
ry code. T
here a
r
e
many differe
n
t
types of architectures, e
a
c
h
with
uni
qu
e ch
ara
c
te
rist
ics
and
different limitation
s
.
Flash A
D
Cs,
also
kn
own a
s
pa
rallel A
D
Cs, a
r
e th
e fa
stest
way to
conve
r
t an a
nalog
sig
nal t
o
a
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 7, July 201
4: 5197 – 52
03
5198
digital sign
al
[25]. Flash ADCs a
r
e
ideal for
ap
plicatio
ns re
quirin
g
very large b
a
nd
wi
dth
;
however, the
y
typically co
nsum
e m
o
re
power th
an
o
t
her A
D
C architectures an
d are g
ene
ral
l
y
limited to 8-bi
ts re
solution [
30-3
1
].
Figure 1. Block
Diag
ram o
f
3-bit Flash
ADC
As sh
own in
Figure 1 the f
l
ash A
DC i
s
comp
osed of
three maj
o
r
compon
ents: resi
stors
string,
comp
arato
r
s an
d
encode
r. Th
e
anal
og
input
voltage
is concurrently
compa
r
ed
to t
he
referen
c
e volt
age level
s
provided by th
e
re
sisto
r
n
e
twork st
ring. T
h
e compa
r
ison
maximize
s t
h
e
spe
ed of the
conve
r
si
on
of the ADC
circuit. Th
e ou
tputs of com
parat
o
r
s are
encode
d by the
encode
r blo
c
k, whi
c
h i
s
a com
b
inatio
n of a se
rie
s
of ze
ro
s a
n
d a serie
s
of ones, e.g
.
,
000...011...111. Because
bi
nary code i
s
usually needed
for di
gital
signal pr
ocessing, an encoder
cod
e
is then
transfo
rme
d
to a binary co
de throu
gh
a
n
enco
d
e
r
, to get the desired 3-bit
s
bin
a
ry
numbe
r for the ADC. The
cost of su
ch
a traditi
onal
encod
er in
creased expon
entially with the
resolution.
O
p
timization
s
on a
r
ea
cost
, circuit late
n
c
ie
s a
nd
po
wer con
s
um
p
t
ions
are
g
r
e
a
tly
expecte
d. In this re
se
arch,
low po
we
r co
mparator
ci
rcuit is desi
gne
d to minimize
the cost [32].
3. Methodol
og
y
As mention
e
d
earli
er, in o
r
de
r to de
sig
n
t
he co
mpon
ents of the 3
-
bit ADC, CE
DEC 0.1
8
μ
m pro
c
e
s
s
have be
en
u
s
ed
to de
sig
n
the
circui
t
diagram a
n
d
the layout
of all the th
ree
comp
one
nts
of the ADC circuit. Figu
re
2 sho
w
s t
he
schemati
c di
agra
m
of 3-bi
t ADC ci
rcuit. In
the sche
mati
c dia
g
ram a
s
sho
w
n
in Fi
gure
2 it i
s
cl
ear th
at 3-bits ADC
circuit
is
comp
osed
of
voltage divide
r circuit, co
m
parato
r
blo
c
k and the en
co
der ci
rcuit.
Figure 2. Sch
e
matic Di
ag
ram of 3-bits
ADC Ci
rcuit
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of 3-B
i
t ADC in 0.18
µ
m
CMOS Process (M
o
ham
m
ad Marufuzzam
an)
5199
The ci
rcuit diagra
m
of the voltage divider by
usin
g 8
resi
stors, wh
ich serially co
nne
cted
is
sho
w
n i
n
Fi
gure
2
.
Ea
ch
resi
sto
r
value
ca
n be
obtai
ned
by ma
kin
g
re
si
stor
R1
at 750
Ω
, R2 t
o
R7 at 500
Ω
a
nd R8 at 25
0
Ω
with Vdd at
1.8V.
All the outputs of the voltage divider
circuit
are
com
p
are
d
with th
e comp
arator circuit
diagram a
s
shown in Figu
re 3.
Two out
puts fro
m
ea
ch voltage
di
vider ci
rcuit a
r
e taken a
s
the
input si
gnal
s for ea
ch
co
mparator
circuit to
pro
d
u
c
e one
-
bit o
u
t
put sign
al. To de
sign
th
e
comparator
circuit as shown i
n
Figure 3 curr
ent
mirror method has
been utilized. In
the
comp
arator
stage, an
ope
rational a
m
plif
ier h
a
s be
en
use
d
a
s
com
parato
r
. To
d
e
sig
n
a
co
mp
lex
comp
arator 3
pMOS and 5
nMOS are re
quire
d.
To de
sig
n
3
-
bit ADC ci
rcui
t as
sh
own in
Figu
re
2,
7
compa
r
ators h
a
ve
be
en req
u
ired
to
prod
uce 7 o
u
t
put bits. All the 7-bits o
u
tput is ta
ken
as the i
nput
s for the 7
-
bits encode
r ci
rcuit,
whi
c
h eventu
a
lly produ
ce t
he 3-bit
s
ADC sig
nal
s.
For the conve
n
i
ence, the thre
e sub
circuits
are
desi
gne
d an
d simul
a
ted
sep
a
rately. F
i
nally, all
the three
comp
onent
s are combine
d
tog
e
ther
and teste
d
at physi
cal de
scription le
vel b
a
se
d on avail
able CE
DEC
0.18
μ
m CM
O
S
process.
The output
s of the compa
r
ator
circuit is re
q
u
ired to
use a
s
the inputs of the
encode
r
circuit, whi
c
h
is al
so d
r
a
w
n
usin
g CE
DE
C 0.18
μ
m
CMOS process DA tools a
s
sho
w
n i
n
Fig
u
re
4. To de
sign t
he en
cod
e
r
ci
rcuit, “CEDE
C
sta
nda
rd
cells” l
ogi
c gat
es a
r
e utili
ze
d. All the outputs
of the
comp
a
r
ator ci
rcuit i
s
u
s
e
d
a
s
th
e 7 i
nput
s for the d
e
si
gnin
g
of the
en
co
der
ci
rcuit u
s
i
ng
five inv01a and seve
n nan
d02a lo
gic g
a
t
es.
Figure 3. Sch
e
matic Di
ag
ram of Comp
a
r
ator
Circ
uit for 3-bits
ADC
Figure 4. Selected L
o
gi
c Gates fo
r 7-bi
ts
Enc
o
der Stage
4. Results a
nd Analy
s
is
The Th
e ADC ci
rcuit is d
e
sig
ned in
CEDEC 0.1
8
-
μ
m CMOS
pro
c
e
ss. T
he en
han
c
e
d
ADC
circuit h
a
s b
een ve
rified by u
s
ing t
he ELDONE
T
simulato
r of t
he CE
DEC
proce
s
s. Figu
re
5
sho
w
s the si
mulated outp
u
t result
s for the com
p
a
r
ato
r
circuit.
Figure 5. Simulation re
sult
s for the com
parato
r
ci
rcuit
Evaluation Warning : The document was created with Spire.PDF for Python.
ISSN: 23
02-4
046
TELKOM
NI
KA
Vol. 12, No. 7, July 201
4: 5197 – 52
03
5200
In the coding
stage for 3-b
i
t ADC, the circ
uit de
sig
n
and MOS layout should
con
s
ist of
simple lo
gic
circuit
with 7 inputs a
nd 3
outputs
a
c
co
rding to the o
u
tput equatio
n of O1, O2
and
O3 from the truth table a
s
sho
w
n in Ta
b
l
e 1.
Table 1. Input
and output of
enco
der
Inpu
t
OUT1
0 0
0 0 0 0 0 1
OUT
2
0 0
0 0 0 0 1 1
OUT
3
0 0
0 0 0 1 1 1
OUT
4
0 0
0 0 1 1 1 1
OUT
5
0 0
0 1 1 1 1 1
OUT
6
0 0
1 1 1 1 1 1
OUT
7
0 1
1 1 1 1 1 1
O1
0 0
0 0 1 1 1 1
O2
0 0
1 1 0 0 1 1
O3
0 1
0 1 0 1 0 1
After desig
ning all three
stage
s of the 3-bi
ts ADC, all the diffe
rent co
mpon
ents are
simulate
d an
d verified. Fi
nally, all the three
comp
o
n
ents a
r
e
co
mbined to fo
rm a 3-bits A
DC
circuit, which
is
simulate
d
and ve
rified
again to
get
t
he de
si
red
o
u
tput sig
nal
s
as illu
strated
i
n
Figure 6.
Figure 6. Simulated Outp
ut Results fo
r t
he Test of 3-bits ADC
Circuit
Figure 7. Layout Diag
ram
of Compa
r
ato
r
Circuit
Evaluation Warning : The document was created with Spire.PDF for Python.
TELKOM
NIKA
ISSN:
2302-4
046
De
sign of 3-B
i
t ADC in 0.18
µ
m
CMOS
Process (M
o
ham
m
ad Marufuzzam
an)
5201
The layo
ut di
agra
m
for th
e co
mpa
r
ato
r
circuit i
s
sho
w
n in
Figu
re
7. After su
ccessfully
desi
gn th
e
schematic dia
g
ram of
com
parator
circ
uit, th
e de
sig
n
h
a
s
been
sim
u
lat
ed a
nd
with t
he
su
ccessful si
mulation resu
lt, the design
ed is prepa
re
d for the layo
ut diagra
m
, which i
s
sh
own
in
Figure 7.
It is found that, with the powe
r
supply
vo
ltage 1.8V and the inp
u
t analog
sign
als a
s
V
(IN) the
com
parato
r
i
s
su
ccessfully p
r
odu
ce th
e
outp
u
t
r
e
s
u
lts
as
V (O
UT
)
,
wh
ic
h is sh
own
in
Figure 5.
It is observed
that the resu
lts meet the require
me
nt of the truth tab
l
e indicate
d in Table
1. The input value of the O
U
T4 is
sam
e
for the output
O1.
The si
mulatio
n
re
sult in Fi
gure
6 sho
w
s that a pro
p
e
r
co
nversion i
s
ha
ppen
ed
with the
analo
g
input
signal to digital output signal. It is
o
b
se
rved that
the signal is interp
reted
well
begin
n
ing f
r
o
m
the ea
rly
stage to
the
final st
ag
e a
nd the
outpu
t obeyed th
e
theoretical t
r
uth
table of 3-bits ADC.
Flash a
nalo
g
-to-digital con
v
erters, also
kno
w
n a
s
pa
rallel ADCs, a
r
e the faste
s
t way to
conve
r
t an
a
nalog
sig
n
to
a digital
si
gn
al. Flash
ADCs are id
eal
for ap
plicatio
ns
req
u
irin
g
very
large b
and
wi
dth; howeve
r
, they typicall
y cons
ume
more p
o
wer
than other A
DC a
r
chitect
u
re
s
and are gen
e
r
ally limited to 8-bits
re
sol
u
tion [32
]. To achieve lo
w-power con
s
u
m
ption with h
i
gh
conve
r
si
on
-speed a
nd to
enhan
ce d
e
s
ign
reu
s
abili
ty
in terms o
f
digital implementation
with
more
re
gula
r
mask p
a
tterns, the time
-domain
co
m
pari
s
on
is
de
vised in th
e
flash A
DC. T
h
e
prototype, wh
ich ha
s be
en
fabr
icated in
a stand
ard 0.
18 um CM
OS technol
ogy, achi
eves a F
O
M
of 0.91p
J/co
n
v
. Although n
o
low-po
we
r
digital ci
rcuit tech
niqu
e ha
s been
com
p
ri
sed, furth
e
r lo
w
-
power op
eration ca
n be e
a
sily ac
hieve
d
by voltage scaling o
r
re
ductio
n
tech
n
i
que
s of leakage
power. Ta
ble
2 provid
es t
he pe
rform
a
n
c
e a
nalys
i
s
a
nd the
comp
arison
study
of the differe
nt
ADC ci
r
c
uits.
Table 2. Perf
orma
nce Co
mpari
s
o
n
Parameters
This
stud
y
[28]
[31]
[32]
Technolog
y
(CM
O
S)
0.18
m
0.18
m
0.18
m
0.13
m
Resolution 3-bit
5-bit
8-bit
6-bit
Architecture Flash
Time-Dom
ain
Flash
SAR - Flash
F
lash
Suppl
y
voltage
1.5 V
1.8 V
1.2 V
1.5V
Power consumpti
on
36.327 mW
8mW
166 nW
160 mW
Chip area
1.044 mm²
0.132 mm²
0.132 mm²
0.12 mm²
4. Conclusio
n
In this re
sea
r
ch, de
sign
of 3-bits A
DC
usin
g CE
DEC 0.18
μ
m pro
c
ess
is
de
sc
r
i
be
d
to
conve
r
t the analog inp
u
t si
gnal to digital
output si
gnal
. Moreover, 3
-
bits flash ADC archite
c
ture
with lo
w ha
rd
ware
com
p
le
xity and lo
w
latency i
s
propo
sed. All
the th
ree
sub
ci
rcuits; volt
age
divider, com
parato
r
an
d
encode
r hav
e been
de
si
gned
su
ccessfully to co
m
p
ly with the
ADC
c
i
rc
uit. However, this 3-bits
flas
h type
ADCs
have
li
mitations
su
ch a
s
the
devi
c
e i
s
accu
rat
e
for
the conve
r
si
o
n
of analog voltage to digital form
from 0 to 3 voltage in amplitude and for a
c
curate
result the inp
u
t voltage sh
ould be g
r
eat
er or le
ss
er t
han the refe
rence voltage of the compa
r
ator
about
±0.05
volt. Moreov
er, thi
s
a
r
chi
t
ecture
can
be exten
ded
to me
dium-t
o-hig
h
re
solu
tion
appli
c
ation
s
b
e
ca
use this si
mplicity of the circuit.
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046
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