Indonesian J
ournal of Ele
c
trical Engin
eering and
Computer Sci
e
nce
Vol. 2, No. 2,
May 2016, pp
. 259 ~ 267
DOI: 10.115
9
1
/ijeecs.v2.i2.pp25
9-2
6
7
259
Re
cei
v
ed Fe
brua
ry 10, 20
16; Re
vised
April 6, 2016;
Accept
ed Ap
ril 18, 2016
Capacitor Voltage Balancing of Five Level Dio
d
e
Clamped Converter based STATCOM
D. Sindhuja, V
1
. Yu
v
a
raju
M.E.
2
Dep
a
rtment of Electrical
and
Electron
ics En
gin
eeri
n
g
K.S Rangas
am
y Co
lle
ge of T
e
chno
log
y
T
i
ruchengo
de, India
*Corres
p
o
ndi
n
g
author, e-ma
i
l
:
1
sindh
ujas
iet
@
gmai
l.com,
2
y
u
va
ng
sp
m@gma
i
l
.
co
m
A
b
st
r
a
ct
T
he pow
er q
u
a
lity d
e
ter
m
in
e
s
the fitness o
f
the
electric
al
pow
er to the
consu
m
er dev
i
c
es. T
o
improve
the
qu
ality of th
e p
o
w
e
r de
liver
ed
many co
mpe
n
sat
i
ng
devic
es ar
e
used. T
h
e F
A
CT
S devic
es a
r
e
nor
mal
l
y
used
t
o
re
duce
the
p
o
w
e
r qu
ality
pr
obl
e
m
s by
in
du
cing
on
e
or
mo
re AC
trans
mis
s
ion
par
a
m
eter
s.
T
he
static syn
chron
ous co
mpens
ator
(ST
A
T
C
OM) can ac
t as either a
source or si
nk of reactive
AC
pow
er
to an e
l
ectricity netw
o
rk. T
he basic e
l
ectronic
blo
ck
of the ST
AT
COM is the
voltage-source inverter
that converts a
n
inp
u
t dc volt
a
ge int
o
a thre
e-
phas
e outp
u
t voltag
e.
T
he ST
AT
COM emp
l
o
ys an inv
e
rter i
n
order to o
b
tain
the voltag
e source of a
d
jus
t
abl
e
ma
gn
itud
e and
phas
e from th
e DC li
nk voltag
e on
t
h
e
capac
itor.
In this mode
l, the
ST
AT
COM is desig
ned w
i
th
the five level
dio
de cla
m
ped
converter (DC
C
)
controlled by s
pace vector pulse width modulation
(SVPWM) technique. The spac
e vec
t
or technique
with
α
,
β
frame
is referred
here.
T
he dc li
nk ca
pacitor v
o
ltag
e
equ
ali
z
at
io
n for the five l
e
v
e
l di
od
e cla
m
p
e
d
converter w
a
s expl
ain
ed. The
Total Harmon
i
c Distortion
of the sourc
e
curr
ent w
ill be con
s
ider
ably re
duc
ed.
Ke
y
w
ords
:
Di
ode cl
a
m
pe
d c
onverter, spac
e vector puls
e
w
i
dth mo
dul
ati
on, T
o
tal Har
m
onic Dist
o
rtion
Copy
right
©
2016 In
stitu
t
e o
f
Ad
van
ced
En
g
i
n
eerin
g and
Scien
ce. All
rig
h
t
s reser
ve
d
.
1. Introduc
tion
The A
C
p
o
wer tran
smissi
on lin
e o
pera
t
ion is
ge
nerally co
nstrain
ed
by limitati
on of
one
or mo
re n
e
twork
pa
ramete
rs
whi
c
h in
cl
ude
s
line im
peda
nce and
operating va
riable
s
su
ch
as
voltages a
n
d
current
s. As a result, the po
we
r lin
e is un
able
to dire
ct po
wer flo
w
am
ong
gene
rating
st
ations. Th
ere
f
ore the tran
smissio
n
sy
stem ha
s to b
e
ca
pable
of transmitting
the
power
gen
erated
with m
a
ximum efficie
n
cy. Th
e maj
o
r
pro
b
lem
is with th
e q
u
a
lity of the po
we
r
transmitted.
The p
o
wer q
uality depe
nd
s u
pon
vari
o
u
s fa
ctors
su
ch
as voltag
e, frequ
en
cy
and
pha
se. Flexi
b
le AC T
r
an
smissio
n
System (FA
C
TS) is th
e te
chn
o
logy; its
pri
n
cip
a
l role i
s
to
enha
nce po
wer tra
n
sfe
r
ca
pability and
controlla
bility
in AC p
o
wer
system. A
sta
t
ic syn
c
h
r
on
o
u
s
comp
en
sato
r (STATCOM
) is a re
gul
ating devic
e
used o
n
a
l
ternating
cu
rre
nt electri
c
ity
transmissio
n
netwo
rks. It can a
c
t as
eith
er a
so
urce o
r
si
nk
of rea
c
t
i
ve AC po
we
r to an ele
c
tri
c
ity
netwo
rk. It ca
n be used for
power qu
ality improveme
n
t.
The m
u
ltileve
l inverte
r
s ha
ve drawn tre
m
endo
us
int
e
re
st in
the
power indu
st
ry. They
provide
a n
e
w
set of feat
ure
s
that a
r
e
well
suit
ed fo
r u
s
e in
rea
c
t
i
ve power
co
mpen
sation.
The
concept of Multilevel Inverters
(MLI)
does not limit
on just two lev
e
ls of voltag
e
to create an
AC
sign
al. Instea
d seve
ral vol
t
age level
s
a
r
e ad
ded to
each othe
r in
orde
r to
cre
a
te a sm
ooth
e
r
stepp
ed
wav
e
form, with l
o
we
r dv/dt a
nd lo
wer
ha
rmonic
disto
r
ti
ons.
With th
e more volta
g
e
levels, the
waveform it
creates be
com
e
s
sm
oothe
r, but
with m
a
ny levels the
de
sign
be
co
mes
more
compli
cated, with mo
re co
mpo
nent
s and
compli
cated co
ntrolle
r for the inverter is nee
ded.
The STATCOM with Di
ode Cl
ampe
d multilevel
Conve
r
ter
usin
g Spa
c
e
Vector
Modulatio
n is pro
posed
an
d it can
be
used to im
p
r
ove
the quality of
the po
we
r d
e
livered. Sp
a
c
e
vector mo
dul
ation is a PWM control alg
o
rithm for
multi-phase mult
i level inverters, in whi
c
h t
he
referen
c
e sig
nal is sa
mpl
ed reg
u
larly;
after
each
sampl
e
, non-zero active switchi
ng vect
ors
adja
c
ent to the reference vector a
nd on
e or more
of the zero switchin
g vectors are sel
e
cte
d
for
the appropri
a
te fraction of the sam
p
ling
perio
d in or
d
e
r to synthe
si
ze the refe
re
nce
signal a
s
the
averag
e of t
he u
s
ed
vect
ors.SVM i
s
a
digital mo
du
lation techniq
ue whe
r
e the
obje
c
tive is
to
gene
rate PWM load line voltage
s that are in aver
ag
e equal to a given or refe
ren
c
e loa
d
line
voltages. T
h
i
s
i
s
do
ne in
each sampli
n
g
pe
riod
by
prop
erly
sele
cting the
swit
ch
state
s
of t
h
e
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ISSN: 25
02-4
752
IJEECS
Vol.
2, No. 2, May 2016 : 259 –
267
260
inverter a
nd the cal
c
ul
atio
n of the appropriate ti
me
perio
d for ea
ch state. Th
e
sele
ction of
the
states an
d th
eir time
pe
rio
d
s
are
a
c
co
mplish
ed
by the
spa
c
e
vector tra
n
sfo
r
m
a
tion. Capa
ci
tor
voltage bala
n
cin
g
with p
a
ssive front
end
s is
sho
w
n in [1], [6] and [8]. Th
e sin
u
soi
dal
PWM
method fo
r
DCM
C i
s
giv
en in [9]. Fa
st optimum
predi
ctive
co
ntrol for bip
o
l
ar b
a
ck to
b
a
ck
conve
r
ter
ca
n be seen i
n
[2]. In [4]
the ca
pa
citor v
o
ltage bal
an
cing is d
one
with the hel
p
o
f
curre
n
t flow model. A elliptical refe
ren
c
e frame sp
a
c
e vector mo
d
u
lation is p
r
o
posed he
re fo
r the
balan
cing of f
i
ve level Diod
e clamp
ed co
nverter.
2. Multile
v
e
l
SVPWM for
DCMC based STATCOM
The m
u
ltilevel converte
r
can
be
conn
ected
to the
po
wer
syste
m
for
re
activ
e
po
we
r
comp
en
satio
n
. The
loa
d
side
is conn
ected
to th
e
ac
supply
a
nd the
d
c
si
de i
s
o
pen,
not
con
n
e
c
ted to any dc voltag
e. For the co
ntrol of
rea
c
ti
ve powe
r
flow, the inverte
r
gate co
ntrol
is
pha
se
shifted
by 18
0
˚
. Th
e
dc si
de
cap
a
c
itors a
c
t a
s
a loa
d
. When
a multilevel
conve
r
ter dra
w
s
pure
rea
c
tive power, the ph
as
e voltag
e a
nd cu
rrent are 90
˚
a
part, a
nd the ca
pa
ci
tor ch
arg
e
an
d
discha
rge
ca
n be bala
n
ce
d.
2.1. Space Vector M
odul
ation
Space Ve
cto
r
Modulation
became a
standa
rd
for th
e swit
chin
g p
o
we
r convert
e
rs. Any
three
-
ph
ase system (d
efined by
a
x
(t), a
y
(t) a
z
(t))
can b
e
represented
uniqu
e
l
y by a rotating
vec
t
or
a
S
:
a
s
=
2
/3[a
x
(t)+
a
.
a
y
(t)+a
2
.a
z
(t)]
(1)
whe
r
e,
a
=e
j2
π
/3
and
a
2
= e
j4
π
/3
.
Given a th
re
e-ph
ase
syst
em, the ve
ctorial
re
p
r
e
s
e
n
tation i
s
a
c
h
i
eved by the
followin
g
3/2 tran
sform
a
tion:
2
3
1
1
2
1
2
0
√
3
2
√
3
2
(2)
whe
r
e (
A
α
,
A
β
) are formin
g an ortho
g
o
nal 2-p
h
a
s
e system and
a
S
=
A
α
+
j
.
A
β
.
A vector ca
n be
uniqu
ely defi
ned i
n
the
co
mplex pla
ne
by these
com
pone
nts.
a
x
–
ca
n b
e
a vol
t
age, current
or
flux and doe
s not ne
ce
ssarily ha
s to
be sinu
soi
d
al. It results an uniqu
e corre
s
p
ond
en
ce
betwe
en a Sp
ace Ve
ctor in
the compl
e
x plane a
nd a three
-
p
h
a
s
e system. The m
a
in advanta
g
e
s
of this mathe
m
atical repre
s
entatio
n are:
Analysis of th
ree
-
ph
ase sy
stem
s as
a
whole in
stead
of lookin
g at each pha
se;
It allows u
s
in
g the pro
pert
i
es of the
vec
t
orial
rotation. Us
ing rotation with
t
lead
s to an
analysi
s
in DC com
pon
ent
s by withdrawing the rotatio
nal effect.
2.2. SVPWM for Fiv
e
Le
vel DCMC
Diod
e-Clamp
ed
Multilevel Conve
r
ters (DCM
Cs
) are one kind
of multilevel
con
v
erter
fo
r
large
scal
e a
nd hig
h
volta
ge po
we
r
con
v
ersio
n
s. Fi
g
u
re
1 sho
w
s the mai
n
ci
rcu
i
t of a five-lev
el
DCM
C. The
converte
r with
the other leve
l stru
cture h
a
s
the simila
r circuit
s
.
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IJEECS
ISSN:
2502-4
752
Cap
a
cito
r Vol
t
age Balan
c
in
g of Five Le
vel Diod
e Cla
m
ped Con
v
e
r
ter based …
(D. Sindhuja,
V)
261
Figure 1. Structure of
DCM
C
No m
a
tter
which
level
co
nverter is u
s
ed, t
he
stabil
ization
an
d e
quali
z
ation
of
dc-lin
k
cap
a
cito
r voltage
s are im
p
o
rtant for bot
h safe
an
d n
o
rmal o
p
eration of a DCM
C
. Due to th
e
active po
we
r con
s
um
ption
and en
ergy e
x
chan
ge
bet
wee
n
the dc-l
ink capa
cito
r and a
c
source,
the unb
alan
ci
ng ph
enom
en
on of d
c
-lin
k
cap
a
cito
r voltage
s will o
ccurTh
e
hig
her
the level u
s
e
d
in
the DCMC is
the more difficult the b
a
lan
c
e o
per
ation
become
s. Pa
rticula
r
ly the
stable
are
a
h
a
s
a stri
ct limit that the mo
d
u
lation in
dex
coul
d not
b
e
high
er th
a
n
0.55
app
r
o
x
imately in a
c
tive
power conve
r
sion a
ppli
c
ation.
3. Sy
stem Configura
tion
of STAT
CO
M
The STATCOM is designed with the SVPWM te
chnique to enhance the system
stability
by equ
alizati
on of th
e
DC lin
k
ca
pa
citor voltage.
In the bl
ock diag
ram, th
e STATCOM
is
desi
gne
d
wit
h
the sp
ace vector pul
se width
m
odul
a
t
ion techniq
u
e
to
control t
he di
ode
cla
m
ped
conve
r
ter. Th
e level of the diode
clam
pe
d co
nverte
r chosen is five.
Here the GT
O (Gate tu
rn
Off
Thyristo
r) to
control the inj
e
cted
cu
rre
nt or the
co
mp
ensating voltage. DC link
cap
a
cita
nce value
has to be ch
ose
n
. The nu
mber of the swit
chin
g device
s
in the DCMC a
nd the
number of the
cap
a
cito
rs a
r
e de
cide
d by
the level
of the in
ve
rter ch
osen.
With high
er am
ounts of volt
age
levels, the n
u
m
ber
of diod
e
s
g
r
ows q
uad
ratically
wi
th the level m fol
l
owin
g the e
q
uation (m - 1
)
*
(m - 2).
A consta
nt source is
con
necte
d to the load
throu
g
h
the converte
r/inverter
circuit. The
inverter blo
ck is
made
of I
G
BT (Gate-i
n
sulate
d bi
pol
ar tran
sisto
r
s). To
provide
prop
er qu
ality of
power to the
load an
d also
to redu
ce th
e harm
oni
cs
the STATCO
M is co
nne
c
t
e
d as the
sh
unt
comp
en
satin
g
device. S
T
ATCOM
co
nne
cted
will
provid
e co
mpen
sation
curre
n
t for t
h
e
equali
z
ation
of the voltage quality. Th
erefo
r
e t
he
current ha
rmo
n
ics can be
eliminated. T
h
e
injectio
n of the cu
rrent dep
end
s upo
n th
e switch
in
g seque
n
ce of the diod
e cl
a
m
ped
conve
r
ter
whi
c
h is give
n by the spa
c
e vector mo
d
u
lation techni
que.
Figure 2. Block
Diag
ram o
f
STATCOM
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ISSN: 25
02-4
752
IJEECS
Vol.
2, No. 2, May 2016 : 259 –
267
262
3.1. Sy
stem
Con
f
igura
t
ion
As in the bl
ock dia
g
ra
m
of the syste
m
,
each
blo
ck i
s
d
e
si
gn
ed an
d the
system i
s
formed. T
he
sou
r
ce bl
ock
is a th
re
e ph
ase
voltage
source of
16
0*
sqrt (3
) i.e
ap
proximately 2
2
0
volt phase to pha
se rms
was
cho
s
e
n
for the ope
ra
tion
. The ope
rati
ng freq
uen
cy
of the system
is
50
Hz.
The
lo
ad i
s
re
sistiv
e natu
r
e. T
h
e
voltage
of th
e loa
d
i
s
simi
lar to
the
so
u
r
ce
voltage
a
n
d
the po
we
r rating of the l
oad
is d
e
ci
ded
a
s
15
kW. Th
e
load i
s
con
n
e
cted
with th
e so
urce th
ro
ugh
conve
r
ter inv
e
rter bl
ock.
The re
ctifier
block is the
three ph
ase
unc
o
n
trolle
d
rectifier. Th
e diode i
s
u
s
ed a
s
swit
chin
g dev
ice. The
DC
output of the
rectifier i
s
gi
ven to the LC ci
rcuit. Since IGBT devi
c
e
s
are u
s
ed in the three ph
a
s
e inverte
r
, the gene
ration
of gate pulse
is req
u
ire
d
. The method u
s
ed
for the trigge
ring of the inverter i
s
pul
se
widt
h mod
u
la
tion. In the PWM techniqu
e for gate pul
se
gene
ration
th
e
voltage reg
u
lator block a
nd
the
Discre
t
e PWM bl
ocks
are empl
o
y
ed. The volt
age
regul
ator blo
c
k h
a
s the
pro
portion
al g
a
in
of 0.
4
and
in
tegral
gain
of
500.
The
carrier freq
uen
cy
of the
Discret
e PWM
g
ene
rator is
sele
cted a
s
200
0
Hz. Th
e
sam
p
ling time
for th
e ge
ne
ration
of
the PWM is chosen a
s
0.1
s.
The STAT
COM mod
e
l i
s
conn
ecte
d
to the syst
em in
shunt
. The blo
cks of the
STATCOM
can b
e
sep
a
rated to
DCMC
block a
nd g
a
te g
e
n
e
ration
blo
ck. The volta
g
e
maintaine
d
a
c
ro
ss the ca
pacito
r
is 1
0
V. The
swit
ching meth
od
use
d
for the
swit
chin
g of the
GTOs is SVPWM. The frequency of
operation is 50 Hz. The volt
age level is
5. The operating
voltage of the SVPWM technique is specif
ied as 440
V and current value as 10
A.
3.2. Modulati
on of DCM
C
In the DCM
C
topology th
e
use of voltag
e cl
a
m
pin
g
di
ode
s is e
s
se
ntial. A com
m
on
DC-
bus i
s
divided
by an even n
u
mbe
r
, depe
nding o
n
the
numbe
r of vol
t
age levels in
the inverter,
of
bulk
ca
pa
cito
rs i
n
serie
s
with a n
eutra
l point in
th
e
middle of th
e
line. From this
DC-bu
s
,
with
neutral
point
and
cap
a
cito
rs, there a
r
e
clamping
diod
es
con
n
e
c
ted
to an m
-
1
n
u
mbe
r
of val
v
e
pairs, whe
r
e
m is the num
ber of voltage
levels in
the inverter
(voltage levels it ca
n gene
rate
).
3.3. Selectiv
e Harmonic
Elimination
Selective Ha
rmoni
c Elimi
nation (S
HE) is a lo
w
switchi
ng freq
uen
cy strate
gy that uses
cal
c
ulate
d
switching
angle
s
to eliminate
certai
n ha
rmo
n
ics in the
ou
tput vo
ltage. With the h
e
lp
of
Fouri
e
r Se
rie
s
analy
s
is t
he amplitud
e
of any
odd
harmo
nic in
the output sign
al ca
n b
e
cal
c
ulate
d
. The switchi
ng
angle
s
mu
st however b
e
lowe
r than
π
/
2 deg
ree
s
an
d for a nu
mb
er of
swit
chin
g ang
les ha
rmo
n
ic
comp
one
nts
can b
e
affect
ed, whe
r
e a
-
1
numbe
r of harmo
nics can
be
eliminated
(o
ne a
ngle
to
set the fun
d
a
m
ental). If a
n
g
les were
to
be la
rge
r
th
a
n
π
/2 a correc
t
output sig
nal
would
not be achi
evabl
e. For an i
n
verter with
m levels a
= m-1/2. Hig
her
harm
oni
cs
ca
n be filtered
out with addit
i
onal filter
s a
dded b
e
twee
n the inverter and the load
if
need
ed. Fo
r
a five-level in
verter a
= 2,
so the
r
e a
r
e t
w
o
swit
chin
g angle
s
availa
ble an
d a -
1
= 1
angle
s
can b
e
use
d
for ha
rmoni
c comp
onent elimin
a
t
ion.
Figure 3. Switchin
g with an
gles d
e
termi
n
ed by
Selecti
v
e Harm
oni
c Elimination fo
r a Five-level
inverter
3.4. Po
w
e
r L
o
sses
Loss is
an i
m
porta
nt asp
e
ct of po
wer electroni
cs
sin
c
e lo
wer l
o
sse
s
gives
highe
r
efficien
cy. Since
the
multilevel inverte
r
s ca
n o
p
e
r
ate
at differe
nt switchi
ng freq
uen
cie
s
a
nd
with
different b
a
la
ncin
g control
scheme
s
th
e
y
will not
h
a
ve the
same
a
m
ount of p
o
wer lo
sse
s
. To
be
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IJEECS
ISSN:
2502-4
752
Cap
a
cito
r Vol
t
age Balan
c
in
g of Five Le
vel Diod
e Cla
m
ped Con
v
e
r
ter based …
(D. Sindhuja,
V)
263
able to inve
stigate the switching lo
sse
s
in an inve
rter a mo
del
for losse
s
i
s
nee
ded. T
h
e
swit
ching power loss P
sw
durin
g one
se
con
d
in a switch is d
e
fined
by the formul
a
P
sw
=
½ V
d
I
o
I
t
(3)
There V
d
is the voltage over the
swit
ch
when off, I
0
is the current th
rough th
e swit
ch afte
r turn
e
d
on or b
e
fore turne
d
off and
t is either th
e
turn on tim
e
ton or the
switch off time
t
off
. The sum of
all the
switch
ing lo
ss eve
n
t
ene
rgie
s
du
ring
one
second fo
r
one
swit
ch
re
sult
s in that
switch's
swit
ching power loss.
4. Opera
t
ion of STAT
CO
M
4.1. Opera
t
ion of DCMC
In the DCM
C
topology th
e
use of voltag
e cl
a
m
pin
g
di
ode
s is e
s
se
ntial. A com
m
on
DC-
bus i
s
divided
by an even n
u
mbe
r
, depe
nding o
n
the
numbe
r of vol
t
age levels in
the inverter,
of
bulk
ca
pa
cito
rs i
n
serie
s
with a n
eutra
l point in
th
e
middle of th
e
line. From this
DC-bu
s
,
with
neutral
point
and
cap
a
cito
rs, there a
r
e
clamping
diod
es
con
n
e
c
ted
to an m
-
1
n
u
mbe
r
of val
v
e
pairs, whe
r
e
m is th
e n
u
m
ber
of voltag
e level
s
in th
e inverte
r
(vo
l
tage level
s
it
ca
n ge
ne
rat
e
).
With this
co
n
f
iguration five
levels of volt
age
can
be g
enerated b
e
twee
n point a
and the
neut
ral
point n; Vdc/2 , Vdc/4 , 0,-Vdc/4 a
nd –
V
dc/2
, depe
nding on
whi
c
h switche
s
that are switched
on. With
a
hi
gher nu
mbe
r
of voltage l
e
vels th
e
comp
l
e
xity of the in
verter i
n
crea
se. Fro
m
Ta
bl
e 1
it can
be
se
e
n
that for the
voltage V
dc
/2 all
the
u
ppe
r swit
che
s
are
turned
on, co
nne
cting
p
o
in
t
a
to the V
dc
/2 p
o
tential. For the output voltage V
dc
/
4
swi
t
che
s
S
2
, S
3
,S
4
and S
1
are turne
d
on a
n
d
the voltage i
s
held
by the h
e
lp
of
the su
rroundi
ng clam
ping
di
ode
s D
1
and
D`
1
. Fo
r voltage level
s
–V
dc
/4 or
-V
dc
/2 clam
ping
d
i
ode
s
D
2
an
d
D`
2
or D
3
an
d D
`
3
hold
the
voltage, re
sp
ectively. For the
voltages
±Vd
c
/2 the cu
rre
n
t, when bot
h voltage an
d cu
rre
nt are
positive goe
s thro
ugh the
four
top or botto
m swit
che
s
.
For the oth
e
r states p
o
siti
ve current, while voltage i
s
po
sitive, goes
throug
h the
D
x
diode
s a
nd ne
gative
curre
n
t thro
u
gh the
D`
x
diode
s an
d al
so th
rou
gh t
he
swit
che
s
in b
e
twee
n the cl
amping di
ode
s and the lo
a
d
Table 1. Swit
chin
g state
s
of one five-le
v
el phase leg
‘1’ means tu
rned on a
nd ‘0
’ means tu
rne
d
off
Output Voltage
S
1
S
2
S
3
S
4
S
1
` S
2
` S
3
` S
4
`
Vdc/2
1 1 1
1
0
0
0
0
Vdc/4
0 1 1
1
1
0
0
0
0
0 0 1
1
1
1
0
0
-Vdc/4
0 0 0
1
1
1
1
0
-V
dc
/2
0 0 0
0
1
1
1
1
If there i
s
a
DC-sou
rce
cha
r
ging
the
DC-bus
t
here a
r
e
also
current
s flowing
thro
u
gh the
DC-bu
s
to
ke
ep the
DC-bu
s voltag
e
con
s
tant. Ta
bl
e
5.1 al
so
sh
o
w
s that
som
e
switch
es a
r
e
on
more f
r
equ
en
tly than others, mainly S
4
a
nd S`
1
, a
s
lon
g
as
a si
nu
soi
dal outp
u
t wa
ve that req
u
ires
the use of all
voltage level
s
is
cre
a
ted.
Whe
n
the
inv
e
rter i
s
tran
sferri
ng a
c
tive
power thi
s
le
ads
to unbala
n
ce
d cap
a
cito
rs voltages
sin
c
e the cap
a
cit
o
rs
are
cha
r
g
ed and di
sch
a
rge
d
une
qu
ally,
partly due to different wo
rkload
s.
4.2. Vector Repres
entatio
n
The first step
in the algorithm is to tran
sform the referen
c
e ve
cto
r
V
ref (
a, b,
c
) = [
Va,
Vb, Vc
] into
2-D
α
,
β
coo
r
dinate. As i
s
well
kno
w
n
,
the voltage vector in th
e
abc
frame is
transfe
rred in
to 2-D the
αβ
frame a
s
V
α
V
β
Vo
2
3
1
1/2
1/2
0
√
3
/2
√
3
/2
1/2
1
/2
1/2
Va
Vb
Vc
(4)
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ISSN: 25
02-4
752
IJEECS
Vol.
2, No. 2, May 2016 : 259 –
267
264
That is,
V
α
=
Va
−
Vc
, an
d
V
β
=
−
Va
+
Vb
.
obviou
s
ly, the
cal
c
u
l
ation i
s
a
si
mple inte
gral
transfo
rmatio
n. Assumin
g
that the volta
ges
have
a f
o
rm
with the
polar ge
omet
ry as
V
ref =
[
Vr
sin
ω
t, Vr
sin(
ω
t
−
2
π
/
3)
, Vr
sin(
ω
t
+ 2
π
/
3)], the sub
s
ti
tution of these expre
ssi
on
s in yields,
√
3
3
1
(5)
whe
r
e
V
d
c
is the voltage of the dc-lin
k capa
citor.
E
quation (3) i
s
a standa
rd
elliptic eq
uation.
That is to say, a circula
r
tra
j
ectory of
V
re
f in the traditional
αβ
coordinate will be t
r
ansformed into
an elliptical trajectory in the
α
_
β
_
coo
r
di
nate.
Assu
ming th
at floor (
∗
) prese
n
ts the
o
peratio
n that
roun
ds
ea
ch
element of th
e input
sign
al to th
e
nea
re
st inte
ger value
to
ward mi
nu
s i
n
finity, the vertex of
V
1(
α
1
,
β
1) co
ul
d
be
cal
c
ulate
d
as
α
1 = floor(
V
α
)
β
1 = floor(
V
β
) (
6
)
Thus, the a
d
jace
nt vertice
s
V
2(
α
2
,
β
2),
V
3(
α
3
,
β
3), a
nd
V
4(
α
4
,
β
4) could b
e
fast
ascertain
ed
as
(
α
2
,
β
2) = (
α
1 +
1
,
β
1) (
α
3
,
β
3) = (
α
1
,
β
1 + 1)
(
α
4
,
β
4) = (
α
1 +
1
,
β
1 + 1)
The
ve
rtice
s
of V1, V
2
, a
n
d
V3, t
he
min
i
mum
d
o
wn
ward tria
ngl
e,
wh
ere V
ref
is
lo
ca
ted
in
∆
1 2
3
.
Ce
rtai
nly, V
ref
locatin
g
in th
e up
wa
rd tri
a
ngl
e
∆
3 4 5
wil
l
be p
r
e
s
ente
d
by the ot
he
r three ve
rti
c
es
V
2
, V
3
,
an
d V
4
. Wheth
e
r
V
ref
i
s
lo
cating
i
n
th
e
do
wn
ward
or up
ward t
r
ia
ngl
e
co
uld
b
e
dete
r
mi
ne
d b
y
the follo
wi
n
g
crite
r
i
on:
α
+
β
≤
α
1
+
β
1
+1
,
V
re
f
(7)
α
+
β
>
α
1
+
β
1
+1
,
V
re
f
(8)
Obviou
sly, it is also a simpl
e
algorith
m
for digital imple
m
entation.
4.3. D
w
elling Time Calculation
A
ssu
ming t
h
a
t
V
ref doe
s
n
o
t ch
ange
its
amplitude
in
one m
odul
e p
e
riod
Ts
, its a
v
erage
effect in one
module pe
ri
od might be
equivalent
to the three
most adja
c
e
n
t vectors with
respe
c
tive dwelling times a
s
V
ref
Ts
=
V
1
T
1 +
V
2
T
2 +
V
3
T
3
,
if
V
ref in
∆
123 or
(9)
V
2
T
2 +
V
3
T
3 +
V
4
T
4
,
if
V
ref in
∆
234
(10
)
Be
c
a
us
e
T
1 +
T
2 +
T
3 =
Ts
, the
dwelling time
whe
n
V
ref is locating in
_
12
3 could b
e
o
b
tai
ned
as,
T
2 = (
α−
α
1)
Ts
T
3 = (
β
−
β
1)
Ts
T
1 =
Ts
−
T
2
−
T
3
(11
)
If
V
ref loc
a
tes in
∆
234, the cal
c
ulatio
ns b
e
com
e
T
2 = (
β
1 +
1
−
β
)
Ts
T
3 = (
α
1 +
1
−
α
)
Ts
T
4 =
Ts
−
T
2
−
T
3
(12
)
Therefore, th
e basi
c
pro
c
e
ssi
ng of dwell
i
ng ti
me and locatio
n
crite
r
i
on are all sim
p
lified.
Once the T
s
a
r
e no
rmali
z
e
d
by the syste
m
clo
ck
peri
o
d,
all of these
equation
s
co
uld be
reali
z
e
d
by fast calcul
ations, such as
ad
dition, subtra
ction, co
mpari
s
o
n
, an
d truncation, whi
c
h are time
and area efficient in digital fixed-poi
nt ap
plicatio
n.
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEECS
ISSN:
2502-4
752
Cap
a
cito
r Vol
t
age Balan
c
in
g of Five Le
vel Diod
e Cla
m
ped Con
v
e
r
ter based …
(D. Sindhuja,
V)
265
4.4. Minimu
m Energ
y
Pr
operty
Assu
ming th
at all dc-lin
k
cap
a
cito
rs
of
the
n
-l
evel DCM
C
h
a
ve the
sa
me ca
pacita
n
ce
and voltage, the mathem
atical conditio
n
s are
C
1 =
C
2 =
· · ·
=
Cn
=
C
VC
1 =
· ·
·
=
VCn
−
1 =
V
dc/(
n
−
1)
(13
)
The total
en
e
r
gy
store
d
in
the capa
cito
rs
woul
d
rea
c
h the
minimu
m value
whe
n
thei
r voltag
es
are bal
an
ced
(14
)
Define a p
o
sit
i
ve-definite cost functio
n
J
to indicate th
e energy drift from the mini
mum
(15
)
Whe
r
e,
(16
)
whi
c
h is th
e
voltage devia
tion of cap
a
citor
Ci
. If a d
e
finite negati
v
e
∆
J
coul
d be
gua
ra
ntee
d
throug
h the
p
r
ope
r P
W
M
o
u
tputs, the
vo
ltages woul
d f
l
uctuate
towa
rd the
bal
an
ced value
s
. T
h
a
t
is
(17
)
whe
r
e
iC
i
i
s
t
he
curre
n
t ch
arge
into
ca
p
a
citor
Ci
.
Thi
s
con
d
ition i
s
call
ed th
e m
i
nimum
ene
rg
y
prop
erty for a
balan
ced
n
-l
evel DCMC. It could b
e
used as th
e ba
sic p
r
in
ciple f
o
r d
c
-cap
acit
or
voltage bala
n
c
ing a
nd cont
rol.
5. Simulation and Re
sults
To verify the
above d
e
sig
n
and a
nalysi
s
, a simulatio
n
model
wa
s
desi
gne
d usi
ng Mat
lab\Simulin
k. A load of 15
kW i
s
set. Th
e load
will
be
activated at
0.02s. Th
e value
s
of cu
rrent,
voltage ca
n be varied with
the con
n
e
c
tio
n
of the
STATCOM. Th
e simulation re
sults are
sho
w
n in
Figure 4. The
Simulink m
o
del was d
e
si
g
ned
with t
he
config
uratio
n
mentione
d. T
he ge
neration
o
f
gate pulse is
done with the
help of SVPWM metho
d
. The refe
ren
c
e signal i
s
formed and the
n
it
unde
rgo
e
s transfo
rm
s to cal
c
ulate the
sampl
e
time. The re
sp
ectiv
e
Simulink o
u
tput wavefo
rms
for the
given
model
are
shown in fig
u
res
4 to 8.
T
h
e analy
s
is of
total ha
rmon
ic di
stortio
n
wa
s
done for the
sou
r
ce cu
rre
n
t. The IEEE standa
rd
for the THD i
s
belo
w
5%. The obtain
ed
THD
level is
2.61
%. This i
s
sh
own i
n
the fi
gure
8.
Initial
l
y the load i
s
not conn
ect
ed to the
system.
With the con
nectio
n
of the load with the circui
t after 0.1 s the chan
ge in curre
n
t and the voltage
values a
r
e no
ted.
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ISSN: 25
02-4
752
IJEECS
Vol.
2, No. 2, May 2016 : 259 –
267
266
Figure 4. Voltage waveform across the
cap
a
cit
o
r
Figure 5. Co
mpen
sation
current from th
e
STATCOM
Figure 6. Wa
veform of the sou
r
ce cu
rren
t
Figure 7. Output voltage waveform of the
STATCOM
Figure 8. THD analy
s
is of
sou
r
ce cu
rren
t
6. Conclusio
n
DCM
C
can b
e
use
d
in re
a
c
tive power
compen
satio
n
without voltag
e unbal
an
ce
probl
em
and have a common DC-b
u
s and a
r
e p
o
ssible in ba
ck
-to-ba
ck co
nfiguratio
ns
.
With aspe
ct to
industrial popularity, design
sim
p
licit
y, suitability for back-
to-back and reactive power
comp
en
satio
n
the
DCMC
have b
een
ch
ose
n
for
simu
lation for the
Elec
tric
Gr
id Sys
t
em
case i
n
this work.
Wi
th the proposed SVPWM control me
thod in and the capaci
tor voltage unbalance
c
an be c
ont
rolled whic
h mak
e
s
the DCMC an attr
ac
tive c
hoic
e
. This
paper presents
an SVPWM
algorith
m
in t
he
αβ
fra
m
e
with d
c
-lin
k
cap
a
cito
r volt
age
balan
cin
g
control
for
diode
cla
m
pe
d
multilevel STATCOM. The
five-level converter ge
ne
rates almo
st sinusoidal voltage and
current
waveforms
e
v
en at funda
mental
swit
ching freque
n
c
y.
The d
c
li
nk
cap
a
cito
rs voltages
are
well
balan
ce
d with
very small ri
pple. The
system has
lo
w
harm
oni
cs in
the input cu
rrent. Each swi
t
ch
in the conve
r
ter can swit
ch only on
ce per
cycle
whe
n
perfo
rming funda
m
ental frequ
e
n
cy
Evaluation Warning : The document was created with Spire.PDF for Python.
IJEECS
ISSN:
2502-4
752
Cap
a
cito
r Vol
t
age Balan
c
in
g of Five Le
vel Diod
e Cla
m
ped Con
v
e
r
ter based …
(D. Sindhuja,
V)
267
swit
ching whi
c
h will
result
s in
high effi
ciency. Simulation result
s conclude that
the proposed
SVM strategy
is able to ca
rry out the vo
ltage-b
a
lan
c
i
ng task, with
no req
u
ireme
n
t for additio
nal
power ci
rcuitry, within the specifie
d ran
g
e
of operatio
n
.
Referen
ces
[1]
Busqu
e
ts-Mon
ge, S Ale
puz,
J Bordo
n
a
u
and J P
e
rac
a
ula. “
Vo
ltag
e
bal
anci
ng c
ont
rol of d
i
od
e-
cla
m
p
ed
mu
ltil
evel c
onverter
s
w
i
th passive
front-ends
”.
I
EEE Trans. Power Electron.
200
8; 23(4)
:
175
1-17
58.
[2]
Chav
es, E M
a
rgato, JF
Sil
v
a, SF
Pint
o
and
J Santana. “Fast optimu
m-predictive control
and
capac
itor vo
lta
ge
bal
anci
n
g
s
t
rateg
y
for
bip
o
lar
ba
ck-to-
b
a
ck NPC c
onv
e
r
ters in
hi
gh-v
o
ltag
e d
i
rect
current transmi
ssion s
y
stems”
.
IET
Gen. Tra
n
smiss. Distrib.
2011; 5(3): 3
6
8–3
75.
[3]
Jing, H Yu
nlo
n
g
, H Xi
an
gni
ng
,
T
Cheng, C Jun, an
d
Z
Ron
g
xia
ng. “Multil
e
v
el circu
i
t topol
ogi
es bas
e
d
on the s
w
itch
ed-ca
pacitor c
onverte
r a
nd
dio
de-cl
ampe
d
converter”.
IEEE Trans. Power Electron.
201
1; 26(8): 21
27–
21
36.
[4]
Khaj
eho
dd
in,
A Bakhsh
ai a
nd PK Jai
n
. “A simple vo
lta
ge ba
la
ncin
g
scheme for m
-
level
dio
de-
clamp
ed multi
l
e
vel co
nverter
s
based
on a
gener
aliz
ed c
u
rrent flo
w
m
ode
l”.
IEEE Tr
ans. Power
Electron.
20
08;
23(5): 224
8–
2
259.
[5]
Marches
oni a
n
d
P
T
enca. “Diode-c
l
amp
ed
multilev
e
l
co
nv
erters: A practicabl
e
w
a
y
t
o
b
a
la
nce dc-l
ink
voltag
es”.
IEEE Trans. Ind. E
l
ectron.
20
02;
49(4): 75
2–
765
.
[6]
Mohd Ar
if Kha
n
, Atif Iqbal
an
d Sk Moi
n
Ah
mad.
“Spac
e V
e
ctor Puls
e W
i
dth Mod
u
l
a
tion
Scheme f
o
r
a
Seven-P
has
e Voltag
e So
urce Inverter”.
Internati
ona
l Jo
urnal of P
o
w
e
r El
ectronics
and
Drive Syste
m
.
201
1; 1(1): 7-2
0
.
[7]
Pou, R Pi
nd
ad
o, and
D B
o
ro
yev
i
ch. “Vo
l
tag
e
-ba
l
anc
e l
i
mit
s
in fo
urlev
e
l
dio
de-cl
ampe
d
converter
s
w
i
t
h
pass
i
ve front ends”.
IEEE Trans. Ind. E
l
ectron
. 20
05;
52(1): 19
0–
196
.
[8]
Ren
ge a
nd H
M
Sur
y
a
w
a
n
sh
i. “F
ive-leve
l di
ode cl
amp
ed i
n
verter to el
imi
nate commo
n
mode vo
ltag
e
and re
duce dv
/dt in medium
voltage rati
ng
inducti
on mot
o
r drives”.
IEEE Trans. Power Electron
.
200
8; 23(4): 15
98–
16
07.
[9]
Saee
difar
d
, R Iravan
i an
d J Pou. “Anal
ys
is a
nd
contro
l of d
ccapac
itor- volt
age-
drift phe
no
meno
n of a
passiv
e
front-e
nd five-l
evel co
nverter”.
IEEE Trans. Ind. Electron.
2007; 5
4
(
6): 3255
–3
266
.
[10]
Sirisha
BN S
u
shee
la
and
P
Satishkum
a
r. “T
hree Phase T
w
o
L
eg
Ne
utra
l Poi
n
t Cl
ampe
d Co
nverte
r
w
i
t
h
out
put D
C
Volta
ge R
e
gul
ation
an
d Input
Po
w
e
r F
a
ctor Correcti
o
n”. Internatio
n
a
l
Jour
na
l of
Pow
e
r Electron
ics and Dr
ive S
ystem
. 20
12; 2
(
2): 138-1
50.
[11]
Z
h
igu
o
an
d P F
ang Z
hen
g. “A sinuso
i
da
l P
W
M
method
w
i
th voltag
e ba
l
anci
ng ca
pab
ili
t
y
for dio
de-
clamp
ed five-l
e
v
el conv
erters”
.
IEEE
Trans. Ind. Appl.
2
009;
45(3): 102
8–
1
034.
[12]
Z
h
igu
o
, P F
a
n
g
Z
hen
g, KA C
o
rzin
e, VR Ste
f
anov
ic, JM L
e
u
then, a
nd S
Gataric. “Volta
ge b
a
la
ncin
g
control
of
dio
d
e
clam
ped
mu
ltileve
l r
e
ctifier/inverter s
y
stem
s”.
IEEE Trans. Ind. Appl.
2
005; 41(
6):
169
8–
170
6.
Evaluation Warning : The document was created with Spire.PDF for Python.