Inter national J our nal of P o wer Electr onics and Dri v e System (IJPEDS) V ol. 15, No. 4, December 2024, pp. 2262 ∼ 2274 ISSN: 2088-8694, DOI: 10.11591/ijpeds.v15.i4.pp2262-2274 ❒ 2262 Impedance netw ork-based ultra sparse matrix con v erter with enhanced v oltage gain Zahid Hassan, M. A. Khan, Md. Rabiul Islam Department of Electrical and Electronic Engineering, F aculty of Engineering, Bang abandhu Sheikh Mujib ur Rahman Science and T echnology Uni v ersity , Gopalg anj, Bangladesh Article Inf o Article history: Recei v ed Oct 7, 2023 Re vised May 7, 2024 Accepted Jun 2, 2024 K eyw ords: A C to A C con v erter Doubler boost netw ork High v oltage g ain matrix con v erter Impedance netw ork Ultra sparse matrix con v erter V oltage g ain enhancement ABSTRA CT The matrix con v erter is de vised to achie v e sinusoidal input current and output v oltage, and high po wer density . The typical matrix con v erter gi v es v oltage g ain less than unity using a signicantly lar ge number of switches. T o reduce the number of switches an ultra sparse matrix con v erter (USMC) is introduced whose v oltage g ain is still less than unity . Researchers also introduced man y modied v ersions of these matrix con v erters including quasi-Z-source, series Z- source, switched inductor , and switched capacitor USMCs. Although all of these matrix con v erters ha v e their relati v e adv antages and disadv antage s in terms of the number of switches and passi v e elements, the v oltage g ain is still mar ginal. This paper focused on achie ving higher v oltage g ain using minimal sw itches and passi v e elements. W e proposed a doubler boost impedance netw ork based ultra sparse matri x con v erter (DB-USM C). The doubler boost impedance netw ork consists of a boost stage and doubler stage where the boost stage enhances the v oltage and the doubler stage mak es it double. The v oltage g ain of the proposed DB-USMC con v erter is 4.00 at a 50 % duty c ycle. The obtained results of the proposed DB-USMC con v erter sho w a path to get superior v oltage g ain using minimal switches and passi v e elements in a cost-ef fecti v e manner . This is an open access article under the CC BY -SA license . Corresponding A uthor: Zahid Hassan Department of Electrical and Electronic Engineering, F aculty of Engineering Bang abandhu Sheikh Mujib ur Rahman Science and T echnology Uni v ersity Gopalg anj-8100, Bangladesh Email: zahidhassan423359@gmail.com 1. INTR ODUCTION High v oltage g ain is an essential requirement in po wer sys tems and rene w able ener gy systems. The generated base v oltages are not enough for ef fecti v e po wer transmission due to the i 2 R losses which cause lo w po wer ef cienc y . Currently , a step-up transformer with high v oltage alternating current (HV A C) transmission solv es this issue. Ho we v er , the transformer is not al w ays suitable because of its b ulkier size, lar ge space requirement, and high cost. Als o, the transformer cannot v ary the frequenc y to meet the grid requirement. Besides, high-v oltage direct current (HVDC) transmission is more adv antageous compared to the HV A C [1]. So if we substit u t e the tra nsformer with the po wer con v erters then we get tw o benets. Firstly , we can use the high direct current (DC) v oltage in HVDC transmission. Secondly , mak e the output v oltage and frequenc y of rene w able ener gy syst ems suitable for the grid system. W e can also con v ert the output of the rene w able ener gy systems at a suitable v oltage and frequenc y to direct use in industry and households with minimum cost. The matrix con v erters [2], a class of po wer con v erters, ha v e attracted much attention due to their abil- J ournal homepage: http://ijpeds.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 2263 ity to con v ert poly-phase alternating current (A C) to poly-phase A C at v ariable v oltage and frequenc y with aiming to achie v e higher v oltage g ain. It has sinusoidal input and output with a unity po wer f actor , re generati v e capability , and less harmonic distortion [2]-[4] that mak es it suitable for v arious applications. Although matrix con v erters ha v e man y applications, the major dra wback is the necessity of a lar ge number of s witches and lo w v oltage g ain [5], [6]. F or e xample, a typical s p a rse matrix con v erter is designed by using fteen or twelv e switches [7], [8] with v oltage g ain less than unity . The ultra sparse matrix con v erter (USMC) is designed by modifying the sparse matrix con v erter to reduce the number of switches. The typical USMC requires nine switches [9], [10] which is still higher in number . On the other hand, the USMC does not ha v e an y interme- diate topologies and therefore char ge storage is not possible si n c e there ha v e no passi v e elements. Therefore, the v oltage g ain of USMC is v ery lo w which is 0.866. The USMC is currently us ed in rene w able ener gy and photo v oltaic (PV) applications [11], [12], wind ener gy inte gration in microgrids [13], feeding permanent magnet synchronous motors (PMSMs) in applications with eld-oriented control (FOC) [14], [15] and as a po wer -transferring de vice [16]. But the lo w v oltage g ain reduces their ef cienc y and also limits applicability in industries. The v oltage g ain can be impro v ed by using a step-up transformer , b ut this is costly and require more space. T o o v ercome the limitations of con v entional sparse matri x con v erters res earchers proposed the Z-source matrix con v erter by introducing the Z-source impedance netw ork [17]. The Z-source matrix con- v erter aims to enhance v oltage g ain using four passi v e elements (tw o capacitors and tw o inductors) [18]. The Z-source impedance netw ork is inte grated with an ultra sparse matrix con v erter and the resulting matrix con- v erter is called ZS-USMC [19]. The ZS-USMC gi v es a v oltage g ain of 1.5 emplo ying the same number of switches as USMC and four passi v e elements, which is still lo w . Besides, this con v erter has no common ground in the impedance netw ork [20]. T o circumv ent this dra wback series Z-source ultra sparse matrix con- v erter (SZS-USMC) is introduced [21], [22]. The adv antage of SZS-USMC is that it has common ground, with all elements the sam e as ZS-USMC, b ut it requires addi tional diode [23], and v oltage g ain drops to 0.5. On the other hand, the SZS-USMC produces discontinuous rectier output current which is a serious issue that increases the ripple. T o address these limitations, a quasi-Z-source impedance netw ork is inte grated into USMC (QZ- USMC) [24], [25]. The QZ-USMC has a v oltage g ain of 1.5 using the same number of switches and passi v e elements as ZS-USMC. In QZ-USMC, common mode v oltage, the same v oltage present at tw o or more nodes of a circuit with respect to a reference point, is also increased which can increase the leakage current that may damage the insulation. Finally , although the Z-source impedance netw ork inte grated USMCs has relati v e ad- v antages and disadv antages the noticeable point is that the v oltage g ain is still lo w . T o o v ercome the limitations of the Z-source impedance netw ork inte grated USMCs and impro v e v oltage g ain, an acti v e zero-state switched netw ork is inte grated with ZS-USMC [26]. One v ersion of it is switched capacitor ZS-USMC (SCZ-USMC) [27], [28] that requires se v en pass i v e elements and ten switches. It has a v oltage g ai n of 3.0, which is mar ginal, and a wide load range re g arding po wer f actor . The limitation of SCZ-USMC is the limited v oltage con v er - sion ratio due to using capacitors to transfer ener gy between dif ferent v oltage le v els. T o transcend this barrier , switched inductor ZS-USMC (SIZ-USMC) is reported in [29], [30]. The SIZ-USMC has the same v oltage g ain of 3.0 using six passi v e el ements and nine switches which are slightly lo wer than the SCZ-USMC. It also has higher v oltage stress [31] which is the amount of v oltage that is applied across the switching de vices in the con v erter , which can cause them to break do wn or f ail due to e xcessi v e v oltage. Both SCZ-USMC and SIZ- USMC ha v e the same v oltage g ai n b ut require a lar ge number of passi v e elements which is costly . T o reduce the number of passi v e elements the switched boost USMC (SB-USMC) is introduced [32]. In SB-USMC, only tw o passi v e elements are required and it has lo wer inductor current stress. The required number of diodes is also reduced b ut the v oltage g ain drops to 2.0. On the other hand, it has higher v oltage stress. All e xisting matrix con v erters ha v e their relati v e adv antages and disadv antages b ut the most noticeabl e dra wback of all matrix con v ert ers is that the v oltage g ain is lo w and mar ginal. Therefore, we need more v oltage g ain to meet the requirements of po wer systems and rene w able ener gy systems. Ho we v er , the question arises, ho w we can achie v e higher v oltage g ain using a small number of switches and passi v e elements? T o answer this question, we proposed a doubler boost ultra sparse matrix con v erter (DB-USMC) by inte grating a no v el ‘doubler boost impedance netw ork’ into t he ultra sparse matrix con v erter . The proposed DB-USMC uses the doubler boost concept that comes from the v oltage doubler circuit and boost con v erter . The doubler boost impedance netw ork has tw o stages that a re boost a n d doubler st ages. W e simul ated the proposed DB-USMC using matlab simulink softw are. Finally , the results sho w that the proposed DB-USMC Impedance network-based ultr a spar se matrix con verter with enhanced volta g e gain (Zahid Hassan) Evaluation Warning : The document was created with Spire.PDF for Python.
2264 ❒ ISSN: 2088-8694 con v erter has a v oltage g ain of 4.00 at 50 % duty ratio. It also requires only three passi v e elements which are less than the other reported con v erters e xcept for SB-USMC. The obtained results sho w a path to design a matrix con v erter to meet the requirements of po wer systems and rene w able systems with superior v oltage g ain using minimal passi v e elements that reduce cost. W e or g anized the paper as follo w: i) Section 2, we described the proposed DB-USMC topology with an elaborate description of the doubler boost netw ork which is the heart of the proposed DB-USMC topology , formulation of the mathematical background, and de v elopment of the emplo yed switching pattern; ii) Section 3, we included the methodology of ho w the proposed DB-USMC topology has been tested and v alidated with a summary of the used v alue of all parameters; iii) Section 4, we summarized the ndings, with the aim of meeting the demand for high v oltage g ain, including a comparati v e analysis; and i v) Section 5, we concluded with the future directions. 2. PR OPOSED T OPOLOGY The proposed DB-USMC topology , as sho wn in Figure 1, is consist of three stages: the rectier stage on the left, the doubler boost stage in the middle, and the in v erter stage on the right. The main function of the rectier stage is to con v ert A C-DC. Three-phas e A C-DC rectier act as a boost rectier where output rectied v oltage is 1 .5 times the input A C v oltage [33]. This stage consists of three unidirectional switches that are S X , S Y , and S Z , and twelv e po wer diodes that are connected to the 3-phase supply . Three phase supply sources are connected in X , Y , and Z points where each line contains an inductor and a capacitor that constitute a lter . The output of the rectier stage is DC denoted by V r o that is directly coupled to the doubler boost stage. The main function of the doubler booster stage is to boost the input DC t hat is sho wn separately in Figure 2. The doubler booster stage is di vided into tw o substages; booster stage and doubler stage. The booster stage consist of an inductor denoted by L and a switch denoted by S . On the other hand, the doubler stage consist of tw o capacitors denoted by C where both capacitors ha v e the same v alue and tw o diodes denoted by D 1 and D 2 . The output of the doubler boost stage is also DC, denoted by V db in Figure 1, which is directly con- nected to the input of the in v erter stage, and the main function of this stage is to con v ert input DC into A C. The in v erter stage consists of si x switches that are denoted by S AX , S AY , S B X , S B Y , S C X , and S C Y . The outputs are tak en as u A , u B , and u C . W e e v aluated the performance of the proposed DB-USMC topology , as described abo v e, using matlab simulink softw are. Three important steps in e v aluating the performance of the proposed DB-USMC topol- ogy are understanding the operation of the doubler booster impedance netw ork, determining the appropriate switching strate gy , and calculating the proper v alue of passi v e elements. W e described all three steps in 2.1. Figure 1. Proposed DB-USMC topology 2.1. Doubler boost impedance netw ork Doubler boost (DB) con v erter is a step-up con v erter and dynami c beha vior of DB con v erter is s imilar to the boost con v erter that is addressed in [34]. The complete operation of the doubler boost con v erter can be described in tw o modes. The rst is the shoot-through mode, and t he second is the non-shoot-through mode. Int J Po w Elec & Dri Syst, V ol. 15, No. 4, December 2024: 2262–2274 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 2265 F or each c ycle of pulses, it is high for a certain period of time and lo w for the remaining time. The con v erter run in shoot-through mode when the pulse is high and runs in non-shoot-through mode when the pulse is lo w . In the shoot-through state, switch S is ON, and diodes D 1 and D 2 are OFF which can visualized in Figures 1 and 2. The switch and diodes both can not be ON in together . So in this m od e boost stage is ON and the doubler stage is OFF in Figure 2. Let apply KVL to the boost stage circuit, as in (1). V r o − V L = 0 (1) In the non-shoot-through mode, switch S is OFF and diodes D 1 and D 2 are ON, as can be visualized in Figures 1 and 2. In this mode b oos t stage is OFF and the doubler stage is ON therefore current o ws through the doubler circuit. The operation of t he v oltage doubler circuit is described in [35]. Let appl y KVL in the doubler circuit, as in (2). V r o − V L − V r o 1 = 0 (2) V r o 1 is the v oltage that acts as the input v oltage of the doubler circuit as sho wn in Figure 2, as in (3)-(6). V r o − V L − V D B 2 = 0 (3) V r o 1 = V D B 2 (4) V L = V r o − V D B 2 (5) Z T 0 V L = 0 (6) By solving this equation, as in (7). V D B = 2 V r o 1 − D (7) The output v oltage of the doubler boost represent in (7). It is also clear that the doubler boost impedance netw ork boost the v oltage le v el from V r o to 2 V r o / (1 − D ) . No w , the maximum phase output v oltage of the rectier stage is gi v en by (8). V abc = m f √ 3 V D B (8) Figure 2. The doubler boost stage of the proposed DB-USMC topology Impedance network-based ultr a spar se matrix con verter with enhanced volta g e gain (Zahid Hassan) Evaluation Warning : The document was created with Spire.PDF for Python.
2266 ❒ ISSN: 2088-8694 The nal A C output v oltage represent in (8). The o v erall g ain of the proposed con v erter including the po wer f actor is as in (9). V abc V xy z = √ 3 m f 2 × 2 1 − D cos( α ) (9) Where α is the angle between v oltage and current. Boosting f actor (BF) of DB-USMC is represented by (10) and (11). B F = √ 3 m f 2 × 2 1 − D = √ 3 m f 1 − D (10) D = B F − √ 3 m f B F (11) The (11), that represents t he required duty ratio to obtain the desired v oltage g ain in terms of the boosting f actor . 2.2. Switching strategy The optimization of con v erter ef cienc y depends on the switching technique [36]. W e use state v ector pulse width modulation (SVPWM) [37] for generating the control signal to control the output current of the rectier stage and the v oltage of the in v erter stage. The pulse width modulation signal is generated by com- paring the reference v oltage with a carrier signal, which has a x ed frequenc y and amplitude. In SVPWM, rstly each reference v ector , such as I X , I Y , and I Z , is con v erted i nto a set of three v ectors, which is then used to generat e a pulse width m od ul ation (PWM) signal for each phase. In SVPWM, the duty c ycle of the PWM signal is adjusted based on the position of the reference v ector in the space v ector diagram. In the rectier stage, there ha v e three reference v ectors, I X , I Y , and I Z , and corresponding nine v ectors. Among nine v ectors six are acti v e v ectors that are I xy , I y z , I z x , I y x , I z y , and I xz and three are zero v ectors that are I xx , I y y , and I z z where I xy , I y z , I z x , I y x , I z y , and I xz are the line current between the tw o corresponding lines and I xx , I y y , and I z z are the line current of x, y , and z line, respecti v ely . Similarly , in the in v erter stage, there are six acti v e v ectors that are V 001 , V 010 , V 011 , V 100 , V 101 , V 110 , and tw o zero v ectors that are V 000 and V 111 where V 001 (001 is the binary number) means the v oltage when S X , S y are OFF and S z is ON and similarly switches are ON and OFF based on other v ectors. On the other hand, tw o zero v ectors V 000 and V 111 indicate the v oltage when all switches are either ON or OFF . T o implement SVPWM in the rectier stage, reference input current I r f is synthesized by tw o acti v e v ectors. Similar things will happen for the in v erter stage. The reference v oltage is synthesized by a combination of acti v e and zero v ectors. In the DB-USMC control strate gy , the duty ratio of SVPWM i s continuously v arying and also there ha v e dif ferent duty ratios for the rectier and in v erter stages. The duty ratio D I xy and D V 001 for the rectier and in v erter stages, respecti v ely , are dened by (12)-(14). D I xy = sin( π 3 − γ ) cos( γ ) (12) D V 001 = m f sin( π 3 − ∂ ) (13) D V 001 = m f sin( ∂ ) (14) Here γ is the sector angle of the rectier stage and ∂ is the v ector angle of output v oltage in the in v erter stage. Similarly , we can dene duty ratio for all other acti v e v ectors such as D I X Z and D V 010 . The o v erall duty ratio is dened as the multiplication of corresponding duty ratios in rectier and in v erter stages such as D I xy and D V 001 . All o v erall duty ratios for DB-USMC are gi v en in (15)-(19). D a = D I xy × D V 001 (15) D b = D I xy × D V 010 (16) D c = D I xz × D V 010 (17) Int J Po w Elec & Dri Syst, V ol. 15, No. 4, December 2024: 2262–2274 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 2267 D d = D I xz × D V 001 (18) D 0 = 1 − D a − D b − D c − D d − D (19) Here D is the duty ratio in the shoot mode for the doubler boost impedance netw ork where shoot mode is one of tw o modes of operation that is described in 2.1. In the rectier stage, the a v erage output v oltage is 1 . 5 × V xy z where V xy z is the input phase v oltage. Finally , based on the abo v e-mentioned duty ratios we dened the switching pattern. W e ha v e sho wn the switching pattern for the proposed DB-USMC in T able 1. The switching strate gy of DB-USMC is designed to reduce switching losses. F or I xy , v ectors of in v erter stage V 000 , V 001 , and V 010 are ON and the duty ratio at that time will be D 0 /6, D a /3, and D b /1.5 to mak e sure that all v ector of in v erter stage are not ON all together . Similarly , F or I xz v ector of the in v erter stage V 010 , V 001 , V 000 , V 000 , V 001 , and V 010 are ON and the duty ratio at that time will be D c /1.5 D d /3, D 0 /6, D 0 /6, D d /3, D c /1.5. Ag ain for I xy , v ectors of in v erter stage V 010 , V 001 , and V 000 are ON and the duty ratio at that time will be D b /1.5, D a /3, and D 0 /6. T able 1. The switching pattern for e v aluating the proposed DB-USMC topology Non shoot through Shoot through V 000 D 0 / 6 V 000 D 0 / 6 V 001 D a/ 3 V 001 D d / 3 V 010 D b / 1 . 5 V 010 D c / 1 . 5 V 010 D c / 1 . 5 V 010 D b / 1 . 5 V 001 D d / 3 V 001 D a / 3 V 000 D 0 / 6 V 000 D 0 / 6 2.3. P assi v e elements W e calculate the v alue of passi v e components based on the ripple current across the inductor and the ripple v oltage across the capacitor using the CCM mode. CCM is a continuous-current mode technique that is addressed [38]. W e calculate the v alue of passi v e components based on the ripple current across the inductor and the ripple v oltage across the capacitor , as in (20). V r o = V L = L di dt = L ∆ I L ∆ t (20) No w ∆ t = D T where T = 1 /f is the time period, as in (21). ∆ I L = D T V r o L (21) From (7), we get (22). ∆ I L = D (1 − D ) V D B 2 Lf (22) According to the continuous conduction mode, we get (23) and (24). I L − 1 2 ∆ I L = 0 (23) I L = D (1 − D ) V D B 4 Lf (24) No w P 0 = V D B I L , as in (25) and (26). L = D (1 − D ) V D B 2 4 f P 0 (25) L = D (1 − D ) V 2 D B cos α 4 f % nP o (26) Impedance network-based ultr a spar se matrix con verter with enhanced volta g e gain (Zahid Hassan) Evaluation Warning : The document was created with Spire.PDF for Python.
2268 ❒ ISSN: 2088-8694 See (26), this gi v es the required v alue of L for % n ripple. On the other hand for capacitor , as in (27)-(31). I C = C d V c d t = C ∆ V D B ∆ t (27) C = ∆ tI C ∆ V D B (28) C = D T I C ∆ V D B (29) C = D T I C ∆ V D B ∆ V 2 D B (30) C = D T P 0 ∆ V 2 D B (31) As V C = V D B , we found (32). C = D T P o ∆ V 2 D B (1 − D )% z cos α (32) See (32), that gi v es the required v alue of C for % z ripple. 3. METHODOLOGY W e tested and v alidated the proposed DB-USMC topology , as described in section 2, using MA T - LAB/simulink R2018a softw a re as the literature suggested [32], [35]. At rst, we designed and constructed the proposed DB-USMC topology in the MA TLAB/Simulink softw are based on the diagram sho wn in Figure 1. After that, we assigned the v alue of all elements as indicated on the diagram from T able 2. In constructing T able 2, we calculated the v alue of tw o important passi v e elements, the inductor , and capacitor , as L = 0 . 2198 µH and C = 25 µF using (26) and (32), res pecti v ely , with taking 1.5625% and 0.3185% ripple f actor , respecti v ely . The v alue of all other elements is selected by re vie wing e xisting literature [19], [24], [25], [27], [31]. In se- lecting the input A C supply we tried to k eep it close to the North American po wer supply as sho wn in Figure 3 with a peak v alue of 100 V and root mean square (RMS) v alue of 70.7 V . W e selected the duty rati o and switching frequenc y as 0.5 and 40 KHz, respecti v ely based on the e xisting literature [39], [40]. Finally , we set the switching pattern based on T able 2 and simulate the proposed DB-USMC topology . T able 2. The used v alue of parameters for three dif ferent stages of the proposed DB-USMC topology Rectier stage Doubler boost stage In v erter stage P arameter V alue P arameter V alue P arameter V alue Switch rating 3000 V , 1000 A Switch rating 3300 V , 1200 A Switch rating 3000 V , 1000 A Diode rating 1200 V , 30 A Diode rating 1200 V , 30 A Diode rating 1200 V , 30 A Input lter ( L in ) 1 mH Inductor 0.2198 µH Output lter ( L out ) 1mH Input lter ( C in ) 10 µF Capacitor 25 µF Output lter ( C out ) 1 µF Int J Po w Elec & Dri Syst, V ol. 15, No. 4, December 2024: 2262–2274 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 2269 Figure 3. Input w a v eform to the rectier stage of the proposed DB-USMC topology 4. RESUL TS AND DISCUSSION W e e v aluated the performance of the proposed DB-USMC topology in terms of v oltage g ain and the required elements to implement it. W e obtained an end to end v oltage g ain of 4.00 with a minimal number of elements required to implement the proposed DB-USMC topology . The obtained high v oltage g ain tak es us one st ep forw ard to answer the question of ho w we can achie v e higher v oltage g ain to meet the requirements of po wer systems and rene w able ener gy systems. Besides, the minimal number of elements required to implement the proposed DB-USMC topology enables to distrib ution of the solution at a reasonable cost. The 4.1 represents the output obtained at each stage of the proposed DB-USMC topology with an ultimate aim of high v oltage g ain and 4.2 represents a comparison of obtained results with the e xisting solutions for minimizing the cost. 4.1. Results The output of the rectier stage is 176V DC v oltage (rectied) as sho wn in Figure 4 whereas the input A C supply to this stage, as well as for the proposed DB-USMC topology , has a peak v alue of 100V and an RMS v alue of 70.7V as sho wn in Figure 3. The rectied output v oltage is slightly dif ferent from the theoretical v alue which is theoretically demonstrated as 150V in Section 2 This dif ference is due to the use of the lter circuits which also act as the storage elements. Therefore, a v oltage g ain of 2.49 with respect to the RMS v alue of the input A C supply is obtained in this stage. This v oltage dri v es the doubler booster circuit. Figure 4. Output w a v eform of the rectier stage The rectied 176V DC acts as the i nput v oltage to the doubler boost stage. The duty ratio of the doubler boost ci rcuit is 0.5. In shoot-through mode, the switch acts as a short circuit, so the doubler circuit Impedance network-based ultr a spar se matrix con verter with enhanced volta g e gain (Zahid Hassan) Evaluation Warning : The document was created with Spire.PDF for Python.
2270 ❒ ISSN: 2088-8694 is OFF and no v oltage is produced in this mode. The current across the inductor i s sho wn in Figure 5. In the non-shoot-through mode, the doubler stage is ON, and v oltage stress across diodes ( D 1 and D 2 ) is sho wn in Figure 6. In this mode, we get a maximum v oltage that is 680V -690V , which is sho wn in Figure 7. So in the doubler boost stage, we get the v oltage that is 4 times the input to this stage. So a high v oltage g ain of 3.92 with respect to the input to this stage and 9.76 with res pect to the RMS v alue of the input A C supply is obtained in the doubler boost stage. Figure 5. W a v eform of the current across the inductor Figure 6. W a v eform of the v oltage across diodes ( D 1 and D 2 ) The boosted DC v oltage acts as the input of the in v erter stage. In the in v erter stage, we get the output A C v oltage with a peak v alue of 400V , which is sho wn in Figure 8. So the v oltage at the output stage is 4 times the input A C supply . Therefore a high v oltage g ain of 4.00 with respect to the input A C supply and 0.41 with respect to the input to this stage is obtained. The obtained results at dif ferent stages are summarized in T able 3. The obtained high g ain at dif ferent stages meets the v arious requirements of the po wer systems and rene w able ener gy systems. The doubler boost stage is the main stage to achie v e this high v oltage g ain. By increasing the modulation inde x or duty c ycle, higher v oltage can be achie v ed where the limit is M f + D ⩽ 1 . Int J Po w Elec & Dri Syst, V ol. 15, No. 4, December 2024: 2262–2274 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 2271 Figure 7. Output w a v eform of the doubler boost stage Figure 8. Output w a v eform of the in v erter stage of the proposed DB-USMC topology T able 3. V oltage g ain of the proposed DB-USMC topology Stage of the proposed DB- USMC topology Output Reference v oltage Obtained v oltage g ain Applications Rectier stage 176 V Input A C supply (100 V peak and 70.7 V RMS) 2.49 Boosted rectier Doubler boost stage 690 V Input A C supply 9.76 HVDC transmission Input to this stage 3.92 Boosting DC In v erter stage 400 V(peak) 283 V (RMS) Input A C supply 4.00 HV A C transmission Direct industrial usages Input to this stage 0.41 – 4.2. Comparati v e analysis W e conducted a comparati v e analysis among the proposed DB-USMC and e xisting con v erters such as ZS-USMC, SZS-USMC, QZ-USMC, SIZ-USMC, and SB-USMC. W e compared the proposed DB-USMC con v erter ag ainst e xisting con v erters considering parameters that are inductor current, capacitor v oltage, the required number of passi v e elements, and the required number of diodes. The comparati v e analyses are sum- marized in T able 4. Impedance network-based ultr a spar se matrix con verter with enhanced volta g e gain (Zahid Hassan) Evaluation Warning : The document was created with Spire.PDF for Python.