Inter national J our nal of Recongurable and Embedded Systems (IJRES) V ol. 14, No. 1, March 2025, pp. 200 ∼ 207 ISSN: 2089-4864, DOI: 10.11591/ijres.v14.i1.pp200-207 ❒ 200 FPGA implementation of articial neural netw ork f or PUF modeling Mohd Syaq Mispan 1,2 , Mohammad Haziq Ishak 2 , Aiman Zakwan Jidin 1,2 , Haslinah Mohd Nasir 2 1 Micro and Nano Electronics (MiNE) Research Group, Centre for T elecommunication Research and Inno v ation (CeTRI), Uni v ersiti T eknikal Malaysia Melaka, Durian T ungg al, Malaysia 2 F aculty of Electronics and Computer T echnology and Engineering, Uni v ersiti T eknikal Malaysia Melaka, Durian T ungg al, Malaysia Article Inf o Article history: Recei v ed Feb 26, 2024 Re vised Jul 22, 2024 Accepted Aug 12, 2024 K eyw ords: Computational model Hardw are ngerprinting Lightweight authentication Machine learning Ph ysical unclonable function ABSTRA CT Field-programmable g ate array (FPGA) is a prominent de vice in de v eloping the internet of things (IoT) application since it of fers parallel computation, po wer ef cienc y , and sca lability . The identication and authentication of these FPGA- based IoT applications are crucial to secure the user -sensiti v e data transmitted o v er IoT netw orks. Ph ysical unclonable function (PUF) technology pro vides a great capability to be used as de vice identication and authentication for FPGA- based IoT applications. Ne v ertheless, con v entional PUF-based authentication suf fers a huge o v erhead in storing the challenge-response pairs (CRPs) in the v erier’ s database. Therefore, i n this paper , the FPGA implementation of the Arbiter -PUF model using an articial neural netw ork (ANN) is presented. The PUF model can generate the CR Ps on-the-y upon the authentication request (i.e., by a pro v er) to the v erier and eliminates huge storage of CRPs database in the v erier . The architecture of ANN (i.e., Arbiter -PUF model) is designed in Xilinx system generator and subsequently con v erted into intell ectual property (IP). Further , the IP is programmed in Xilinx Artix-7 FPGA with other peripher - als for CRPs gene ration and v alidation. The ndings sho w that the Arbiter -PUF model implementation on FPGA using the ANN technique achie v es approxi- mately 98% accurac y . The model consumes 12,196 look-up tables (LUTs) and 67 mW po wer in FPGA. This is an open access article under the CC BY -SA license . Corresponding A uthor: Mohd Syaq Mispan F aculty of Electronics and Computer T echnology and Engineering, Uni v ersiti T eknikal Malaysia Melaka Jalan Hang T uah Jaya, 76100 Durian T ungg al, Melaka, Malaysia Email: syaq.mispan@utem.edu.my 1. INTR ODUCTION Internet of things (IoT) enable the ubiquitous electronic de vices in which these de vices are connected via an internet netw ork, and it is possible to e xchange data among them. IoT implementation often requires specic and unique netw ork requirements, which can be programmed or reprogrammed in the eld of applica- tion with a cost and time-ef cient manner . Field-programmable g ate array (FPGA) is a foundation for b uilding the ne xt generation of IoT systems since it of fers scalability , lo w latenc y , and lo w po wer [1]-[3]. FPGA can be programmed or reprogrammed according to the requirements of IoT applicat ions. Examples of IoT applica- tions include secure access, smart surv eillance cameras, smart homes, and smart meters. All these applications require user -specic data to be processed. Hence, it is v ery crucial to enable de vice identication and authen- tication in IoT applications [4]. J ournal homepage: http://ijr es.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 201 Ph ysical unclonable function (PUF) is a technology that can be deplo yed in FPGA-based IoT ap- plications for de vice identication and authentication. PUF pro vides root-of-trust from a hardw are layer by e xploiting the inte grated circuit (IC) manuf acturing intrinsic process v ariations [5]. PUF maps an input kno wn as a challenge to generate a unique output kno wn as a response. The mapping of the challenge and response pairs (CRPs) is unique for a group of similar types of PUFs (i.e., de vice-specic response). Hence, PUF pro- vides a great and promising capability to be used for de vice identication and authentication application. Figure 1 depicts the PUF-based identication and authentication process, which consists of tw o phases; enrollment and authentication. During the enrollment phase, the CRPs of the pro v er are e xtracted and stored in the v erier database, d , in a trusted en vironment. In the eld of application, the pro v er sends its response ( ˜ r ) to the v erier and compares it ag ainst the response ( r ) in the database. If both responses are matched, the pro v er is a genuine or v alid de vice, otherwise, the pro v er is identied as a f ak e de vice. V erier − → Pr o v er j ⟨ c ij , r ij ⟩ with c ij ← T R N G () ← → r ij ← P U F ( c ij ) 1x Enrollment d j ← d ⟨ c , r ⟩ ← ⟨ c ij , r ij ⟩ with i ← d j d x Authentication d j ← d j − 1 c − → ˜ r ← P U F ( c ) Abort if HD ( ˜ r,r ) > ϵ ˜ r ← − Figure 1. Identication and authentication process using PUF [6], [7] PUF-based identication and authentication, as described abo v e, has a major dra wback of se v ere area o v erhead in the v erier database. The CRPs are not allo wed to be reused to a v oid on-path attack or man-in- the-middle attack [8]. Therefore, the v erier has to store an enormous amount of CRP s to authenticate the PUFs. Storing the PUF computational model is an alternati v e solution to o v ercome the se v ere area o v erhead in the v erier database [9]-[13]. Aghaie et al. [9] de v eloped a technique to b uild the computational model of delay-based PUFs by using an internal delay sensor kno wn as a time-do-digital con v erter (TDC) in FPGA. The sensor measures the delay of signals that pass through the switching components in delay-based PUF architecture. Subsequently , the measured delay is used to b uild the PUF computational model. Although the abo v e method reduces the number of CRPs to b uild the PUF computational model, the sensors remain on-chip, hence e xposing the de vice to be easily model ed by the adv ersaries. In other studies [10]-[13], the machine learning (ML) technique is used to model the PUF . Enormous CRPs are measured during the enrollment phase, and subsequently the PUF model is b uilt using ML technique based on the e xtracted CRPs. Else where, Idris et al. [14] de v eloped a lightweight authentication protocol that is b uilt using the PUF model. The usage of the PUF model in the v erier database and its ph ysical PUF in the pro v er de vice without an y protection mechanism is insecure, as an adv ersary can perform a modeling attack by coll ecting the e xposed CRPs. Hence, the protocol in [14] deplo ys secret pattern recognition to perform mutual authentication between the v erier and pro v er . In another study , Y ue et al. [15] proposed an authentication scheme in v olving the sequence of dynamic random acces s memory (DRAM) po wer -up v alues and con v olutional neural netw ork (CNN). Po wer -up v alues in memory are random and e xhibit de vice- specic features . CNN is deplo yed to model these unique features based on the DRAM po wer -up sequence that has been con v erted to a tw o-dimensional (2D) image structure. The proposed authentication scheme requires only the DRAM-PUF m o de l (i.e., unique feature) in the database. Ne v ertheless, deplo ying deep learning architecture such as CNN in the proposed authentication scheme requires a huge area as deep learning typically consists of a signicant number of layers and a comple x computational matrix. All of the abo v e studies sho w that deplo ying the PUF model in the database of v erier is getting the attention of the PUF research community . Ne v ertheless, the chose n ML technique must be able to b uild the PUF model in a cost-ef cient manner . Moreo v er , the pre vious studies only focusing on methodical approach (i.e., b uilding protocol of using PUF model) and/or simulation-le v el analysis only . Therefore, this study focuses on a PUF computational model de v elopment in Xilinx Artix-7 FPGA board using an articial neural netw ork (ANN) to enable lightweight authentication protocol in FPGA-based IoT applications. The PUF model accurac y , area and po wer consumption are e v aluated and discussed. FPGA implementation of articial neur al network for PUF modeling (Mohd Syaq Mispan) Evaluation Warning : The document was created with Spire.PDF for Python.
202 ❒ ISSN: 2089-4864 2. METHOD k -bit Arbit er -PUF [16], [17] is used as a case study for b uilding the computational model of PUF in FPGA. Figure 2 illustrates the top-le v el architecture of k -bit Arbiter -PUF . Arbiter -PUF is chosen in our study as it has a lightweight architecture [18] and k v alue is set to 32 to pro vide considerably enough process v ariations for Arbiter -PUF implementation in FPGA [19]. There are three major design steps in the de v elopment of PUF modeling in FPGA. First, the ph ysical Arbiter -PUF is implemented on FPGA follo wing the methods as described in [20]. Subsequently , random and unique challenges were generated using 32-bit linear -feedback shift re gister (LFSR) with a primiti v e polynomial of x 32 + x 31 + x 30 + x 10 + 1 and applied to the ph ysical Arbiter - PUF to generate the 1-bit corresponding responses. In total, 20,200 CRPs are e xtracted from the ph ysical Arbiter -PUF for b uilding the PUF model. Ar b ite r  (S R l atch)  A B Swit ch in g  Co m p o n e n t Inp u t c 1   =  0 c 2   =  1 c k   =  1 c k - 1   =  0 ∆ t Resp o n se  0  /  1 t o p 0 b o t 0 t o p 1 b o t 1 t o p k - 1 b o t k - 1 t o p k b o t k 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Figure 2. k -bit Arbiter -PUF architecture Based on the e xtracted CRPs, the ne xt step is to b uild the PUF model in a MA TLAB using the ANN technique. A 3-layer of ANN architecture is used, which consi sts of one input layer , one hidden layer with v e neurons, and one output layer . The number of neurons has been determined based on the rule of thumb described in [21]. Log-si gmoid function is used as an acti v ation in the hidden layers, which is gi v en as f ( x ) = 1 1+ e − x . F ollo wing [22], a resilient backpropag ation algorithm is used as the training algorithm as it pro vides f ast con v er gence time and optimum prediction accurac y . 20,000 CRPs are used as a training data set, and the remaining 200 CRPs are used as a test data set. The weightage and bias v alues from the successful trai ning of PUF modeling in MA TLAB are e xtracted for the subsequent design steps. The third design step is to implement the abo v e ANN architecture (i.e., with the e xtracted weight and bias v alues) in Xilinx system generator . Xilinx system generator is a MA TLAB Simulink add-on that enables the de v elopment of architecture-le v el FPGA designs using graphical block programming [23]. The design of the 32-bit Arbiter -PUF model in Xilinx system generator is subsequently con v erted into intellectual property (IP) core. Finally , the IP core, MicroBlaze core processor , and other peripherals are programmed into Xilinx Artix-7 FPGA using Xilinx V i v ado Design Suite to v alidate the functionality of the Arbiter -PUF model as compared to the ph ysical Arbiter -PUF . 3. RESUL TS AND DISCUSSION 3.1. Articial neural netw ork ar chitectur e As described in section 2, 32-bit Arbiter -PUF can be modeled by using ANN in which the ANN architecture consists of 3 layers which are input, hidden, and output layer . Figure 3 illustrates the top-le v el architecture of ANN in the Xilinx system generator en vironment. The number of i np ut at the input layer is equi v alent to k . The feature e xtraction is also implemented at the input layer to transform the inputs to parity v ectors [24]. The transformed inputs are fed to the hidden layer for the subsequent process. In the hidden layer , it consists of v e neurons. The e xtracted weightage and bias v alues from the ANN modeling in MA TLAB are applied in the Xilinx system generator en vironment for the computational of the neuron’ s output. The computati onal process in each neuron can be represented as x = Σ k i =1 w i c i + θ where x is the neuron’ s output, c is the i -th transformed input, w is the weightage, and θ is the bias v alue. Figure 4 depicts the partial computational block diagram to compute the neuron’ s output in the hidden layer . Block CMult is used to compute multiplication of w c and block AddSub is used to compute Σ . Int J Recongurable & Embedded Syst, V ol. 14, No. 1, March 2025: 200–207 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 203 Figure 3. T op-le v el of ANN architecture for modeling the 32-bit Arbiter -PUF Figure 4. P artial computational block diagram of each neuron in the hidden layer The output of each neuron, x is input to the log-sigmoid acti v ation function, which is gi v en as f ( x ) = 1 1+ e − x . The log-sigmoid acti v ation function bounds its output to the range of (0,1). According to T isan et al. [25], a piece wise second-order approximation is used i n our study to reduce the computational comple x- ity . Figure 5 illustrates the implementation of the log-sigmoid acti v ation functi on in Xilinx system generator . Meanwhile, Figure 6 depicts the graph comparison of an ideal log-sigmoid v ersus piece wise second-order ap- proximation. As can be seen, the approximation technique requires a bigger x v alue to bounds its output to the range of (0,1). FPGA implementation of articial neur al network for PUF modeling (Mohd Syaq Mispan) Evaluation Warning : The document was created with Spire.PDF for Python.
204 ❒ ISSN: 2089-4864 Figure 5. Computational block diagram of sigmoid acti v ation function − 60 − 40 − 20 0 20 40 60 0 0 . 2 0 . 4 0 . 6 0 . 8 1 x f(x) Piece wise approximation Ideal log-sigmoid Figure 6. Comparison of an ideal and approximation log-sigmoid acti v ation functions Subsequently , the acti v ated output is input to the third layer or output layer . Figure 7 illus trates the computational block diagram of an output layer . The computational process in the output layer can be represented as o = Σ n j =1 w j y j + θ where o is the output, y is equi v alent to f ( x ) (i.e., the acti v ated output), w is the weightage, θ is the bias v alue, and n is the total number of neurons. The output layer performs the classication process to classify the response ‘0’ and ‘1’. In the output layer , an additional block called a comparator is required to counteract the approximated computation of log-sigmoid functions. The des ign of 32-bit Arbiter -PUF model in Xilinx system generator which based on ANN architecture as discussed abo v e is con v erted into an IP core. Subsequently , the I P core, MicroBlaze core processor , and other peripherals are programmed into Xilinx Artix-7 FPGA as illustrated in Figure 8 for CRPs collection. Figure 7. Computational block diagram of an output layer Int J Recongurable & Embedded Syst, V ol. 14, No. 1, March 2025: 200–207 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 205 Figure 8. CRPs e xtraction using microblaze core processor 3.2. Modeling accuracy and ar ea consumption 20,000 CRPs are collected from the Arbiter -PUF model using the MicroBlaze core processor as con- gured in Figure 8. These CRPs are compared ag ainst the measured CRPs of ph ysical Arbiter -PUF . Figure 9 depicts the modeling accurac y of the Arbiter -PUF model. The number of CRPs is v aried from 400 CRPs up to 20,000 CRPs. The r esults sho w that the Arbiter -PUF model achie v es v ery high accurac y , approximately on a v erage 98%. T able 1 lists the area and po wer consumption of the Arbiter -PUF model. The area and po wer con- sumption of the PUF model is higher than the ph ysical PUF because of the comple xity of ANN architecture as compared to Arbiter -PUF architecture (see Figure 2). Based on these ndings, the Arbiter -PUF is suitable to be used in resource-constrained pro v ers as it consumes insignicant area o v erhead and po wer . The corresponding PUF model can be congured in the v erier to perform the authentication process. As discussed in section 1, storing the PUF model in the v erier signicantly reduces the area o v erhead as compared to storing CRPs for each PUF-based de vice. All the pre viously proposed techniques of using PUF model [9]-[15] as discussed in section 1 are methodical approach (i.e., b uilding protocol of using PUF model) and/or simulation-le v el analysis. Therefore, no comparison of the area o v erhead and po wer consumption can be made. The successful PUF model pro vides scalability in which an unlimited number of authentications can be performed by a pro v er as it is no longer limited by the number of CRPs stored in the v erier’ s database. 0 0 . 5 1 1 . 5 2 50 60 70 80 90 100 CRPs ( 10 4 ) Modeling Accurac y (%) Figure 9. Modeling accurac y of 32-bit Arbiter -PUF modelled using ANN technique T able 1. Area o v erhead and po wer consumption Unit block LUTs Po wer consumption (mW) Ph ysical arbiter -PUF 32 < 1 Arbiter -PUF model 12196 67 FPGA implementation of articial neur al network for PUF modeling (Mohd Syaq Mispan) Evaluation Warning : The document was created with Spire.PDF for Python.
206 ❒ ISSN: 2089-4864 4. CONCLUSION In this st udy , the 32-bit Arbiter PUF has been modeled using the ANN technique in MA TLAB and subsequently , the model is implemented on FPGA using Xilinx system generator and Xilinx V i v ado Design Suite. The FPGA implementation consumes 12196 LUTs, 67 mW po wer , and ≈ 98% accurac y . A successful implementation of the PUF model can replace the c o n v entional CRPs database in the v erier . The v erier consists of the ANN architecture and a database of weightage and biases of pro v ers. PUF model pro vides scalability in which an unlimited number of authentications can be performed by a pro v er . Future direction may focus on security enhancement of the v erier database to a v oid adv ersaries’ attacks on retrie ving the weightage/biases information. A CKNO WLEDGEMENT The authors w ould lik e to thank the Uni v ersiti T eknikal Malaysia Melaka and Ministry of Higher Ed- ucation Malaysia for the nancial funding of project completion. Grant No. FRGS/1/2020/TK0/UTEM/02/56. REFERENCES [1] M . Elna w a wy , A. F arhan, A. A. Nab ulsi, A. R. Al-Ali , and A. Sag ah yroon, “Role of FPGA in internet of things applica- tions, ” in IEEE International Symposium on Signal Pr ocessing and Information T ec hnolo gy , pp. 1-6, 2019, doi: 10.1109/IS- SPIT47144.2019.9001747. [2] A. Magyari and Y . Chen, “Re vie w of state-of-the-art FPGA applicati ons in IoT netw orks, ” Sensor s , v ol. 22, no. 19, pp. 1-18, 2022, doi: 10.3390/s22197496. [3] T . P . Dinh, C. Pham-Quoc, T . N. Thinh, B. K. D. Nguyen, and P . C. Kha, “A e xible and ef cient FPGA-based random forest architecture for IoT applications, ” Internet of Things , v ol. 22, pp. 1-14, 2023, doi: 10.1016/j.iot.2023.100813. [4] R. Mahmoud, T . Y ousuf, F . Aloul, and I. Zualk ernan, “Internet of things (IoT) security: Current status, challenges and prospecti v e measures, ” in International Confer ence for Internet T ec hnolo gy and Secur ed T r ansactions , pp. 336-341, 2016, doi: 10.1109/IC- ITST .2015.7412116. [5] M. S. Mispan, B. Halak, and M. Zw olinski, “A surv e y on the susceptibility of PUFs to in v asi v e, semi-in v asi v e and non-in v asi v e attacks: challenges and opportunities for future directions, ” J ournal of Cir cuits, Systems and Computer s , v ol. 30, no. 11, pp. 1-37, 2021, doi: 10.1142/S0218126621300099. [6] G. E. Suh and S. De v adas, “Ph ysical Unclonable Functions for de vice authentication and secret k e y generation, ” in A CM/IEEE Design A utomation Confer ence , pp. 9-14, 2007, doi: 10.1145/1278480.1278484. [7] J. Delv aux, R. Peeters, D. Gu, and I. V erbauwhede, “ A surv e y on lightwei ght entity authentication with strong PUFs, ” A CM Com- puting Surv e ys , v ol. 48, no. 2, pp. 1–42, No v . 2015, doi: 10.1145/2818186. [8] M. S. Mispan, A. Z. Jidin, M. R. Kamaruddin, and H. M. Nasir , “Proof of concept for lightweight PUF-based authentication protocol using NodeMCU ESP8266, ” Indonesian J ournal of Electrical Engineering and Computer Science , v ol. 24, no. 3, pp. 1392-1398, 2021, doi: 10.11591/ijeecs.v24.i3.pp1392-1398. [9] A. Aghaie, M. Ender , and A. Moradi, “PUFs ph ysical learning: accelerating the enrollment via delay-based model e xtraction, ” IEEE T r ansactions on Emer ging T opics in Computing , v ol. 10, no. 3, pp. 1621-1632, 2022, doi: 10.1109/TETC.2021.3115176. [10] A. Aghaie, M. Ender , and A. Moradi, “PUFs Ph ysical Learning: Accelerating the Enrollment via Delay-B ased Model Extraction, ” IEEE T r ansactions on Emer ging T opics in Computing , v ol. 10, no. 3, pp. 1621–1632, Jul. 2022, doi: 10.1109/TETC.2021.3115176. [11] A. Ali-Pour , F . Afghah, D. Hely , V . Beroulle, and G. Di Natale, “Secure PUF-based Authentication and K e y Exchange Protocol using Ma chine Learning, ” in Pr oceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI , IEEE, Jul. 2022, pp. 386–389, doi: 10.1109/ISVLSI54635.2022.00086. [12] M. S. E. Quadir and J. A. Chandy , “Embedded systems authentication and encryption using strong PUF modeling, ” in IEEE Inter - national Confer ence on Consumer Electr onics , pp. 1-6, 2020, doi: 10.1109/ICCE46568.2020.9043104. [13] Y . Y ilmaz, S. R. Gunn, and B. Halak, “Lightweight PUF-based authentication protocol for IoT de vices, ” in 2018 IEEE 3r d Interna- tional V erication and Security W orkshop, IVSW 2018 , pp. 38–43, 2018, doi: 10.1109/IVSW .2018.8494884. [14] T . A. Idriss, H. A. Idriss, and M. A. Bayoumi, “ A Lightweight PUF-Based Authentication Protocol Using Secret P attern Recognition for Constrained IoT De vices, ” IEEE Access , v ol. 9, pp. 80546–80558, 2021, doi: 10.1109/A CCESS.2021.3084903. [15] M. Y ue, N. Karimian, W . Y an, N. A. Anagnostopoulos, and F . T ehranipoor , “DRAM-Based Authentication Using Deep Con v olu- tional Neural Netw orks, ” IEEE Consumer Electr onics Ma gazine , v ol. 10, no. 4, pp. 8–17, 2021, doi: 10.1109/MCE.2020.3002528. [16] D. Lim, “Extracting secret k e ys from inte grated circuits, ” M.S. thesis, Massachusetts Instit ute of T echnology , Cambridge, United States, 2004. [17] J. W . Lee, D. Lim, B. Gassend, G. E. Suh, M. V an Dijk, and S. De v adas, “ A technique to b uild a secret k e y in inte grated circuits for identication and authentication applications, ” IEEE Symposium on VLSI Cir cuits, Dig est of T ec hnical P aper s , pp. 176–179, 2004, doi: 10.1109/vlsic.2004.1346548. [18] A. Babaei and G. Schiele, “Ph ys ical unclonable functions in the internet of things: State of the art and open challenges, ” Sensor s (Switzerland) , v ol. 19, no. 14, pp. 1–18, Jul. 2019, doi: 10.3390/s19143208. [19] T . Xu, “Digital ph ysical unclonable functions : architecture and applications, ” M.S. thesis, Uni v ersity of California, 2014. [20] M. H. Ishak, M. S. Mispan, W . Y . Chie w , M. R. Kamaruddin, and M. A. K orobk o v , “Secure lightweight obfuscated delay-based ph ysical unclonable function design on FPGA, ” Bulletin of Electrical Engineering and Informatics , v ol. 11, no. 2, pp. 1075–1083, Apr . 2022, doi: 10.11591/eei.v11i2.3265. [21] J. Heaton, Intr oduction to neur al networks for J ava, 2nd Edition , 2nd ed. Heaton Research, Inc., 2008. Int J Recongurable & Embedded Syst, V ol. 14, No. 1, March 2025: 200–207 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 207 [22] J. Mathe w , R. S. Chakraborty , D. P . Sahoo, Y . Y ang, and D. K. Pradhan, “ A no v el memristor -based hardw are security primiti v e, ” A CM T r ansactions on Embedded Computing Systems , v ol. 14, no. 3, pp. 1–20, May 2015, doi: 10.1145/2736285. [23] Xilinx, V ivado design suite tutorial - model-based DSP design using system g ener ator , 2020. [24] Y . Gao et al., “Obfuscated challenge-response: A secure lightweight authenti cation mechanism for PUF-based perv asi v e de vices, ” in 2016 IEEE International Confer ence on P ervasive Computing and Communication W orkshops, P erCom W orkshops 2016 , IEEE, Mar . 2016, pp. 1–6, doi: 10.1109/PERCOMW .2016.7457162. [25] A. T isan, S. Onig a, D. MIC, and A. Buchman, “ Digital implementation of the sigmoid function for FPGA circuit s, ” Acta T ec hnica Napocensis , v ol. 50, no. 2, pp. 15-20, 2009. BIOGRAPHIES OF A UTHORS Mohd Syaq Mispan recei v ed B.Eng. electrical (electronics) and M.Eng. electrical (computer and microelectronic system) from Uni v ersi ti T eknologi Malaysia, Malaysia in 2007 and 2010 respecti v ely . He had e xperienced w orking in semiconductor industries from 2007 until 2014 before pursuing hi s Ph.D. de gree. He obtained his Ph.D. de gree in electronics and electrical engi- neering from Uni v ersity of Southampton, United Kingdom in 2018. He is currently a senior lecturer in F aculty of Electronics and Computer T echnology and Engineering, Uni v ersiti T eknikal Malaysia Melaka. His current research interests incl ude hardw are security , CMOS reliability , VLSI design, and electronic systems design. He can be contacted at email: syaq.mispan@utem.edu.my . Mohammad Haziq Ishak recei v ed B.Eng. electronics from Uni v ersiti T eknikal Malaysia Melaka, Malaysia in 2021. He is w orking to w ard tw oshe M.Sc. de gree in electronics engineering with the Uni v ersiti T eknikal Malaysia Melaka (UT eM). His M.Sc. de gree research is focusing on the implementation of a lightweight authentication scheme using ph ysical unclonable function for FPGA-based IoT applications. He can be contacted at email: haziqsepd@gmail.com. Aiman Zakwan Jidin is currently a Ph.D. candidate at Uni v ersiti Malaysia Perli s, Malaysia. His research topic is focusing on optimizing memory testing algorithm ef cienc y for im- pro ving f ault co v erage. Pre viously , he obtained his M.Eng. in electronic and microelectronic system from ESIEE Engineering P aris, France in 2011, before w orking as FPGA IP Core Design Engineer at Altera Corporation Malaysia (no w part of Intel). He is a full-time lecturer and researcher at Uni- v ersiti T eknikal Malaysia Melaka (UT eM), in electronic and computer engineering. His research interests include DFT , VLSI, and FPGA system design. He can be contacted at email: aimanzak- w an@utem.edu.my . Haslinah Mohd Nasir recei v ed her bachel or de gree in electrical - electronic engineer - ing (2008) from Uni v ersiti T eknologi Malaysia (UTM), M.Sc. (2016) and Ph.D. (2019) in elec- tronic engineering from Uni v ersiti T eknikal Malaysia Melaka (UT eM). She had 5 years (2008-2013) e xperience w orking in industry and currently a lecturer in UT eM. Her research interest includes microelectronics, articial intelligence, and biomedical. She can be contacted at email: hasli- nah@utem.edu.my . FPGA implementation of articial neur al network for PUF modeling (Mohd Syaq Mispan) Evaluation Warning : The document was created with Spire.PDF for Python.