Inter
national
J
our
nal
of
P
o
wer
Electr
onics
and
Dri
v
e
System
(IJPEDS)
V
ol.
16,
No.
3,
September
2025,
pp.
1417
∼
1428
ISSN:
2088-8694,
DOI:
10.11591/ijpeds.v16.i3.pp1417-1428
❒
1417
Optimization
of
tw
o-stage
DTMOS
operational
transconductance
amplier
with
Fir
ey
algorithm
Udari
Gnaneshwara
Chary
1,2
,
Swathi
Mummadi
3
,
Kakarla
Hari
Kishor
e
1
1
Department
of
Electronics
and
Communication
Engineering,
K
oneru
Lakshmaiah
Education
F
oundation,
V
addesw
aram,
India
2
Department
of
Electronics
and
Communication
Engineering,
B
V
Raju
Institute
of
T
echnology
,
Narsapur
,
India
3
Department
of
Computer
Science
and
Engineering,
B
V
Raju
Institute
of
T
echnology
,
Narsapur
,
India
Article
Inf
o
Article
history:
Recei
v
ed
Dec
18,
2024
Re
vised
Apr
5,
2025
Accepted
May
25,
2025
K
eyw
ords:
DTMOS
Firey
algorithm
O
T
A
Po
wer
analysis
T
w
o-stage
operational
transconductance
ampliers
ABSTRA
CT
This
paper
presents
a
methodology
for
optimizing
dynamic
threshold
MOSFET
(DTMOS)
tw
o-stage
operational
transconductance
ampliers
(O
T
As)
tailored
for
biomedical
applications
through
the
utilization
of
the
Firey
algorithm.
The
optimization
process
focuses
on
enhancing
k
e
y
performance
metrics
such
as
g
ain,
bandwidth,
and
po
wer
ef
cienc
y
,
which
are
critical
for
biomedical
signal
processing,
neur
al
interf
aces,
and
wearable
healthcare
de
vices.
The
methodology
encompasses
circuit
architecture
denition,
Firey
algorithm
implementation,
tness
e
v
aluation,
and
result
analysis.
The
optimization
results
re
v
eal
a
signicant
enhancement
in
performance
metrics.
Specically
,
the
number
of
transistors
in
the
design
is
25.
The
initial
o
v
erall
g
ain
w
as
76.65
V/V
,
with
a
po
wer
ef
cienc
y
(
µ
)
of
1.6.
After
optimization,
the
o
v
erall
g
ain
w
as
signicantly
impro
v
ed
to
84.029
dB
using
the
Firey
algorithm,
demonstrating
superior
performance
compared
to
e
xi
sting
algorithms.
The
po
wer
ef
cienc
y
(
µ
)
w
as
also
enhanced
to
1.702,
underscoring
the
ef
cienc
y
impro
v
ements
achie
v
ed
through
optimization.
Simulation
results
and
statistical
analysis
conrm
that
the
Firey
algorithm
ef
fecti
v
ely
achie
v
es
opt
imal
congurations,
impro
ving
the
rob
ustness
of
O
T
A
designs
ag
ainst
parameter
v
ariat
ions.
These
enhancements
v
alidate
the
algorithm’
s
ef
cac
y
in
addressing
po
wer
-performance
trade-of
fs
and
its
suitability
for
di
v
erse
biomedical
applications.
Ph
ysical
prototyping
of
the
optimized
design
further
demonstrates
real-w
orld
functionality
,
underscoring
its
practical
applicability
.
This
is
an
open
access
article
under
the
CC
BY
-SA
license
.
Corresponding
A
uthor:
Kakarla
Hari
Kishore
Department
of
Electronics
and
Communication
Engineering,
K
oneru
Lakshmaiah
Education
F
oundation
V
addesw
aram,
Guntur
,
Andhra
Pradesh
522302,
India
Email:
kakarla.harikishore@kluni
v
ersity
.in
1.
INTR
ODUCTION
Operational
transconductance
ampliers
(O
T
As)
are
fundamental
components
in
analog
int
e
gra
ted
circuits,
playing
a
vital
role
in
v
arious
applications,
including
biomedical
signal
processing,
neural
interf
aces,
and
implantable
medical
de
vices.
The
optimization
of
DTMOS
tw
o-stage
O
T
As
for
biomedical
applications
has
been
an
area
of
acti
v
e
research,
with
a
focus
on
impro
ving
performance
metrics
such
as
g
ain,
bandwidth,
po
wer
consumption,
and
area
ef
cienc
y
.
This
literature
re
vie
w
pro
vides
an
in-depth
analysis
of
the
related
w
ork
and
recent
adv
ancements
in
O
T
A
optimization,
specically
for
biomedical
applications
using
the
Firey
Algorithm.
S
e
v
era
l
bio-inspired
optimization
techniques
ha
v
e
been
applied
to
O
T
A
sizing
and
parameter
optimization.
The
authors
F
ortes
et
al.
[1]
e
xplored
t
h
e
use
of
bio-inspired
algorithm
s,
such
as
genetic
J
ournal
homepage:
http://ijpeds.iaescor
e
.com
Evaluation Warning : The document was created with Spire.PDF for Python.
1418
❒
ISSN:
2088-8694
algorithms
and
particle
sw
arm
optimization,
for
tw
o-stage
O
T
A
sizing
optimization.
Their
study
demonstrated
the
ef
fecti
v
eness
of
bio-inspired
algorithms
in
achie
ving
impro
v
ed
O
T
A
performance,
including
higher
g
ain
and
lo
wer
po
wer
consumption.
Hybrid
optimization
approaches
ha
v
e
g
ained
popularity
in
recent
years
due
to
their
ability
to
combine
the
strengths
of
multiple
optimization
algorithms.
Laskar
et
al.
[2]
introduced
the
HWPSO
algorithm,
a
h
ybrid
whale-particle
sw
arm
optimization
approach
applied
to
electronic
design
optimization
problems,
including
O
T
A
sizing
optimization.
This
h
ybrid
algorithm
sho
wed
promising
results
in
achie
ving
optimal
O
T
A
congurations
for
biomedical
applications.
Researchers
ha
v
e
focused
on
de
v
eloping
no
v
el
design
methodologies
with
the
increasing
demand
for
lo
w-po
wer
and
area-ef
cient
O
T
As
in
portable
and
wearable
biomedical
de
vices.
In
[3]-[6]
proposed
an
ultra-lo
w
po
wer
and
area-ef
cient
O
T
A
design
specically
tailored
for
portable
and
wearable
applications.
Their
w
ork
addressed
the
challenges
of
po
wer
consumption
and
area
cons
traints,
making
it
suitable
for
compact
and
ener
gy-ef
cient
wearable
de
vices.
The
study
[7]-[9]
presented
a
no
v
el
O
T
A
design
methodology
,
which
is
designed
specically
for
implantable
medical
de
vices.
This
methodology
considered
the
unique
requirements
of
implantable
applications,
such
as
lo
w
po
wer
consumption,
high
rel
iability
,
and
compatibility
with
implantable
sensors.
The
study
emphasized
the
importance
of
application-specic
design
approaches
in
optimizing
O
T
As
for
biomedical
applications.
The
remaining
paper
is
outlined
as
follo
ws:
i)
Section
2
talks
about
the
e
xisting
state-of-the-art
w
orks;
ii)
Section
3
discusses
the
proposed
design
of
the
DTMOS
tw
o-st
age
operational
transconductance
amplier;
iii)
Section
4
e
xplains
the
proposed
AI
based
optimization
for
DTMOS
O
T
A;
i
v)
Section
5
demonstrates
the
result
analysis
of
the
proposed
w
ork;
and
v)
Finally
,
the
paper
is
concluded
in
section
6.
2.
B
A
CKGR
OUND
W
ORK
The
design
and
optimization
of
operational
transconductance
ampliers
(O
T
As)
remain
a
cri
tical
area
of
research
in
analog
and
mix
ed-signal
circuit
design
due
to
their
e
xtensi
v
e
applications
in
lters,
analog-to-digital
con
v
erters,
and
other
signal
processing
systems.
Among
v
arious
O
T
A
congurations,
the
tw
o-stage
design
is
particularly
popular
for
its
ability
to
achie
v
e
high
g
ain
and
wide
output
swing.
Ho
we
v
er
,
con
v
entional
tw
o-stage
O
T
As
often
encounter
trade-of
fs
between
po
wer
ef
cienc
y
,
g
ain,
bandwidth,
and
linearity
,
posing
signicant
challenges
for
modern
lo
w-po
wer
,
high-performance
applicati
o
ns
.
Dynamic
threshold
MOS
(DTMOS)
technology
has
emer
ged
as
a
promising
solution
to
these
challenges,
particularly
in
lo
w-v
oltage
en
vironments.
By
dynamically
v
arying
the
threshold
v
oltage,
DTMOS
de
vices
enable
enhanced
transconductance
and
reduced
subthreshold
leakage,
making
them
suitable
for
ener
gy-ef
cient
analog
circuits
[10].
Despite
these
adv
antages,
optimizing
DTMOS-based
O
T
As
in
v
olv
es
na
vig
ating
a
high-dimensional
design
space
with
nonlinear
relationships
between
circuit
parameters.
T
raditional
optimization
techniques,
such
as
gradient-based
methods,
often
f
all
short
in
handling
such
comple
xity
and
may
con
v
er
ge
to
suboptimal
solutions.
In
this
conte
xt,
bio-inspired
optimization
algorithms,
such
as
the
Firey
algorithm
(F
A),
of
fer
a
rob
ust
alternati
v
e
for
circuit
design
optimization.
F
A,
inspired
by
the
ashing
beha
vior
of
reies,
is
particularly
ef
fecti
v
e
in
handling
multi-obj
ecti
v
e
and
non-linear
optimization
problems.
The
algorithm
emplo
ys
a
sw
arm-based
approach
where
reies
are
attracted
to
brighter
ones
based
on
their
objecti
v
e
function
v
alues,
leading
to
the
e
xploration
of
promising
re
gions
in
the
solution
space.
This
characteristic
mak
es
F
A
well-suited
for
optimizing
analog
circuit
parameters,
where
objecti
v
es
lik
e
po
wer
consumption,
g
ain,
bandwidth,
and
phase
mar
gin
must
be
balanced.
Pre
vious
studies
ha
v
e
demonstrated
the
ef
cac
y
of
F
A
in
di
v
erse
applications,
including
lter
design,
VLSI
layout
optimization,
and
RF
circuit
tuning,
highlighting
its
potential
in
analog
design
automation.
F
or
instance,
Khan
et
al.,
[11]
emplo
yed
F
A
to
optimize
lo
w-noise
amplier
design,
achie
ving
signicant
performance
impro
v
ements
compared
to
con
v
entional
methods.
Similarly
,
the
w
ork
[12]
sho
wcased
the
application
of
F
A
in
tuning
PID
controllers
for
enhanced
system
stability
.
The
w
ork
in
[13]
focused
on
optimizing
DTMOS
O
T
As
for
lo
w-po
wer
biomedical
signal
processing
using
the
Firey
algorithm.
Their
study
demonstrated
signicant
impro
v
ements
in
O
T
A
performance
metrics,
including
reduced
po
wer
consumption
without
compromising
signal
quality
.
The
study
[14]
pro
vided
a
comprehensi
v
e
re
vie
w
of
bioinspired
optimization
algorithms,
discussing
their
applications
in
microelectronics
and
nanophotonics,
including
O
T
A
optimization.
Their
re
vie
w
shed
light
on
the
benets
and
challenges
of
using
bio-inspired
algorithms
in
optimizing
CMOS
O
T
As.
Additionally
,
the
w
ork
[15]
e
xplored
ef
cient
O
T
A
des
ign
for
wearable
health
monitoring
de
vices,
addressing
po
wer
and
area
ef
cienc
y
for
wearable
applications.
Shah
et
al.
[16]
proposed
an
ef
cient
method
for
optimizing
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
16,
No.
3,
September
2025:
1417–1428
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
❒
1419
O
T
As
specically
tailored
for
im
plantable
periprosthetic
de
vices.
Their
s
tudy
focused
on
achie
ving
lo
w-po
wer
consumption
and
high
g
ain
in
O
T
As
to
enhance
the
performance
of
implantable
periprosthetic
systems.
The
optimization
technique
demonstrated
in
this
w
ork
contrib
utes
to
the
adv
ancement
of
neuroproteins
for
medical
applications.
The
result
[17]-[19]
utilized
the
Firey
algorithm
for
optimizing
CMOS
O
T
As
specically
des
igned
for
wearable
electrocardiogram
(ECG)
monitoring
systems.
Their
w
ork
focused
on
achie
ving
high
performance,
lo
w
po
wer
consumption,
and
area
ef
cienc
y
in
O
T
As
to
enhance
the
reliability
and
usability
of
wearable
ECG
monitoring
de
vices.
The
application-specic
optimization
using
the
Firey
algorithm
sho
wcased
impro
v
ements
in
O
T
A
de
sign
for
wearable
healthcare
systems.
The
w
ork
[20]
presented
a
design
and
optimization
methodology
for
lo
w-po
wer
O
T
As
using
the
trans-linear
principle,
specically
applied
to
neural
signal
amplication
in
rehabilitation
engineering.
Their
study
focused
on
optimizing
O
T
As
for
amplifying
neural
signals
with
minimal
po
wer
consumption
while
maintaining
high
delity
.
The
inno
v
ati
v
e
design
approach
and
optimization
techniques
contrib
ute
to
enhancing
neural
signal
processing
in
rehabilitation
applications.
The
st
u
dy
[21],
[22]
introduced
a
h
ybrid
optimization
strate
gy
combining
the
Firey
algorithm
and
particle
sw
arm
optim
ization
(PSO)
for
sizing
CMOS
O
T
As
in
biomedical
de
vices.
The
presented
w
ork
focused
on
achie
ving
optimal
O
T
A
congurations
wi
th
impro
v
ed
g
ain,
bandwidth,
and
po
wer
ef
cienc
y
for
biomedical
signal
processing
applications.
The
h
ybrid
optimization
approach
sho
wcased
enhancements
i
n
O
T
A
performance
for
biomedical
de
vices
[23],
[24].
The
related
w
ork
and
literature
re
vie
w
highlight
the
di
v
erse
approaches
[25],
[26]
and
methodologies
emplo
yed
in
optimizing
CMOS
tw
o-stage
O
T
As
for
biomedical
applications.
From
bio-inspired
algorithms
and
h
ybrid
optimization
approaches
to
lo
w-po
wer
and
area-ef
cient
O
T
A
designs,
researchers
continue
to
adv
ance
the
eld,
addressing
the
unique
challenges
of
biomedical
signal
processing,
wearable
de
vices,
and
implantable
medical
de
vices
[27]-[30].
The
inte
gration
of
F
A
into
the
optimization
process
of
DTMOS-based
tw
o-stage
O
T
As
necessitates
a
comprehensi
v
e
understanding
of
both
the
algorithm’
s
dynamics
and
the
circuit’
s
performance
metrics.
The
design
process
be
gins
with
dening
a
multi-objecti
v
e
cost
function
encompassing
critical
parameters
lik
e
unity-g
ain
bandwidth
(UGBW),
total
harmonic
distortion
(THD),
sle
w
rate
(SR),
and
po
wer
consumption.
The
constraints
imposed
by
DTMOS
technology
,
such
as
v
oltage
headroom
and
leakage
considerations,
further
complicate
the
optimization
landscape
[31].
Unlik
e
con
v
entional
MOSFETs,
DTMOS
de
vices
operate
with
a
body-source
bias
dynamically
adjusted
based
on
the
input
signal,
thereby
requiring
precise
modeling
to
predict
their
beha
vior
accurately
.
The
w
ork
of
[32]-[34]
highlights
the
importance
of
incorporating
adv
anced
de
vice
models
for
v
arious
circuits
to
ensure
optimization
accurac
y
.
T
o
e
v
aluate
the
ef
fecti
v
eness
of
F
A
in
this
domain,
a
thorough
comparison
with
other
metaheuris
tic
algorithms,
such
as
genetic
algorithms
(GA)
and
particle
sw
arm
optimization
(PSO),
is
essential.
While
GAs
e
xcel
in
maintaining
population
di
v
ersity
and
a
v
oiding
premature
con
v
er
gence,
their
computational
o
v
erhead
often
limits
their
applicability
in
time-sensiti
v
e
design
tasks.
On
the
other
hand,
PSO
is
kno
wn
for
i
ts
simplicity
and
f
ast
con
v
er
gence
b
ut
may
struggle
with
local
optima
in
comple
x
landscapes
[35].
F
A
strik
es
a
balance
between
these
approaches,
of
fering
adaptability
through
its
light
intensity-based
attraction
mechanism.
Recent
adv
ancements
in
F
A,
such
as
h
ybri
dization
with
local
search
techniques
and
adapti
v
e
para
meter
tuning,
further
enhance
its
capability
for
high-dimensional
problems.
The
proposed
methodology
for
optimizing
the
tw
o-stage
DTMOS
O
T
A
in
v
olv
es
setting
up
a
simulation
en
vironment
using
the
industry-standard
tool
Synopsys
HSPICE.
The
DTMOS-based
O
T
A
is
designed
with
an
initial
parameter
set
deri
v
ed
fr
o
m
analytical
models
and
prior
designs.
F
A
is
t
hen
emplo
yed
to
iterati
v
ely
rene
these
parameters,
with
each
iterati
on
in
v
olving
circuit
simulation
to
e
v
aluate
the
cost
function.
The
optimization
loop
continues
until
con
v
er
gence
criteria,
such
as
minimal
cost
function
v
alue
or
maximum
iteration
count,
are
met.
Post-optimization,
the
O
T
A
’
s
performance
is
v
alidated
ag
ainst
industry
benchmarks
to
ensure
compliance
with
application-specic
requirements.
Comparati
v
e
studies
with
baseline
designs
optimized
using
con
v
enti
onal
methods
are
conducted
to
quantify
the
impro
v
ements
achie
v
ed
through
F
A.
The
adoption
of
F
A
in
optimizing
tw
o-stage
DTMOS
O
T
As
aligns
with
broader
trends
in
el
ectronic
design
automation
(ED
A),
emphasizing
intelligent
algorithms
for
ne
xt-generation
circuit
design.
By
addressing
the
limitations
of
traditional
methods
and
le
v
eraging
the
unique
features
of
bio-inspired
a
lgorithms,
this
approach
has
the
potential
to
set
ne
w
standards
for
analog
circuit
performance
in
lo
w-po
wer
and
high-speed
domains.
Further
research
may
focus
on
e
xtending
this
methodology
to
other
adv
anced
technologies,
such
as
FinFETs
and
carbon
nanotube
transistors,
thereby
broadening
its
applicability
in
the
e
v
olving
semiconductor
Optimization
of
two-sta
g
e
DTMOS
oper
ational
tr
ansconductance
amplier
...
(Udari
Gnaneshwar
a
Chary)
Evaluation Warning : The document was created with Spire.PDF for Python.
1420
❒
ISSN:
2088-8694
landscape.
3.
METHOD
Operational
transconductance
ampliers
(O
T
As)
are
fundamental
b
uilding
blocks
in
analog
inte
grated
circuit
design,
crucial
for
v
arious
applications
such
as
lters,
oscillators,
and
ampliers.
W
ith
the
gro
wing
demand
for
lo
w-po
wer
,
high-performance
circuits,
the
design
of
O
T
As
has
become
increasingly
challenging.
Dynamic
threshold
MOSFET
(DTMOS)
technology
of
fers
adv
antages
such
as
lo
wer
threshold
v
oltage
and
impro
v
ed
subthreshold
characteristics,
making
it
an
attr
acti
v
e
choice
for
lo
w-po
wer
analog
designs.
Therefore,
we
designed
a
no
v
el
DTMOS-based
tw
o-stage
O
T
A.
The
proposed
DTMOS
O
T
A
circuit
diagrams
is
depicted
in
Figure
1.
This
circuit
consist
of
a
dif
ferential
stage,
wide
range
current
mirrors,
a
tuning
stage,
with
output
swing
stage
with
a
g
ain
impro
v
ement
circuit.
Figure
1.
Schematic
diagram
of
DTMOS
tw
o-stage
O
T
A
3.1.
Differ
ential
stage
with
DTMOS
inputs
Dif
ferential
stages,
the
heart
of
op-amps,
amplify
the
dif
ference
between
tw
o
input
signals.
T
raditionally
,
these
s
tages
rely
on
MOSFETs.
Ho
we
v
er
,
dynamic
threshold
v
oltage
MOSFET
(DTMOS)
transistors
of
fer
an
attracti
v
e
alternati
v
e,
especial
ly
for
lo
w-v
oltage
circuits.
DTMOS
transistors
boast
a
wider
input
common-mode
range
due
to
their
unique
structure.
This
allo
ws
them
to
handle
a
lar
ger
swing
in
input
v
oltages
without
af
fecting
the
dif
ferential
g
ain,
a
signicant
benet
in
lo
w-v
oltage
applications.
Additionally
,
DTMOS
transistors
outperform
MOSFETs
at
lo
w
v
oltages,
making
them
ideal
for
po
wer
-ef
cient
designs.
These
adv
antages
translate
to
practical
applications.
DTMOS
dif
ferential
stages
pa
v
e
the
w
ay
for
lo
w-v
oltage
op-amps,
crucial
for
battery-po
wered
de
vices.
Moreo
v
er
,
their
wider
input
common-mode
range
mak
es
them
suitable
for
high-g
ain
dif
ferential
ampliers
where
strong
signal
amplication
and
noise
rejection
are
essential.
DTMOS
dif
ferential
stages
represent
a
leap
forw
ard
in
analog
circuit
des
ign.
Their
ability
to
handle
a
broader
v
oltage
range
and
perform
well
at
lo
w
v
oltages
mak
es
them
v
aluable
for
v
arious
applications.
3.2.
W
ide
range
curr
ent
mirr
or
cir
cuit
A
current
mirror
is
a
fundamental
analog
circuit
block
that
replicates
a
current
from
an
input
terminal
to
an
output
terminal.
A
simple
current
mirror
has
limitations
which
are
lo
w
output
impedance
and
restricted
output
v
oltage
swing.
The
wide-range
cascode
current
mirror
ele
v
ates
the
performance
of
the
basic
cascode
design
by
achie
ving
both
high
output
impedance
and
a
wider
output
v
oltage
swing.
This
is
accomplished
through
a
cle
v
er
biasing
scheme
that
le
v
erages
the
strengths
of
the
cascode
structure.
The
output
v
oltage
swing
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
16,
No.
3,
September
2025:
1417–1428
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
❒
1421
of
a
standard
cascode
design
is
constrained,
despite
its
high
output
impedance.
T
o
o
v
ercome
the
limitation,
the
wide-r
ange
v
ersion
adds
a
third
transistor
that
is
used
just
for
biasing.
The
designer
ef
fecti
v
ely
adjusts
the
v
oltage
drop
across
the
cascode
stack
by
carefully
adjusting
the
g
ate
v
oltage
of
this
biasing
transistor
.
This
allo
ws
the
output
v
oltage
to
swing
much
closer
to
the
supply
v
oltage
without
compromising
the
high
output
impedance.
This
additional
layer
of
biasing
comple
xit
y
unlocks
the
signicant
adv
antage
of
a
wider
output
v
oltage
swing,
enabling
the
mirror
to
operate
o
v
er
a
lar
ger
range
of
currents
while
still
preserving
the
high
output
impedance
characteristic
of
the
cascode
design.
3.3.
T
uning
stage
The
tuning
circuits
are
essential
components
of
DTMOS
op
amps
constructed
with
DTMOS
transistors.
The
y
pro
vide
numerous
major
adv
antages.
One
signicant
adv
antage
is
stability
.
Op-amps
ha
v
e
high
g
ain
b
ut
limited
bandwidth,
which
can
cause
oscillations.
T
uning
circuits,
which
frequently
include
capacitors,
implement
re
gulated
g
ain
roll-of
f,
pre
v
enting
this
instability
.
The
y
also
assist
in
re
gulating
the
g
ain-bandwidth
trade-of
f,
allo
wing
for
desired
g
ain
within
a
gi
v
en
frequenc
y
range.
T
uning
circuits
can
also
af
fect
settling
time
and
s
le
w
rate,
which
are
both
critical
in
quick-response
applications.
In
certain
circumstances,
the
y
e
v
en
increase
common-mode
rejection,
or
the
capacity
to
lter
out
unw
anted
noise.
By
carefully
constructing
these
circuits,
op-amp
designers
may
reach
peak
performance
in
certain
applications.
3.4.
Output
swing
and
gain
stage
An
operational
amplier
(op-amp)
amplies
the
v
oltage
dif
ference
between
its
inputs,
b
ut
its
ou
t
put
can
only
swing
in
a
certain
range.
This
range,
kno
wn
as
the
output
swing,
is
dened
as
the
highes
t
and
lo
west
v
oltage
limitations
that
the
output
may
achie
v
e
while
rem
aining
in
linear
functioning.
It
is
critical
to
consider
both
t
he
output
swing
and
the
op-amp’
s
g
ain
(amplication
le
v
el).
If
the
g
ain
is
set
too
hi
gh
for
the
a
v
ailable
swing,
the
output
signal
will
distort
as
it
attempts
to
surpass
the
limitations.
The
g
ain
stage
ef
fecti
v
ely
amplies
the
signal,
b
ut
the
output
swing
serv
es
as
a
ceiling,
limiting
the
maximum
increased
output
v
oltage.
Understanding
and
re
gulating
the
output
swing
allo
ws
us
to
create
op-amp
circuits
that
generate
clean,
amplied
signals
without
distortion.
A
dynamic
threshold
MOSFET(DTMOS)
based
tw
o-stage
operational
transconductance
am
p
l
ier
circuit
is
con
v
erted
to
a
netlist
le
with
an
e
xtension
“.sp”.
The
netlist
le
is
gi
v
en
belo
w:
m23
v
out
net90
net9
net9
p12
w=2.1u
l=0.1u
nf=2.0
m=1
m22
net9
net90
vdd
vdd
p12
w=1.05u
l=0.1u
nf=1.0
m=1
m7
net70
net82
vdd
vdd
p12
w=0.12u
l=0.1u
nf=1.0
m=1
m8
net82
net82
vdd
vdd
p12
w=0.12u
l=0.1u
nf=1.0
m=1
m9
net60
net82
vdd
vdd
p12
w=1.05u
l=0.1u
nf=1.0
m=1
m1
net23
vinp
net84
vinp
p12
w=0.12u
l=0.1u
nf=1.0
m=1
m2
vss
vinp
net84
vinp
p12
w=0.12u
l=0.1u
nf=1.0
m=1
m3
vss
vinn
net50
vinn
p12
w=1.05u
l=0.1u
nf=1.0
m=1
m4
net15
vinn
net50
vinn
p12
w=4.2u
l=0.1u
nf=4.0
m=1
m16
net16
vbias
vdd
vbias
p12
w=0.12u
l=0.1u
nf=1.0
m=1
m18
net13
net15
vdd
vdd
p12
w=0.36u
l=0.1u
nf=1.0
m=1
m14
net20
net20
net60
net60
p12
w=0.96u
l=0.1u
nf=1.0
m=1
m12
net84
net20
net60
net60
p12
w=0.12u
l=0.1u
nf=1.0
m=1
m13
net50
net20
net60
net60
p12
w=0.24u
l=0.1u
nf=1.0
m=1
m19
net99
net15
net13
net13
p12
w=0.48u
l=0.1u
nf=1.0
m=1
m24
v
out
net99
net11
net11
n12
w=1.44u
l=0.1u
nf=3.0
m=1
m25
net11
net99
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m11
net82
net70
vss
vss
n12
w=0.72u
l=0.1u
nf=1.0
m=1
m10
net70
net70
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m5
net23
net18
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m6
net15
net18
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m21
net14
net16
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m17
net16
net16
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m15
net20
vtune
vss
vss
n12
w=0.12u
l=0.1u
nf=1.0
m=1
m20
net99
net16
net14
net14
n12
w=0.12u
l=0.1u
nf=1.0
m=1
Optimization
of
two-sta
g
e
DTMOS
oper
ational
tr
ansconductance
amplier
...
(Udari
Gnaneshwar
a
Chary)
Evaluation Warning : The document was created with Spire.PDF for Python.
1422
❒
ISSN:
2088-8694
The
circuit
operates
with
a
supply
v
oltage
of
0.4
V
and
the
input
signals
are
v
oltages
of
0.2
V
.
The
design
in
Figure
1
uses
M1,
M2,
M3,
and
M4
as
its
dif
ferential
input
pair
and
is
dri
v
en
by
current
mirror
circuits
denoted
by
M5
and
M6.
The
transistors
M7,
M8,
M9,
M10,
and
M11
together
form
the
wide
range
cascode
current
mirror
circuit.
The
Iref
through
the
M7
and
M8
is
copied
to
the
M9
transistor
and
then
it
is
applied
to
the
dif
ferential
pair
.
The
transistors
M12,
M13,
M14,
and
M15
mak
e
up
the
tuning
circuitry
.
The
dif
ferential
input
pair
current
is
duplicated
in
the
MOSFETs
M4
and
M6
thanks
to
the
connection
between
the
drain
and
g
ate
terminals
of
these
MOSFETs.
The
transistors
M16
to
M21
are
used
for
preserving
the
high
swing,
while
the
transistors
M22
to
M25
are
used
for
producing
the
high
g
ain.
The
proposed
circuit
is
suitable
for
high-
and
lo
w-frequenc
y
applications
and
is
con
v
enient
for
biomedical
applications.
4.
PR
OPOSED
AI-B
ASED
OPTIMIZA
TION
The
proposed
methodology
to
optimize
DTMOS-based
O
T
A
circuits
using
the
Firey
algorithm
is
sho
wn
in
Figure
2.
As
in
Figure
2,
the
proposed
methodology
systematically
optimizes
DTMOS-based
O
T
A
circuits
using
the
Firey
algorithm.
It
in
v
olv
es
four
stages:
i)
DTMOS
circuit
design
and
netlist
generation,
ii)
nding
transistor
parameters,
iii)
applying
the
Firey
optimization
algorithm,
and
i
v)
obtaining
optimi
zed
O
T
A
parameters.
Circuit
modeling:
where
DTMOS
transistors
replace
passi
v
e
components;
algorithm
adaptation,
emplo
ying
the
Firey
algorithm
with
DTMOS-specic
constraints;
implementation
details,
initi
alizing
reies
and
dening
an
objecti
v
e
function
for
iterati
v
e
adjustments
of
transistor
dimensions;
and
performance
e
v
aluation,
assessing
metrics
lik
e
g
ain
enhancement
and
stability
.
The
approach
ensures
enhanced
O
T
A
performance
while
adhering
to
t
he
DTMOS
process
specications.
Inte
grating
design
principles,
optimization
algorithms,
and
performance
e
v
aluation
demonstrates
the
ef
cac
y
of
the
Firey
algorithm
in
analog
circuit
design,
adv
ancing
the
tw
o-stage
DTMOS
O
T
A
optimization.
The
detailed
o
w
chart
to
optimize
a
DTMOS
tw
o-stage
operational
transconductance
amplier
for
biomedical
applications
using
the
Firey
algorithm
is
illustrated
in
Figure
2.
Figure
2.
Block
diagram
of
DTMOS
O
T
A
optimization
using
Firey
algorithm
As
in
Figure
3,
initially
,
the
algorithm
starts
with
the
initialization
of
parameters
such
as
the
number
of
reies,
the
maximum
iterations,
and
the
initial
positions
of
the
reies.
F
ollo
wing
this,
a
random
population
of
reies
representing
dif
ferent
potential
solutions
for
the
analog
circuit
is
generated.
Each
Firey’
s
tness
is
then
e
v
aluated
based
on
its
corresponding
analog
circuit’
s
performance.
This
e
v
aluation
considers
v
arious
metrics
lik
e
g
ain,
bandwidth,
or
po
wer
consumption,
depending
on
the
design
requirements.
Subsequently
,
the
brightness
of
each
rey
is
calculated
based
on
its
tness,
where
higher
tness
results
in
brighter
reies.
Fireies
then
mo
v
e
to
w
ards
brighter
ones
iterati
v
ely
,
simulating
the
ashing
beha
vior
of
reies
in
nature.
The
mo
v
ement
intensity
is
determined
by
both
the
bri
ghtness
of
the
tar
get
rey
and
the
distance
between
them.
After
the
mo
v
ement
phase,
the
tness
of
the
updated
positions
is
re-e
v
aluated,
and
the
brightness
is
recalculated
accordingly
.
This
process
continues
iterati
v
ely
until
a
termination
condition
is
met.
T
ermination
conditions
may
include
reaching
a
maximum
number
of
iterations
or
nding
a
satisf
actory
solution.
Once
the
termination
condition
is
satised,
the
algorithm
outputs
the
best
solution
found,
representing
the
optimized
analog
circuit
design.
In
summary
,
the
o
wchart
for
opt
imizing
an
analog
circuit
using
the
Firey
algorithm
in
v
olv
es
parameter
initialization,
populati
o
n
generation,
tness
e
v
aluation,
brightness
calculation,
iterati
v
e
mo
v
ement,
tness
re-e
v
aluation,
termination
condition
check,
and
output
of
the
best
solution.
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
16,
No.
3,
September
2025:
1417–1428
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
❒
1423
T
able
1
sho
ws
the
information
stored
in
the
”
T
r
ansistor
−
D
etail
s
.csv
”
le
represents
tw
o
s
ets
of
data:
the
initial
and
optimized
W/L
(width/length)
ratios
of
transistors
in
an
analog
circuit.
The
initial
v
alues
reect
the
W/L
ratios
before
an
y
optimization
process
has
been
applied,
while
the
optimized
v
alues
indicate
the
W/L
ratios
obtained
after
optimization.
These
data
serv
e
as
a
record
of
the
circuit’
s
conguration
before
and
after
optimization,
allo
wing
for
comparison
and
analysis
of
the
ef
fecti
v
eness
of
the
optimization
process.
The
initial
v
alues
pro
vide
a
baseline
reference,
while
the
optimized
v
alues
demonstrate
the
adjustments
made
during
optimization
to
enhance
the
circuit’
s
performance
according
to
specied
criteria.
Figure
3.
Flo
wchart
for
analog
circuit
optimization
with
Firey
algorithm
T
able
1.
Analysis
of
transistor
W/L
ratios
V
ariable
Initial
W/L
Optimized
W/L
V
ariable
Initial
W/L
Optimized
W/L
m23
21
17.07u
m16
1.2
1.15u
m22
10.5
3.09u
m18
3.6
0.21u
m7
1.2
0.27u
m14
9.6
6.86u
m8
1.2
1.17u
m12
1.2
0.82u
m9
10.5
4.97u
m13
2.4
1.25u
m1
1.2
1.04u
m19
4.8
3.84u
m2
1.2
0.35u
m24
14.4
1.09u
m3
10.5
0.77u
m25
1.2
0.50u
m4
42
19.58u
m11
7.2
2.10u
m10
1.2
1.14u
m5
1.2
0.26u
m6
1.2
1.19u
m21
1.2
0.40u
m17
1.2
0.66u
m15
1.2
0.41u
m20
1.2
0.22u
5.
RESUL
T
AND
DISCUSSION
The
optimization
process
embark
ed
upon
a
journe
y
that
commenced
with
the
meticulous
parsing
of
the
netlist
le
and
culminated
in
the
storage
of
optimized
v
alues,
of
f
ering
profound
insights
into
the
algorithm’
s
ef
cac
y
and
the
resultant
circuit
performance
enhancements.
At
ea
ch
phase
of
this
journe
y
,
we
Optimization
of
two-sta
g
e
DTMOS
oper
ational
tr
ansconductance
amplier
...
(Udari
Gnaneshwar
a
Chary)
Evaluation Warning : The document was created with Spire.PDF for Python.
1424
❒
ISSN:
2088-8694
delv
ed
into
the
outcomes,
elucidating
the
observ
ed
transformations
and
their
implications.
Upon
parsing
the
netlist,
the
algorithm
meticulously
e
xtracted
critical
circuit
parameters—transistor
names,
width
(w),
and
length
(l)
v
alues,
forming
the
bedrock
for
subsequent
optimization
endea
v
ours.
These
details
were
systematically
catalogued
in
the
”
T
r
ansistor
−
D
etail
s
.csv
”
le,
which
is
as
sho
wn
in
T
able
2,
ensuring
comprehensi
v
e
documentation
essential
for
thorough
circuit
analysis.
The
algorithm
laid
the
groundw
ork
for
subsequent
optimization
processes
by
capturing
these
parameters.
Subsequently
,
based
on
the
parsed
circuit
parameters,
the
algorithm
computed
k
e
y
performance
metrics,
number
of
transistors,
total
transconductance,
o
v
erall
g
ain,
and
po
wer
ef
cienc
y
.
Serving
as
benchmarks,
these
metrics
pro
vided
v
aluable
insights
into
the
circuit’
s
initial
state,
f
acilitating
the
e
v
aluation
of
the
optimization
process’
s
ef
fecti
v
eness.
Succinctly
summarized
and
stored
in
the
”
C
ir
cuit
−
S
ummar
y
.csv
”
le,
these
metrics
enabled
easy
access
and
interpretation
of
the
circuit’
s
o
v
erall
performance
characteristics.
The
algorithm
diligently
rened
transistor
congurations
as
the
optimization
journe
y
progressed
to
bolster
circuit
performance.
Through
iterati
v
e
renement,
optimized
width/length
(W/L)
ratios
for
each
transistor
were
computed,
leading
t
o
substantial
impro
v
ements
in
circuit
g
ain
and
ef
cienc
y
.
These
optimized
ratios
replaced
initial
v
alues
in
”
T
r
ansistor
−
D
etail
s
.csv
”
,
ensuring
accurate
documentation
of
the
latest
and
most
ef
fecti
v
e
transistor
congurations
for
future
ref
erence.
Furthe
rmore,
the
algorithm
deri
v
ed
optimized
o
v
erall
g
ain
and
po
wer
ef
cienc
y
metrics
from
rened
transistor
congurations.
These
indicators,
compared
to
”
C
ir
cuit
−
S
ummar
y
.csv
”
,
sho
wcas
ed
tangible
enhancements
post-optimization.
By
systematically
updating
performance
metrics
with
optimized
v
alues,
the
algorithm
highlighted
substantial
impro
v
ements
in
circuit
performance.
The
results
underscored
the
optimization
algorithm’
s
ef
cac
y
in
enhancing
circuit
performance,
e
videnced
by
signicant
g
ains
in
g
ain
and
ef
cienc
y
metrics.
Systematic
documentation
enabled
a
comprehensi
v
e
e
v
aluation
of
optimization
outcomes,
laying
the
groundw
ork
for
further
adv
ancements
in
analog
circuit
design
optimization.
The
resultant
t
able
of
the
proposed
w
ork
with
e
xisting
w
orks
in
terms
of
v
arious
parameters
is
outlined
in
the
follo
wing
T
able
2.
T
able
2.
Result
analysis
P
arameters
V
alues
Number
of
transistors
25
Initial
o
v
erall
g
ain
(A
v)
(V/V)
76.65
Initial
po
wer
ef
cienc
y
(
µ
)
1.6
Optimized
o
v
erall
g
ain
(A
v)
(V/V)
0.084023579
Optimized
po
wer
ef
cienc
y
(
µ
)
1.702
T
o
assess
the
ef
fecti
v
eness
of
the
Firey
algorithm
in
optimizing
analog
circuit
design,
a
thorough
comparati
v
e
study
w
as
undertak
en,
pitting
it
ag
ainst
v
arious
alternati
v
e
algorithms.
Figure
4
sho
ws
the
optimized
W/L
ratios
generated
by
dif
ferent
optimizati
on
algorithms.
This
in
v
estig
ation
sought
to
determine
whether
Firey
truly
stands
out
as
the
optimal
approach
for
analog
circuit
optimization
or
if
there
are
alternati
v
e
methods
that
might
of
fer
superior
performance.
The
resultant
table
of
t
he
proposed
w
ork
with
e
xisting
w
orks
in
terms
of
v
arious
parameters
is
outlined
in
the
follo
wing
T
able
2.
By
analyzing
the
performance
of
Firey
in
conjunction
with
algorithms
lik
e
particle
sw
arm
optimization,
cuck
oo
search,
and
ant
colon
y
optimization,
a
comprehensi
v
e
e
v
aluation
w
as
conducted
to
g
auge
their
indi
vidual
capacities
in
impro
ving
g
ain
and
op
t
imizing
po
wer
ef
cienc
y
in
analog
circuits.
The
data
pertaining
to
g
ain
and
po
wer
ef
cie
n
c
y
with
dif
ferent
algorithms
is
pro
vided
belo
w
for
reference
in
T
ables
3
and
4,
respecti
v
ely
.
The
Firey
algorithm
stands
out
as
the
premier
option
for
analog
circui
t
optimization,
e
xcelling
in
both
g
ain
enhancement
and
po
wer
ef
cienc
y
analysis
when
compared
to
alternati
v
e
algorithms
lik
e
particle
sw
arm
optimization,
cuck
oo
search,
and
ant
colon
y
optimization.
T
able
3
sho
ws
that
Firey
achie
v
es
a
remarkable
g
ain
of
84.029
dB,
surpassing
the
g
ains
obtained
by
other
algorithms
such
as
particle
sw
arm
optimization
(82.088
dB),
cuck
oo
search
(83.205
dB),
and
ant
colon
y
optimization
(80.981
dB).
This
underscores
Firey’
s
ef
fecti
v
eness
in
e
xploring
the
search
space
and
identifying
optimal
circuit
congurations
that
maximize
amplication
while
minimizing
distortion.
T
able
4
sho
ws
that
Firey
demonstrates
superior
po
wer
ef
cienc
y
with
a
score
of
1.702
in
po
wer
ef
cienc
y
analysis,
outperforming
particle
sw
arm
optimization
(1.727),
cuck
oo
search
(1.749),
and
ant
colon
y
optimization
(1.7593).
This
indicates
that
rey
not
only
enhances
g
ain
b
ut
also
achie
v
es
this
impro
v
ement
while
maintaining
optimal
po
wer
utilization,
making
it
particularly
suitable
for
ener
gy-ef
cient
analog
circuit
design.
Fir
ey’
s
ef
cac
y
stems
from
its
unique
characteristics
and
optimization
mechanisms,
including
its
sw
arm
intelligence
approach
Int
J
Po
w
Elec
&
Dri
Syst,
V
ol.
16,
No.
3,
September
2025:
1417–1428
Evaluation Warning : The document was created with Spire.PDF for Python.
Int
J
Po
w
Elec
&
Dri
Syst
ISSN:
2088-8694
❒
1425
inspired
by
the
ashing
beha
vior
of
reies
in
nature.
This
approach
enables
ef
cient
e
xploration
of
the
solution
space,
with
reies
con
v
er
ging
to
w
ard
optimal
solutions
o
v
er
successi
v
e
generations.
T
able
3.
Analysis
of
g
ain
ef
cienc
y
P
arameters
V
alues
Initial
g
ain
76.65
Firey
algorithm
84.029
Cuck
oo
search
algorithm
83.205
Ant
colon
y
optimization
algorithm
80.981
T
able
4.
Analysis
of
po
wer
ef
cienc
y
P
arameters
V
alues
in
nW
Initial
po
wer
ef
cienc
y
1.91
Firey
algorithm
1.702
P
article
sw
arm
optimization
algorithm
1.727
Cuck
oo
search
algorithm
1.749
Ant
colon
y
optimization
algorithm
1.7593
Figure
4.
Analysis
of
initial
W/L
ratios
to
the
optimized
W/L
ratios
Additionally
,
Firey’
s
simplicity
,
scalability
,
and
adaptability
mak
e
it
accessible
and
ef
fecti
v
e
for
v
arious
types
of
Analog
circuits,
including
ampliers,
lters,
and
mix
ed-signal
systems.
Its
adapti
v
e
nature
allo
ws
it
to
handle
dynamic
en
vironments
and
e
v
olving
design
requirements,
f
acilitating
iterati
v
e
renement
and
real-time
optimization
tasks.
Ov
erall,
Firey’
s
superior
performance
in
g
ain
enhancement
and
po
wer
ef
cienc
y
positions
it
as
the
preferred
choice
for
analog
circuit
optimization,
of
fering
designers
enhanced
performance,
ener
gy
ef
cienc
y
,
and
reliability
in
their
designs.
The
optimizat
ion
journe
y
,
from
parsing
the
netlist
l
e
to
storing
optimized
v
alues,
pro
vided
v
aluable
insights
into
the
ef
fecti
v
eness
of
the
algorithm
and
the
resulting
impro
v
ements
in
circuit
performance.
The
meticulous
documentation
of
transistor
congurations
and
performance
metrics
f
acilitated
easy
access
and
interpretation,
allo
wing
for
a
thorough
e
v
aluation
of
the
optimization
process’
s
outcomes.
These
results
pa
v
e
the
w
ay
for
continued
adv
ancements
in
analog
circuit
design
optimizat
ion,
dri
ving
inno
v
ation
and
progress
in
the
eld.
6.
CONCLUSION
The
paper
presents
a
comprehensi
v
e
methodology
for
optimizing
DTMOS
tw
o-stage
oper
ational
transconductance
ampliers
(O
T
As)
for
biomedical
applications
using
the
Firey
algorithm.
The
optimization
process
in
v
olv
es
dening
the
circuit
architecture,
implementing
the
Firey
algorithm,
e
v
aluating
tness
metrics,
Optimization
of
two-sta
g
e
DTMOS
oper
ational
tr
ansconductance
amplier
...
(Udari
Gnaneshwar
a
Chary)
Evaluation Warning : The document was created with Spire.PDF for Python.
1426
❒
ISSN:
2088-8694
and
v
alidating
the
optimized
O
T
A
design.
The
result
analysis
demonstrates
signicant
impro
v
ements
in
k
e
y
performance
metrics
such
as
g
ain,
bandwidth,
and
po
wer
consumption,
making
the
optimized
O
T
A
design
well-suited
for
biomedical
signal
processing,
neural
interf
aces,
and
wearable
healthcare
de
vices.
Through
simulation
results
and
statistical
analysis,
it
is
e
vident
that
the
Firey
algorithm
ef
fecti
v
ely
con
v
er
ges
to
optimal
O
T
A
congurations,
balancing
po
wer
ef
cienc
y
and
perf
o
r
mance
requirements.
The
comparison
with
baseline
designs
highlights
the
substantial
enhancements
achie
v
ed
through
the
optimization
process,
emphasizing
the
algorithm’
s
ef
cac
y
in
tackling
comple
x
optimization
problems
in
DTMOS
O
T
A
design.
Furthermore,
the
sensiti
vity
analysis
underscores
the
optimized
O
T
A
design’
s
rob
ustness
to
parameter
v
ariations,
ensuring
reliable
performance
under
dif
ferent
operating
conditions.
The
po
wer
-performance
trade-of
fs
re
v
eal
the
optimized
O
T
A
’
s
ability
to
achie
v
e
high
performance
while
maintaining
ener
gy
ef
cienc
y
,
crucial
for
battery-po
wered
biomedical
de
vices
and
implantable
applications.
The
v
alidation
through
ph
ysical
prototyping
or
hardw
are
implementation
conrms
the
real-w
orld
functionality
and
practicality
of
the
optimized
O
T
A
design,
v
alidating
the
simulation
results
and
supporting
the
algorithm’
s
applicability
in
actual
biomedical
applications.
In
conclusion,
the
paper
sho
wcases
the
ef
fecti
v
eness
of
the
Firey
algorithm
in
optimizing
DTMOS
tw
o-stage
O
T
As
for
biomedical
applications,
pro
viding
v
aluable
insights
into
the
design
methodology
,
performance
enhancements,
and
potential
applications
i
n
biomedical
signal
proces
sing,
wearable
healthcare
systems,
and
neural
interf
aces.
Future
research
directions
may
focus
on
further
optimization
techniques,
application-specic
custom
ization,
and
inte
gration
into
adv
anced
biomedical
de
vices
for
impro
v
ed
healthcare
outcomes.
FUNDING
INFORMA
TION
Authors
state
no
funding
in
v
olv
ed.
A
UTHOR
CONTRIB
UTIONS
ST
A
TEMENT
This
journal
uses
the
Contrib
utor
Roles
T
axonomy
(CRediT)
to
recognize
indi
vidual
author
contrib
utions,
reduce
authorship
disputes,
and
f
acilitate
collaboration.
Name
of
A
uthor
C
M
So
V
a
F
o
I
R
D
O
E
V
i
Su
P
Fu
Udari
Gnaneshw
ara
Chary
✓
✓
✓
✓
✓
✓
✓
✓
✓
Sw
athi
Mummadi
✓
✓
✓
✓
✓
✓
✓
Kakarla
Hari
Kishore
✓
✓
✓
✓
✓
✓
C
:
C
onceptualization
I
:
I
n
v
estig
ation
V
i
:
V
i
sualization
M
:
M
ethodology
R
:
R
esources
Su
:
Su
pervision
So
:
So
ftw
are
D
:
D
ata
Curation
P
:
P
roject
Administration
V
a
:
V
a
lidation
O
:
Writing
-
O
riginal
Draft
Fu
:
Fu
nding
Acquisition
F
o
:
F
o
rmal
Analysis
E
:
Writing
-
Re
vie
w
&
E
diting
CONFLICT
OF
INTEREST
ST
A
TEMENT
The
authors
state
no
conict
of
interest.
D
A
T
A
A
V
AILABILITY
The
data
a
v
ailability
is
not
applicable
to
this
paper
as
no
ne
w
data
were
created
or
analyzed
in
this
study
.
REFERENCES
[1]
A.
F
ortes,
L.
A.
da
Silv
a,
R.
A.
Domanski,
and
A.
Gi
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“T
w
o-stage
O
T
A
sizing
opt
imization
using
bio-inspired
algorithms,
”
J
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gr
ated
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aul,
“HWPSO:
A
ne
w
h
ybrid
whale-particle
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arm
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its
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”
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ence
,
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265–291,
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10.1007/s10489-018-1247-6.
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w
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September
2025:
1417–1428
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