Inter national J our nal of Recongurable and Embedded Systems (IJRES) V ol. 15, No. 1, March 2026, pp. 86 ∼ 96 ISSN: 2089-4864, DOI: 10.11591/ijres.v15.i1.pp86-96 ❒ 86 FPGA implementation and bit err or rate analysis of the f orward err or corr ection algorithms in v oice signals Ramjan Khatik, Afzal Shaikh, Shraddha Sawant, Pritika P atil Department of Electrical and Computer Engineering, School of Engineering and T echnology , Anjuman-I-Islam’ s Kalsekar T echnical Campus, Ne w P an v el, India Article Inf o Article history: Recei v ed Apr 1, 2025 Re vised Jan 21, 2026 Accepted Jan 24, 2026 K eyw ords: Con v olution encoding Field programmable g ate arrays Microblaze Spread spectrum V iterbi decoder ABSTRA CT The idea of codes (VITERBI) is broadly utili zed as a part of the wireless com- munication system as a result of their less comple x nature in the decoding of transmitted message. This paper attempt s to de v elop a performance analysis of the decoder by methods for bit error rate (BER) e xamination. The Galois eld- based decoder calculation is only utilized as a part of the communication sys- tems. The decoder calculation-based V iterbi based decoder is carried out using eld programmable g ate arrays (FPGA) and MA TLAB. This paper looks at the e x ecution e xamination of both the calculati ons. The recongurable processor called Microblaze on the Spartan 3E FPGA is utilized for this purpose. MA T - LAB based code is used to see the BER analysis after the FPGA implementation output. This is an open access article under the CC BY -SA license . Corresponding A uthor: Afzal Shaikh Department of Electrical and Computer Engineering, School of Engineering and T echnology Anjuman-I-Islam’ s Kalsekar T echnical Campus Ne w P an v el, Na vi Mumbai, India Email: afzal.aiktc@gmail.com 1. INTR ODUCTION In his landmark 1948 w ork, Shannon demonstrated that e v ery communication channel has a funda- mental upper bound on the amount of information that can be transmitted reliably , determined by the le v el of noise present in the system [1]. Although this theoretical limit established the best possible performance of an y coding strate gy , it did not pro vide a constructi v e method for achie ving it. V iterbi-based codes represent a f amily of block codes characterized by both long code lengths and randomized structure, and the y are kno wn to of fer near -optimal perform ance, operating within approximately 0.0045 dB of the Shannon limit [2]. Among the v arious decoding strate gies, message-pass ing techniques—commonly referred to as the sum–product or belief- propag ation (BP) algorithms—are the most widely adopted in man y implementations [3]-[8]. A fully parallel decoder performs the check-node update in one clock c ycle and the bit-node update in the ne xt, yielding a substantial increase in decoding throughput compared with serial architectures. Ho we v er , a major limitation of these decoders is their lack of e xibility: e xisting parallel implementations [9]-[12] cannot easily accommodate modications to code structure. An y change in code parameters, such as rate or de gree distrib ution, typically requires redesigning the routing between check and bit nodes, making adaptation to ne w code congurations dif cult. The Spartan-3E eld programmable g ate array (FPGA) Kit board features the one of a kind highlights of the Spartan-3E FPGA f amily and gi v es an adv antageous adv ancement board to embedded processing appli- cation. The Kit board features these highlights: the Micro blaze™ embedded processor soft core is a reduced J ournal homepage: http://ijr es.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 87 instruction set computer (RISC) adv anced for usage in Xilinx® Field Programmable Gate Arrays (FPGAs). Figure 1 demonstrates an utilitarian piece outline of the Micro blaze center [13]-[16]. Figure 1. MicroBlze core block diagram [13] Fully robotized age HDL design using the EDK Platgen/Simgen tools. Address range, b yt e-write enable count, information breadth, and tar get architecture are some of the design crit eria that af fect the number of BRAM primiti v es emplo yed. The memory block’ s Ports A and B can be link ed to the follo wing free BRAM interf ace controllers: on-chip memory (OCM), processor local b us (PLB), on-chip peripheral b us (OPB), and local memory b us (LMB). As long as the appropriate amount of byte-write enables are set up, it supports byte, half-w ord, and double w ord e xchanges [17]-[20]. 2. METHOD In this implementation, the v oice input is initially captured and transformed into te xt-based data wit hin MA TLAB, as presented in Figure 2. T w o v oice samples from dif ferent channels are processed independently . After interpolation with the spreading sequence, the spread signal under goes con v olutional encoding as de- scribed in the pre vious sections. The encoded symbols are then modulated using quadrature phase shift k e ying (QPSK), follo wed by the addition of additi v e white Ga ussian noise (A WGN) to simulate channel impairments. QPSK demodulation is performed to retrie v e the noisy tra n s mitted data. This processing pipeline is e x ecuted for a multichannel code di vision multiple access (CDMA) system, with all stages up to this point implemented in MA TLAB. The demodulated output is subsequently stored in te xt format for e xibility in further program- matic manipulation. Error correction is achie v ed through the V iterbi algorithm, whose output—representing the reconstructed information—is also sa v ed as a te xt le. Finally , the reco v ered signal is plotted in MA TLAB and compared with the original w a v eform to assess reconstruction accurac y [21]-[27]. 2.1. Flo w chart explanation In the design w orko w , the Xilinx Platform Studio inte grated within Xilinx ISE 10.1 emplo ys header les generated from v oice sam ples—such as those used in mobile CDMA systems—or from other signal sources processed through MA TLAB’ s signal processing en vironment. Embedded C is utilized to implement the V iterbi encoding procedure, with dedicated routines de v eloped for both the encoding and decoding oper - ations. The signal sampled in MA TLAB is con v erted into a header le and subsequently processed through the V iterbi encoder , after which QPSK modulation is applied. T o emulate wireless transmission conditions, additi v e noise is introduced into the modulated data stream. The corrupted signal is then subjected to QPSK demodulation, follo wed by V iterbi decoding to reco v er the transmitted information. Post-decoding, error de- FPGA implementation and bit err or r ate analysis of the forwar d err or corr ection ... (Ramjan Khatik) Evaluation Warning : The document was created with Spire.PDF for Python.
88 ❒ ISSN: 2089-4864 tection and correcti on mechanisms are e x ecuted. During the iterati v e error -correction stage, t he system’ s per - formance is assessed through t he computation of the bit error rate (BER) curv e and the peak signal-to-noise ratio (PSNR) of the reconstructed signal. Figure 2. Ov erall implementation o wchart 3. RESUL TS AND DISCUSSION From the capture windo w we can observ e that as v oice signal of frequenc y 24 kHz is been multiple x ed with PN sequence of sampled rate with 48 kHz to generate spreaded sequence as it will be suitable format to transmit o v er the netw ork, the abo v e tw o v oice signals with dif ferent PN sequences to ha v e tw o spreaded sequences with distinguish in manner . The rst windo w Figure 3 sho ws the tw o v oice signals with dif ferent consecuti v e le v els of frequencies around 24 kHz to be a spreaded sequences and it’ s beside the w a v eform sho ws that spreaded sequences with dif ferent pn sequences as sho wn in the w a v eforms. The QPSK modulation and demodulation of the spreaded signal as sho wn in Figure 4 with dif ferent w a v eforms, the spreaded signal will be ag ain feeding to the processor to obtain the encoded output as con v o- lution technique later it follo ws the signal w as gi v en to MA TLAB for applying the QPSK m od ul ation and the addition of A WGN noise through MA TLAB. Figure 3. Output w a v e form results for tw o input signals v oice1 and v oice 2 Int J Recongurable & Embedded Syst, V ol. 15, No. 1, March 2026: 86–96 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 89 Figure 4. Output w a v e form results for spreaded sequences for v oice 1 and v oice 2 The Figure 5 sho ws the w a v eform of the QPSK demodulated w a v eforms that include the noise addition by manually with kn o wn amount of noise in the form the equated v alues in the MA TLAB, particularly in QPSK demodulation the signal is mix ed with the orthogonal basis functions in matched lters. The result obtained from matched lters are ag ain tested with the decision de vices, decision. Finally the outputs from decision de vices are ag ain multiple x ed to get spreader message signal which under goes de-spreading in CDMA recei v er . Spread-spectrum in telecommunications usually a t echnique called signal structuring technique that mak es direct sequence and frequenc y hopping on these signals. Similarly as Figure 6 sho ws that, the tw o de spreaded sequences of v oice signal 1 and v oice signal 2 can be used for multiple access or multiple functions, from the abo v e recei v ed signal from the CDMA the de spreaded sequences for the v oice signal 1 and v oice signal 2 as sho wn belo w . Figure 5. Output w a v e form results in binary sequence FPGA implementation and bit err or r ate analysis of the forwar d err or corr ection ... (Ramjan Khatik) Evaluation Warning : The document was created with Spire.PDF for Python.
90 ❒ ISSN: 2089-4864 Figure 6. De-spreaded w a v e form signals in binary sequence The demodulated signal is subsequently processed by the V iterbi algorithm for decoding, ensuring that the computational comple xity does not e xceed t hat of the con v entional V iterbi decoder while progressi v ely minimizing bit-le v el errors across iterations. In traditional wireless communication systems, transmitted signals occup y a x ed carrier frequenc y—typically in the me g ahertz or gig ahertz range—which remains constant o v er time. F or instance, when tuning to an FM radio station, the recei v er displays the same carrier frequenc y at an y instant. Because the carrier frequenc y in such systems is stable, the corresponding bandwidth remains conned within predened limits, enabling straight forw ard signal identication and e xtraction by an y intended recei v er . In a similar manner , Figure 7 sho ws the w a v eform that illustrates the spreaded sequences of the rst input v oice signal and Figure 8 illustrates the spreaded s equence of the Second input v oice signal transmitted within a specied frequenc y range, which denes the structure of the spread-spectrum sequence used in this implementation. Figure 7. Spreadeed sequence w a v e form of binary sequence user1 Int J Recongurable & Embedded Syst, V ol. 15, No. 1, March 2026: 86–96 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 91 Figure 8. Spreaded sequence w a v e form of user2 signal In Figure 9, QPSK modulation, tw o orthogonal sinusoidal carriers are emplo yed to represent the modulation basis functions. The modulation process is car ried out by altering the phase of these carriers in accordance with the incoming message symbols. Figure 9. QPSK modulation of signal1 and signal2 In the QPSK demodulation stage, coherent detection is emplo yed to ensure accurate reco v ery of the transmitted signal. This technique requires kno wledge of the carrier frequenc y and phase at the recei v er , which is achie v ed through the use of a phase -lock ed loop (PLL). The PLL synchronizes with the incoming carrier , maintaining lock on the frequenc y and tracking an y v ariations in both frequenc y and phase. Once synchro- FPGA implementation and bit err or r ate analysis of the forwar d err or corr ection ... (Ramjan Khatik) Evaluation Warning : The document was created with Spire.PDF for Python.
92 ❒ ISSN: 2089-4864 nization is established, the recei v ed w a v eform is multiplied by t he locally generated reference carriers for demodulation. The resulting demodulated signals, plotted at dif ferent operating frequencies, are illustrated in the Figure 10. Figure 10. QPSK demodulation of signal1 and signal2 A MA TLAB-based simulation w as performed for the CDMA s ystem in which the input signal w as spread using a PN sequence. The spread signal w as then transferred to the MicroBlaze processor to generate the con v olutionally encoded data. This encoded output w as subsequently returned to MA TLAB, where QPSK modulation and A WGN channel noise were applied. The QPSK-demodulated si gnal w as then fed back to the MicroBlaze processor for V iterbi decoding. The decoded data were passed through the CDMA de-interlea ving stage, after which BER performance analysis w as conducted. The corresponding results are summarized in T ables 1 and 2. T able 1. Bit error reduction of v oice signal for addition of 10 dB noise le v el with dif ferent code rates Code rate V oice input signal Reduced error bit le v el by decoder BER in percent (%) BER in ef cienc y 1 2 6528 2024 33.76 66.33 1 3 6528 1332 20.40 79.66 2 3 6528 1908 29.22 70.81 T able 2. T ab ulated results for V iterbi decoding of 1 3 code rate for dif ferent noise le v el A WGN in dB Input signal bits Error bits BER in percent (%) BER in ef cienc y -10 179274 76321 42.57 66.33 -5 179274 46943 26.18 73.82 -3 179274 25864 0.144 99.855 5 179274 2 0.00001 99.9999 Figure 11 sho ws the plot of BER with signal to noise ratio in DB for ½ code rate results in MA TLAB, from the graph we can say from this rate the BER achie v ement le v el is around 33%. Int J Recongurable & Embedded Syst, V ol. 15, No. 1, March 2026: 86–96 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Recongurable & Embedded Syst ISSN: 2089-4864 ❒ 93 Figure 11. BER for 1 2 code rate Similarly the Figure 12 also sho ws the plot of BER with signal to noise ratio in dB for 1/3 code rate results dra wn in MA TLAB, from the graph we can say from this code rate the BER achie v ement le v el is around 29%, hence in comparing to ½ code rate reduction of error rate is higher . Figure 12. BER for 1 3 code rate Similarly the Figure 13 snap also sho ws the plot of BER with signal to noise ratio in dB for 2/3 code rate results dra wn in MA TLAB, from the graph we can say from this code rate the BER achie v ement le v el is around 29%, so we can conclude from the abo v e observ at ion among all three code rates the ½ code rate is the best as it is higher rate in reduction of error bits. FPGA implementation and bit err or r ate analysis of the forwar d err or corr ection ... (Ramjan Khatik) Evaluation Warning : The document was created with Spire.PDF for Python.
94 ❒ ISSN: 2089-4864 Figure 13. BER for 2 3 code rate 4. CONCLUSION Based on the abo v e literature surv e y , analysis and de v elopment for implementing the abo v e mentioned concept and implementation of the mult iuser CDMA in MA TLAB and the encoder and decoder implementa- tion on Micro blaze processor follo wed with the QPSK modulation and demodulation on MA TLAB, we can conclude from the results obtained as tab ulated in section 5 for the encoder follo wed by V iterbi decoder with Microblaze processor , it is concluded that e v en for a v ery long data of length about more than one lakh samples tak en from the v oice signal and analyzed in terms of ho w BER v aries with change in A WGN noise le v el for ½, 1/3 and 2/3 code rates. This paper has also analyzed the error reduction with the cumulated order on sample selection. This infers that the BER has reduced v ery much 99.99% while using ½ encoding code rate. FUNDING INFORMA TION Authors state no funding in v olv ed. A UTHOR CONTRIB UTIONS ST A TEMENT This journal uses the C on t rib utor Roles T axonomy (CRediT) to recognize indi vidual author contrib u- tions, reduce authorship disputes, and f acilitate collaboration. Name of A uthor C M So V a F o I R D O E V i Su P Fu Ramjan Khatik ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ Afzal Shaikh ✓ ✓ ✓ ✓ ✓ ✓ ✓ Shraddha Sa w ant ✓ ✓ ✓ ✓ ✓ ✓ ✓ Pritika P atil ✓ ✓ ✓ ✓ ✓ ✓ ✓ C : C onceptualization I : I n v estig ation V i : V i sualization M : M ethodology R : R esources Su : Su pervision So : So ftw are D : D ata Curation P : P roject Administrati on V a : V a lidation O : Writing - O riginal Draft Fu : Fu nding Acquisition F o : F o rmal Analysis E : Writing - Re vie w & E diting Int J Recongurable & Embedded Syst, V ol. 15, No. 1, March 2026: 86–96 Evaluation Warning : The document was created with Spire.PDF for Python.
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FPGA implementation and bit err or r ate analysis of the forwar d err or corr ection ... (Ramjan Khatik) Evaluation Warning : The document was created with Spire.PDF for Python.