Inter national J our nal of P o wer Electr onics and Dri v e System (IJPEDS) V ol. 17, No. 1, March 2026, pp. 553 ∼ 571 ISSN: 2088-8694, DOI: 10.11591/ijpeds.v17.i1.pp553-571 ❒ 553 High v oltage asymmetric con v erter f or electr ostatic particle accelerators Diego Alberto F anego 1 , Orlando Silvio Sandini 1 , Her n ´ an Emilio T acca 1 , Andr ´ es J uan Kr einer 2 1 Uni v ersidad de Buenos Aires, F acultad de Ingenier ´ ıa, Laboratorio de Control de Accionamientos, T racci ´ on y Potencia (LABCA TYP), Buenos Aires, Ar gentina 2 Gerencia de In v estig aci ´ on y Aplicaciones, Comisi ´ on Nacional de Ener g ´ ıa At ´ omica (CNEA), Buenos Aires, Ar gentina Article Inf o Article history: Recei v ed Jun 30, 2025 Re vised Dec 23, 2025 Accepted Jan 23, 2026 K eyw ords: Asymmetric DC-DC con v erter topologies Electrostatic particle accelerators F orw ard-yback con v erters High v oltage po wer supplies Mer ged topology con v erters Po wer electronics ABSTRA CT This w ork presents se v eral topologies of asymmetric high v oltage con v erters for electrostatic particle accelerators. The options are compared on the basis of their transfer functions and the magnetic components required, and the most suitable for the intended purpose is selected. Simulations and measurement results of the prototype, which has symmetrical v oltage output and soft switching in the main trans istor , are presented. The prototype b uilt features output v oltages of 10 kV and -10 kV , the con v erter uses a single common command ground for the transistors s implifying its dri v ers, and also by means of the presented snubber circuit it reco v ers ener gy during soft switching. This is an open access article under the CC BY -SA license . Corresponding A uthor: Die go Alberto F ane go Uni v ersidad de Buenos Aires, F acultad de Ingenier ´ ıa, Laboratorio de Control de Accionamientos T racci ´ on y Potencia (LABCA TYP) A v . P aseo Col ´ on 850 (C1063A CV), Ciuda Aut ´ onoma de Buenos Aires, Ar gentina Email: df ane go@.uba.ar 1. INTR ODUCTION P article accelerators are machines that use electromagnetic elds t o deli v er kinetic ener gy to ions or electrons. Beams of these accelerated char ged part icles, can be used to interact with dif ferent materials, study their properties and produce m odications in a wide v ariety of ph ysical and biological systems. The ener gy le v el that a particle accelerator can reach ranges from kiloelectron v olt to teraelectron v olt. The spectrum of applications of these machines is e xtremely wide, including problem solving in medicine (radiotherap y and nuclear medicine), nuclear technology , microelectronics, materials science, en vironment al science and oil e xploration, among man y others [1]. Probably one of the most socially rele v ant applications is in the eld of human health, in the ght ag ainst cancer . Ion accelerators are an important alternati v e among therapies for the control of malignant tumors, reaching results that ha v e signicant adv antages o v er those obtained with con v entional g amma ray radiotherap y . These ion and neutron tumor control procedures go by the generic name of hadrontherap y . The ph ysical and radiobiological reasons for the superiorit y of hadrontherap y o v er con v entional radiotherap y in the treatment of certain tumors are related to the radi cally dif ferent w ay in which char ged hadrons deposit their ener gy in matter compared to g amma radiation. The penetration depth (range) of the char ged hadron beams is well dened and can be controlled, since it is a function of the initial ener gy of the projectile, accelerating the particles by means of electric elds [2]. J ournal homepage: http://ijpeds.iaescor e .com Evaluation Warning : The document was created with Spire.PDF for Python.
554 ❒ ISSN: 2088-8694 In nuclear ph ysics and technology there are tw o major types of machi n e s (and proces ses): nuclear reactors (based on nuclear ssion) and particle accelerators (based on char ged-particl e induced reactions). In recent years these tw o aspects ha v e be gun to be unied in h ybrid systems or accelerator dri v en systems (ADS), in which a beam of high-ener gy protons or deuterons incident on the right tar get produces v ery lar ge neutron ux es that are injected into a subcritical reactor . This principle is one of the most promising concepts for reducing the radiotoxicity of their w aste [1]. The other v ery rele v ant application of neutron producing accelerators is Boron neutron capture therap y (BNCT). P article accelerators mainly in v olv e tw o well dif ferentiated processes, on the one hand the g e neration of particles and on the other their acceleration. F or the latter , high electric elds are required, so the v oltage po wer supplies must be capable of deli v ering continuous high v oltages, with steps from tens to hundreds of kV , up to a total v oltage that can reach MV [3]–[5]. As most electrical loads, the electrostatic particle accelerators ha v e requirements of v oltage (order 1 MV to 2.5 MV) and current supply (order 10 mA to 100 mA). There are intermediate v oltage specications for acceleration electrodes and for the total operation v oltage which is the serial sum of all the intermediate supply v oltages. Moreo v er , electrostatic lenses are included to a v oid the dispersion of the particle beam (i.e. protons) due to repulsion between char ged particles (this is called space-char ge ef fect). These electrostatic lenses are po wered by other ancillary high v oltage po wer supplies and it is an usual requirement to use symmetrical po wer supplies to dri v e the electrostatic lenses. The topology here presented can be used to implement the main stage acceleration electrodes supplies and also the ancillary electrostatic lenses supplies (either single v oltage or symmetrical ones). This paper addresses high v oltage g e neration sources consisting of a cascade con v erter with a secondary rectier of the capaciti v e multiplier type [6]–[8]. In order to reduce the number of po wer de vices required, and thus impro v e reliability , it is preferred to a v oid symmetrical con v ersion topologies [9], [10]. There are man y approaches to implement this type of po wer supplies, some simple b ut without isolation [6], [11], [12] others including isolation b ut operating in discontinuous mode (DCM) [13]–[15] which is not desired in this case, where the objecti v e is to operate in continuous mode (CM) to achie v e a better utilization f actor of the semiconductors. The high v oltage po wer supplies presented here are primarily i ntended to be used in the elect rostatic particle accelerators current ly under de v elopment at the National Atomic Ener gy Commission (Comisi ´ on Nacional de Ener g ´ ıa At ´ omica - C.N.E.A., Rep. Ar gentina) and e v entually in equipment e xported to other countries (i.e. South K orea) [1], [16]. Moreo v er , these high-v oltage sources are also a fundamental part of the pulse generators for electroporation, since w orking with i ncreasingly narro wer pulses, on the order of tens of nanoseconds, the v oltage of these pulses must be raised to tens of kV [17]. This w ork focuses on the st udy of asymmetric high v oltage con v erters to be used mainly in electrostatic particle accelerators: i) In section 2 se v eral con v erter topologies are presented, their main adv antages and disadv antages are analyzed in order to select one and continue with the w ork; ii) Section 3 presents the simulations of the adopted con v erter; iii) Section 4 discusses the implementation of the prototype, the control strate gy and the measurements on the prototype. In addition, the snubber with ener gy reco v ery used in the prototype to achie v e soft switching is discussed in subsection 4.4. 2. HIGH V OL T A GE ASYMMETRIC DC-DC CONVER TERS Three con v erters with an asymmetrical primary circuit (with a single transistor) are presented theoretically , and the transfer function is determined analytically . Then, with the obtained results, an analysis will be carried out to determ ine the adv antages and disadv antages of each one. The most suitable for the application will be chosen, and on this basis the simulations and the construction of the prototype will continue. 2.1. Boost fed f orward-yback The proposed topology is an i mbricated con v erter , a forw ard-yback fed from a v oltage source through a boost inductor , which is sho wn in Figure 1(a). This arises from the series association of the Boost con v erter and the forw ard con v erter . This con v erter may operate in CM in order to obtain a better utilization of the po wer transistor . If the DCM is adopted [14], [15] some circuit simplication is allo wed b ut with higher transistor currents for the same output po wer . In the conduction time interv al of the transistor ( t O N ), the ener gy deli v ered by the primary source ( V E ) is partly stored in the boost inductor ( L B ) and the magnetizing inductance ( L m ), while another part is deli v ered to the load. During this time no current o ws through the magnetic reset diode ( D r m ). When the transistor Int J Po w Elec & Dri Syst, V ol. 17, No. 1, March 2026: 553–571 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 555 is open, current o ws through the diode D r m and the inductor L B deli v ers, together with the inducta nce L m , ener gy to the load. (a) (b) Figure 1. Boost fed forw ard-yback: (a) circuit with positi v e output and (b) circuit with complementary or ne g ati v e output The secondary part of the con v erter consists of a Greinacher (also kno wn as Cockcroft -W alton multiplier) v oltage doubler circuit [6], [9], [18], [19]. When the transistor is saturated, no current o ws through diode D s 1 , the current o ws through diode D s 2 dischar ging capacitor C s 1 and char ging capacitor C s 2 with the sum of the secondary winding v oltage n S and the v oltage on C s 1 . Finally , when the transistor i s block ed, diode D s 1 conducts char ging capacitor C s 1 through winding n S and capacitor C s 2 dischar ges through the load. Ne xt, the transfer function of the circuit will be obtained in analytic al form, this is necessary to e v aluate the circuit and then propose the control strate gy . The a v erage v oltage at the magnetizing inductance referred to the primary must be zero, therefore as in (1). v n P F D = V C S 1 n P n S (1 − D ) = ⇒ v n P F = 1 − D D V C S 1 n P n S (1) Where the duty c ycle is dened as D = t O N T and T is the total switching period. In the conduction time of the transistor , on the secondary circuit the output v oltage is as (2). V O = v n P F n S n P + V C S 1 (2) Using (1) results in (3). V O = 1 − D D V C S 1 n P n S n S n P + V C S 1 = ⇒ V C S 1 = D V O (3) Then (1) can be re written as (4). v n P F = (1 − D ) n P n S V O (4) At the boost inductor the a v erage v oltage also must be zero, therefore as in (5). D v L B F = (1 − D ) v L B R (5) In the conduction time of the transistor , as (6). v L B F = V E − v n P F (6) Using (4) results in (7). v L B F = V E − (1 − D ) n P n S V O (7) High volta g e asymmetric con verter for electr ostatic particle acceler ator s (Die go Alberto F ane go) Evaluation Warning : The document was created with Spire.PDF for Python.
556 ❒ ISSN: 2088-8694 When the transistor is block ed, and with (3), is obtained as (8). v L B R = n r n S V C S 1 = ⇒ v L B R = n r n S D V O (8) Then, the a v erage v oltage is as (9). D V E − (1 − D ) n P n S V O = (1 − D ) n r n S D V O (9) Finally , the output v oltage is as (10). V O = n S n r + n P 1 (1 − D ) V E (10) And from this, the transfer function is directly obtained. 2.1.1. Complementary output Gi v en the type of application for these circuits, electrostatic particle accelerators, it is interesting to determine what the transfer function of the circuit is for t he complementary output. The circuit is sho wn in Figure 1(b). The pre vious analysis is repeat ed, the a v erage v oltage at the magnetizing inductance referred to the primary must be zero, therefore as in (11). v n P F D = v n S R n P n S (1 − D ) (11) In the conduction time of the transistor , on the secondary side as (12). v n S F = V C S 1 = v n P F n S n P (12) And when the transistor is block ed as (13). V O = V C S 1 + v n S R (13) Combining both e xpressions gi v es as (14). v n S R = V O − v n P F n S n P (14) Using it in (11) gi v es as (15). v n P F = V O n P n S (1 − D ) (15) And also as in (16). v n S R = D V O (16) The a v erage v oltage at the boost inductor must be zero, its e xpression is the same as (5). In the conduction time of the transistor its v oltage is equal to (6), using (15) in it. v L B F = V E − (1 − D ) n P n S V O (17) When the transistor is block ed, and then using (16), gi v es as (18). v L B R = n r n S v n S R = ⇒ v L B R = n r n S D V O (18) Then, the a v erage v oltage has the same e xpression as (9) and the output v oltage is as (19). V O = n S n r + n P 1 (1 − D ) V E (19) It can be observ ed that the transfer is the same as in the pre vious case, which mak es the con v erter attracti v e for use in those cases where tw o complementary outputs with the same v oltage v alues are required using a single secondary winding and tw o rectier circuits. Int J Po w Elec & Dri Syst, V ol. 17, No. 1, March 2026: 553–571 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 557 2.1.2. Magnetizing curr ent F or further design of t he magnetic components it is important to determine the magnetizing cur rent ( I LM ), using the circuit sho wn i n Figure 1(a). The a v erage current in the capacitors C s 1 and C s 2 must be zero, therefore as (20). i S F D = i S R (1 − D ) (20) And as (21). i C S 2 F D = I O (1 − D ) (21) In the conduction time of the transistor , the current on the secondary side is as (22). i S F = i C S 2 F + I O (22) Using this in (21) gi v es (23). i S F = I O D (23) And using the latter in (20) gi v es (24). i S R = I O 1 − D (24) According to the principle of conserv ation of ener gy , if losses are ne glected: P O = V O I O = P E = V E I LB D = ⇒ I LB = V O I O V E D (25) When the transistor is block ed, the current through the magnetic reset winding and the current through the magnetizing inductance are in (26). i r R = I LB ∧ I LM = i P R (26) The magnetomoti v e force is as (27). m.m.f . = n S i S R − i r R n r − i P R n P (27) assuming an ideal transformer as (28). n S i S R = i r R n r + i P R n P (28) And using (24)–(26). I LM = n S n P I O (1 − D ) − V O I O V E D n r n P (29) Finally , using (10), the magnetizing current is as (30). I LM = n S n P I O (1 − D ) 1 − n r D ( n r + n P ) (30) An interesting aspect of the magnetizing current is to determine what v alues of the duty c ycl e mak e it zero, resulting in (31). D = n r n r + n P = ⇒ n r n P = D 1 − D (31) This last e xpression is important because the operation of the con v erter at this point cancels the magnetizing current, which minimizes the core dimensions and a v oids the increase of core losses associated with continuous bias magnetization [20], [21]. High volta g e asymmetric con verter for electr ostatic particle acceler ator s (Die go Alberto F ane go) Evaluation Warning : The document was created with Spire.PDF for Python.
558 ❒ ISSN: 2088-8694 2.2. Flyback fed f orward-yback This is an imbricated con v erter , a forw ard-yback fed from a v oltage source through the inductance of a yback subcon v erter , sho wn in Figure 2(a). It arises from the series association of the primary sides of a yback and a forw ard con v erter; the secondary sides transfer ener gy in parallel. In the condu c tion time interv al of the transistor , the ener gy deli v ered by the primary source ( V E ) is partly stored in the rst magnetizing inductance ( L m 1 ) and the second magnetizing inductance ( L m 2 ), whil e another part is deli v ered to the load. During this time, no current o ws through the yback diode ( D f ). When the transistor is open, current o ws through the diode D f and the inductance L m 1 deli v ers together with the inductance L m 2 ener gy to the load. The secondary part of the con v erter consists of a Greinache r v oltage doubler circuit. When the transistor is saturated, no current o ws through diode D s 1 , the current o ws through diode D s 2 dischar ging capacitor C s 1 and char ging capacitor C s 2 with the sum of the secondary winding v oltage n S and the v oltage on C s 1 . Finally , when the transistor is block ed, diode D s 1 conducts char ging capacitor C s 1 through winding n S and capacitor C s 2 dischar ge through the load. Using the same analysis as for the pre vious con v erter , the output v oltage is obtained as (32). V O = 1 n B D n r + n P n S 1 (1 − D ) V E (32) And from this, the transfer function is directly obtained. (a) (b) Figure 2. T w o topologies studied: (a) yback fed forw ard-yback circuit and (b) boost-yback fed forw ard-yback circuit 2.3. Boost-yback fed f orward-yback This is an imbricated con v erter , a forw ard-yback fed from a v oltage source t hrough the inductor of a boost-yback subcon v erter , sho wn in Figure 2(b). It arises from the series association of the boost-yback con v erter and the forw ard-yback con v erter . In the conduction time interv al of the transistor , the ener gy deli v ered by the primary source ( V E ) is partly stored in the boost inductor ( L mB ) and the magnetizing inductance ( L mp ), while another part is deli v ered to the load. During this time no current o ws through the magnetic reset diode ( D r m ). When the transistor is open, current o ws through the diode D r m and the inductor L mB returns ener gy to the source V E , the inductance L mp deli v ers ener gy to the load. The secondary part of the con v erter consists of a Greinacher v oltage doubler circuit. When the transistor is saturated, no current o ws through diode D s 1 , the current o ws through diode D s 2 dischar ging capacitor C s 1 and char ging capacitor C s 2 with the sum of the secondary winding v oltage n S and the v oltage on C s 1 . Finally , when the transistor is block ed, diode D s 1 conducts char ging capacitor C s 1 through winding n S and capacitor C s 2 dischar ge through the load. Using the same analysis as for the rst con v erter , the output v oltage is obtained as (33). V O = n S n P 1 (1 − D ) − n B D n r V E (33) And from this, the transfer function is directly obtained. Int J Po w Elec & Dri Syst, V ol. 17, No. 1, March 2026: 553–571 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 559 2.4. Con v erter comparison and selection The rst con v erter , called boost fed f o r w ard-yback and presented in subsection 2.1, requires a transformer with s plit primary and a bo os t inductor whose currents ha v e fundamental DC components. Ho we v er , according to (31), it w as determined that for a certain v alue of D, the magnetizing current of the transformer is zero and allo ws to reduce the core size and a v oid the need for a g ap. The second con v erter , called yback fed forw ard-yback and presented in subsection 2.2, requires tw o high v oltage transformers, which mak es it dif cult to b uild, especially the second transformer that requires a secondary winding with twice the v oltage of the rst one. The third con v erter , called boost-yback fed forw ard-yback and presented in subsection 2.3, requires tw o yback t ransformers of higher primary current than the other tw o circuits because when the transistor conducts it returns part of the ener gy to the primary source. This also w orsens the performance of the con v erter if the primary source is not fully re v ersible as in the case of a diode-capacitor bridge source. According to the e xpressions for the output v oltage of the con v erters, (10), (32) and (33), the possibility of v arying this v oltage is e v aluated. The rst con v erter , subsection 2.1, is the most limited in the range of v oltages obtained, while the third one, subsection 2.3, requires the smallest v ariation of the duty c ycle to obtain a wide range of v oltages. All topologies were analyzed theoretically and simulated numerically , and the rst one (boost fed forw ard-yback) w as adopted to i mplement the e xperimental con v erter prototype presented in t his w ork. The zero magnetization current operation condition will be adopted for the design in order to reduce the core losses due to DC magnetizing bias [20]. The possibility of ha ving a complementary output with the same transfer function is highly v alued for this application, while not being required to v ary the output v oltage o v er a wide range. In addition, soft switching in the transistor will be sought, which is discussed in subsection 4.4. 3. SIMULA TIONS The beha vior of the selected con v erter i s studied by simulating the ci rcuit through PSpice ® , and then comparing the results with those obtained analytically . F or the simulation, a primary DC v oltage source, V E , of 311 V is used, which corresponds to the rectied v oltage v al u e of a distrib ution netw ork with a rms v alue of 220 V . An output v oltage v alue, V O , of 1 kV and an output po wer of 500 W are adopted. The switching frequenc y is set at 35 kHz and a duty c ycle D at 0.5, since this is the optimum v alue studied if both primary windings are adopted equal according to (31). The circuit used in the simulation is sho wn in Figure 3(a). If the capacitors in the Greinacher capaciti v e multiplier ha v e small capacitance some current mi ght be dra wn through the diode D r m . Therefore, an auxiliary MOSFET transistor w as added in series with the magnetic reset diode to a v oid unw anted conduction during the conduction time of the main transistor . Both de vices are controlled in a complementary w ay . The auxiliary one, a lo w v oltage MOSFET , has lo w conduction losses and D r m must be maintained to a v oid conduction by the transistor’ s internal diode. The need for a oating v oltage source for the auxiliary transistor command will be solv ed later in the con v erter prototype. The resulting w a v eforms are sho wn in Figures 3(b)–3(e). 4. PR O T O TYPE IMPLEMENT A TION The prototype consists of a full-w a v e rectier formed by a four -diode bridge (50 A, 1 kV) follo wed by three electrolytic capacitors (470 µF , 400 V). Then follo ws the po wer stage formed by the selected con v erter feeding tw o v oltage multipliers to obtain the tw o symmetrical output v oltages. A double control stage for duty c ycle and frequenc y is used, as well as the necessary dri v ers to control both the main IGBT transistor and the auxiliary MOSFET [22]. 4.1. P o wer stage 4.1.1. Primary side In order to simplify the control circuit, the primary circuit of the con v erter w as reformed so that both the emitter of the IGBT and the source of the auxil iary MOSFET ha v e a common ground. This eliminates the need for an auxiliary oating source to dri v e the transistor . The reform can be seen in Figure 4(a). 4.1.2. V oltage multiplier T w o Greinacher (or Cockcroft-W alton) v oltage multipliers of 4 stages each were added to the con v erter , in order to obtain a source with complementary output v oltages of 10 kV with a po wer of 600 High volta g e asymmetric con verter for electr ostatic particle acceler ator s (Die go Alberto F ane go) Evaluation Warning : The document was created with Spire.PDF for Python.
560 ❒ ISSN: 2088-8694 W at each output. This is sho wn in Figure 4(b), where a secondary winding with intermediate point is used to obtain both outputs [9], [19], [23]. The capacitors used in the v oltage multipliers were of polyprop ylene dielectric, 500 V insulation v oltage. In the case of the rst stage, C s 1 , 3 capacitors of 1 µF had to be placed in series; then for C s 2 , 6 in series of 1 µF ; for C s 3 and C s 4 , 6 in series of 680 nF; for C s 5 and C s 6 , 6 in series of 470 nF; and nally for C s 7 and C s 8 , 6 in series of 100 nF . In order to k eep the tw o outputs stable, a double control circuit is used to control the duty c ycle on the one hand and the switching frequenc y on the other hand. F or this reason, the v alue of the rst capacitor , C s 1 neg , is modied to the ne g ati v e v oltage multiplier , decreasing it to 30 nF , making this multiplier more sensiti v e to frequenc y v ariations than the positi v e multiplier whose v oltage is controlled by v arying the duty c ycle. (a) (b) (c) (d) (e) Figure 3. Simulation results of the boost fed forw ard-yback con v erter: (a) circuit used in the simulation, (b) collector current, (c) collector v oltage, (d) magnetic reset diode current, and (e) output v oltage ripple Int J Po w Elec & Dri Syst, V ol. 17, No. 1, March 2026: 553–571 Evaluation Warning : The document was created with Spire.PDF for Python.
Int J Po w Elec & Dri Syst ISSN: 2088-8694 ❒ 561 (a) (b) Figure 4. Circuits used in the po wer stage: (a) modication carried out on the primary side of the con v erter and (b) the double v oltage multiplier 4.2. Contr ol strategy The main block of the control system w as implemented with the SG3524 inte grated circuit which has the necessary modules to perform a duty c ycle v ariation control loop. This standard, classic and widely used inte grated PWM controller w as intentionally adopted to demonstrate that the control method does not require special controllers with sophisticated features. A duty c ycle v ariation control w as used for the positi v e output and a switching frequenc y v ariation control w as used for the ne g ati v e output [24]. In an asymmetrical con v erter com p os ed of tw o sub-con v erters mer ged sharing a single po wer transistor , each sub-con v erter will ha v e its o wn transfer function that will gi v e the output DC v oltage as a function of the input v oltage of the primary source, t he duty c ycle, the switching frequenc y and the current of each output. Assuming that the input v oltage is the same for both sub-con v erters, it is possible to propose: V O 1 = f 1 ( D , f , I O 1 ) ∧ V O 2 = f 2 ( D , f , I O 2 ) (34) Where, V O 1 and V O 2 are the output DC v oltages; I O 1 and I O 2 are the currents deli v ered to each load; D is the duty c ycle; f is the switching frequenc y; and f 1 and f 2 are the transfer functions of each sub-con v erter . Under conditions where these transfer curv es are distinct functions and ha v e crossing points, the system of tw o equations formed by (34) will ha v e a solution, and there will be tw o v alues of duty c ycle and frequenc y which will be the s olution of the system of tw o nonlinear equations. Necessary b ut not suf cient conditions for the technique to be applicable are that the t ransfer functions be continuous and monotonic, since the e xistence of more than one crossing point will generate multiple solutions and therefore unstable operation. Each output v oltage will be fed back to a control loop that will ha v e its o wn dif ferential error am plier , so that the respecti v e error v oltages at the output of the ampliers will be (35). v E 1 = V O 1 − V O 1 ref ∧ v E 2 = V O 2 − V O 2 ref (35) Where, V O 1 ref and V O 2 ref are the desired output v oltages. Based on these error v oltages a duty c ycle and switching frequenc y should be generated such that the y are solution of the system of (34). That is, functions should be found such that as(36). D O = g D ( v E 1 , v E 2 ) ∧ f O = g f ( v E 1 , v E 2 ) (36) In pre vious w ork [24] it w as e xperimentally found that for usual forw ard, yback or their imbrications con v erters a practical solution can be found by adopting them as control action functions, as (37). D = g D ( v E 1 ) ∧ f = g f ( v E 2 ) (37) The functions g D and g f adopted in these references were feedback loops with inte gral and deri v ati v e compensations empirically adjusted to obtain the best possible transient beha vior under load v ariations. T o apply this control method to the proposed dual con v erter , the positi v e output v oltage is fed back with a f ast loop to v ary the duty c ycle, while the ne g ati v e output is fed back with a slo wer loop to v ary the switching frequenc y . F or this reason, the capaciti v e multiplier that generates the ne g ati v e v oltage has lo wer High volta g e asymmetric con verter for electr ostatic particle acceler ator s (Die go Alberto F ane go) Evaluation Warning : The document was created with Spire.PDF for Python.
562 ❒ ISSN: 2088-8694 capacitance so that the plant to be controlled by the slo wer loop is f aster and partly compensates for the slo wer speed of its control loop. In addition, this is necessary to ensure that the transfers of the sub-con v erters ha v e dif ferent slopes depending on the load currents and there is a crosso v er point to ensure that the system of equations has a solution and the operation is stable. According to [6] and [18] a Greinacher (or Cockcroft-W alton) v oltage multiplier has a monotonic transfer that is a function of frequenc y , duty c ycle and output current. T o ensure that the transfer functions corresponding to both capaciti v e multipliers ha v e a crosso v er point, the ne g ati v e multiplier is fed with a v oltage slightly higher than that applied to the positi v e (by adding turns in the respecti v e secondary). In this w ay , if the capacitors were all equal to each other , the ne g ati v e multiplier w ould al w ays gi v e an output v oltage which in modulus w ould al w ays be higher than that of the positi v e multiplier (and there w ould be no crosso v er point). T o ensure that the crosso v er point e xists, the con v erter is operated at the minimum frequenc y and the capacitance v alue of the ne g ati v e multiplier input capacitor C s 1 neg (see Figure 4(b)) is reduced until the modulus of the ne g ati v e v oltage is lo wer than that of the positi v e v oltage. Under these conditions, at minimum frequenc y the modulus of the ne g ati v e v oltage will be lo wer than that of the positi v e v oltage, and on the contrary , at maximum frequenc y the modulus of the ne g ati v e v oltage will be higher . 4.2.1. J oint contr oller f or duty cycle and switching fr equency The controller is an impro v ement of those initially proposed in [24]. The secondary side circuit (Figure 5) contains the error ampliers for the feedbac k of both output v oltages to be re gulated. Each amplier couples its error signal to the primary side (Figure 6) with g alv anic isolation by means of optocouplers. The non-linearity of these optocouplers has no major inuence because their transfer functions are included within tw o ne g ati v e feedback loops with high loop g ains [25]. The positi v e v oltage feedback signal controls the duty c ycle by means of the internal v oltage amplier of the SG3524 controller , while the error signal corresponding to the other supply output v aries the switching frequenc y by means of a bipolar transistor in parallel with the relaxation resistance of the RC oscillator of the PWM modulator inte grated circuit. The assembled prototype of the controller is sho wn in Figure 7(a). Figure 5. Circuit of the secondary side of the control stage Int J Po w Elec & Dri Syst, V ol. 17, No. 1, March 2026: 553–571 Evaluation Warning : The document was created with Spire.PDF for Python.